An 8–15 GHz Doherty Power Amplifier with a Compact Quadrature-Hybrid-Based Output Combiner in 22 nm FD-SOI

Abstract

A compact 8–15 GHz Doherty power amplifier (DPA) is proposed and fabricated in 22 nm FD-SOI CMOS. The proposed DPA relies on a quadrature-hybrid splitter and combiner to replace the bulky $\lambda$/4 impedance inverters at the input and the output of the conventional DPA enabling load modulation over a large fractional bandwidth (FBW = 61%) with efficient and compact integration. The proposed DPA achieves a peak gain of 19.6 dB; ≥17 dB across 8–15 GHz, 18 dBm P1dB, 19.5 dBm $P_{sat}$, and a peak PAE of 21% at 10 GHz, while sustaining 17% PAE at 6 dB back-off. The proposed DPA enables a modulation BW up to 200 MHz for a 256-QAM single carrier (SC) signal with a peak-to-average power ratio (PAPR) of 6 dB. Under this setting, the average output power (Pavg) is measured at 12.5 dBm with an RMS error vector magnitude (EVM) of $-24.1$ dB and an average PAE of 15%. Within the scope of CMOS power amplifiers in 22 nm FD-SOI, we found no published example that jointly demonstrates 8–15 GHz coverage and sustained PAE at 6 dB back-off using a quadrature hybrid.

1. Introduction

Next-generation microwave transmitters—including satellite payloads, phased arrays, and high-capacity backhaul—demand power amplifiers (PAs) that are both compact and efficient across wide frequency spans to enable low-cost, large-scale integration. Achieving these targets in nanoscale CMOS is challenging due to reduced supply voltages, device breakdown limits, and RF substrate losses that depress output power and power-added efficiency (PAE) [1].

At the highest power levels, high-efficiency PAs are frequently implemented in GaN HEMT technology because of its breakdown headroom and power density [2]. In parallel, a large portion of highly integrated front ends—beamforming and frequency-conversion chains—has moved to CMOS/FD-SOI, where area, integration, and multi-channel scalability are decisive. This work targets that CMOS integration space.

In silicon technologies, substrate-induced loss and parasitics in passives and interconnects are first-order constraints on achievable efficiency and bandwidth. Silicon-on-insulator (SOI) platforms alleviate loss compared with bulk CMOS; however, aggressive scaling of the buried oxide and metal stack can reintroduce attenuation and phase error in on-chip lines and networks. For example, in 22 nm FD-SOI, on-chip transmission lines may incur on the order of 0.5 dB/mm loss around 10–12 GHz, with commensurate phase dispersion that penalizes Doherty load modulation if not co-optimized [3].

The Doherty power amplifier (DPA) is a leading architecture for high efficiency at output back-off, but classical quarter-wave ($\lambda /4$) impedance inverters are area- and loss-prohibitive at X/Ku bands: even with slow-wave structures, $\lambda /4$ sections are millimeters long and introduce multi-dB loss, eroding PAE and narrowing bandwidth [4,5].

To mitigate these limits, prior works have replaced the single $\lambda /4$ inverter with (i) lumped or offset-line K/J-inverter and multi-section post-matching networks to flatten the Doherty load trajectory, and (ii) reconfigurable/tunable load-modulation networks—each trading complexity, area, or true broadband performance [6,7].

In parallel to passive load-modulation networks, dual-input (digital) Doherty PAs provide independent control of the main/auxiliary drives, enabling optimization of the back-off load trajectory and linearity via amplitude/phase coordination and algorithmic tuning (e.g., [8]). These approaches offer flexibility at the cost of added control complexity and calibration. The present work is complementary: we target a single-input architecture that preserves Doherty active-load modulation across 8–15 GHz using compact in/out quadrature hybrids, suitable for highly integrated CMOS front ends.

This work leverages a compact quadrature hybrid as a unifying element for both the input splitter and the output combiner, thereby realizing the load modulation for the Doherty operation while simultaneously improving bandwidth and reducing footprint. The fabricated DPA in GlobalFoundries 22 nm FD-SOI shows a continuous operating band from 8 to 15 GHz (Ku-band coverage in addition to X-band), aligning closely with electromagnetic and circuit co-simulations. Across this 8–15 GHz span, the proposed DPA maintains relatively high gain and back-off efficiency while benefiting from the hybrid’s inherent 90° phase balance and low insertion loss, enabling wideband load modulation without bulky $\lambda /4$ sections [9].

• Main contributions:

• A compact quadrature-hybrid-based Doherty topology that replaces lossy on-chip $\lambda /4$ inverters while preserving the Doherty load-line trajectory.
• Wideband 8–15 GHz-measured operation in 22 nm FD-SOI with maintained competitiveness with state-of-the-art CMOS DPAs.
• A passive co-design methodology that accounts for on-chip attenuation and phase dispersion to sustain hybrid balance and DPA linearity over a large fractional bandwidth.

This paper has been organized as follows. Section 2 briefly discusses the quadrature hybrids operating as impedance inverters for the DPA, while Section 3 provides an insight on the proposed DPA relying on the hybrid splitter/combiner. Measurements of the fabricated DPA have been presented in Section 4, which also provides a comparison with the state of the art. Finally, conclusions have been drawn in Section 5.

2. Quadrature Hybrids as Impedance Inverters: Robust DPA Operation Alongside Broader Bandwidth

A miniaturized quadrature-hybrid coupler is proposed as an alternative for the lossy $\lambda /4$ transmission lines in the conventional DPA, shown in Figure 1, to perform impedance inversion and coherent power combining/splitting. In this section we aim to validate the quadrature-hybrid combiner as an impedance inverter ensuring robust operation for the DPA, and to prove the broader bandwidth operation due to using a quadrature hybrid as a splitter/combiner instead of $\lambda /4$ transmission lines. In the end of this section, the layout of the proposed hybrid combiner is introduced associated with a brief characterization for that output combiner.

Figure 1. Block diagram of the conventional DPA.

2.1. Validation of DPA Load Modulation Using a Quadrature-Hybrid Combiner

We assume an ideal quadrature hybrid is used as an output combiner for a DPA. For this implementation, Port-1 to Port-4 are connected to the output of the main amplifier, the output of the auxiliary amplifier, the load, and 50 $\Omega$ termination, respectively.

With ports 3 and 4 terminated in $Z_0$, the four-port reduces to the driving-point two-port seen at ports 1–2 [10]:

$$\left[\begin{array}{c}{v}_1\\ v_2\end{array}\right]={\mathbf{Z}}_{\mathrm{hyb}}\left[\begin{array}{c}{i}_1\\ i_2\end{array}\right],\hspace{1em}{\mathbf{Z}}_{\mathrm{hyb}}={\displaystyle \frac{Z_0}{3}}\left[\begin{array}{cc}1& 2\sqrt{2}\mathrm{j}\\ 2\sqrt{2}\mathrm{j}& 1\end{array}\right].$$

(1)

Treat the PA outputs as Norton sources with main current $I_M$ and auxiliary current in quadrature $I_A=\mathrm{j}\rho I_M$ with $\rho \ge 0$:

$$I_A=\mathrm{j}\rho I_M.$$

(2)

Using (1) and (2) yields purely real driving-point loads at the drains:

$$Z_M^{\left(0\right)}\left(\rho \right)={\displaystyle \frac{Z_0}{3}}\left(1-2\sqrt{2}\rho \right),Z_A^{\left(0\right)}\left(\rho \right)={\displaystyle \frac{Z_0}{3}}\left(1+{\displaystyle \frac{2\sqrt{2}}{\rho }}\right).$$

(3)

As depicted, by using a quadrature hybrid as an output combiner, the impedance seen at the drain of the main amplifier is inversely proportional to the auxiliary amplifier current. This is similar to the load modulation when the $\lambda /4$ transmission lines are used as impedance inverters in the conventional DPAs [11] as shown in Figure 2.

Figure 2. Conceptual active-load modulation in a two-way Doherty PA.

However, Equation (3) shows that $Z_A^{\left(0\right)}\left(\rho \right)>0$ for all $\rho >0$, while $Z_M^{\left(0\right)}$ crosses zero at ${\rho }_0=1/\left(2\sqrt{2}\right)$. This apparent instability is a well-known theoretical limitation of the ideal model and the subsequent analysis shows it is not a practical concern. In fact, silicon non-idealities and finite output conductance of the main and the auxiliary amplifiers eliminate that instability condition.

Silicon non-idealities are captured by (i) a common insertion-loss factor $a\le 1$ (voltage) in the hybrid/passives, in that a small dissipative offset $r\ge 0$ referred to the ports, and (ii) a net auxiliary-path deficit factor $\kappa \in [0,1]$ (extra loss and/or gain imbalance). These map the physical ratio $\rho$ to an effective ratio at the drains:

$${\rho }_{\mathrm{eff}}=\kappa \rho ,\hspace{1em}0\le \rho \le n,\hspace{1em}0\le {\rho }_{\mathrm{eff}}\le \kappa n,$$

(4)

where $n\triangleq I_{max,A}/I_{max,M}$ is the physical sizing (aux/main). With loss only (no quadrature error), the baseline loads remain real:

$$Z_M^{\left(0\right)}\left({\rho }_{\mathrm{eff}}\right)={\displaystyle \frac{Z_0}{3}}\left(1+r-2\sqrt{2}a{\rho }_{\mathrm{eff}}\right),\hspace{1em}{Z}_A^{\left(0\right)}\left({\rho }_{\mathrm{eff}}\right)={\displaystyle \frac{Z_0}{3}}\left(1+r+{\displaystyle \frac{2\sqrt{2}a}{{\rho }_{\mathrm{eff}}}}\right).$$

(5)

Let $G_M>0$ and $G_A>0$ be the devices’ shunt output conductance at the main and auxiliary drains. The actual driving-point impedances are the parallel combinations

$$Z_M\left({\rho }_{\mathrm{eff}}\right)={\displaystyle \frac{Z_M^{\left(0\right)}\left({\rho }_{\mathrm{eff}}\right)}{1+G_M{Z}_M^{\left(0\right)}\left({\rho }_{\mathrm{eff}}\right)}},\hspace{1em}{Z}_A\left({\rho }_{\mathrm{eff}}\right)={\displaystyle \frac{Z_A^{\left(0\right)}\left({\rho }_{\mathrm{eff}}\right)}{1+G_A{Z}_A^{\left(0\right)}\left({\rho }_{\mathrm{eff}}\right)}}.$$

(6)

Since (5) are real, the exact real part reduces to

$$\Re \left\{Z_k\right\}={\displaystyle \frac{X_k+G_k{X}_k^2}{{(1+G_k{X}_k)}^2}},\hspace{1em}{X}_k\triangleq Z_k^{\left(0\right)}\in \mathbb{R},k\in \{M,A\},$$

(7)

so $\Re \left\{Z_k\right\}>0$ if $X_k+G_k{X}_k^2>0$.

In the 6 dB back-off peak PAE design, the reachable effective ratio is bounded as

$$0\le {\rho }_{\mathrm{eff}}\le {\rho }_{max}\approx \kappa n\approx 1.$$

(8)

The worst-case (most negative) baseline for the main occurs at ${\rho }_{\mathrm{eff}}={\rho }_{max}$:

$$X_{M,min}\equiv Z_M^{\left(0\right)}\left({\rho }_{max}\right)={\displaystyle \frac{Z_0}{3}}\left(1+r-2\sqrt{2}a{\rho }_{max}\right).$$

(9)

From (7), a single design-time bound on $G_M$ guarantees $\Re \left\{Z_M\right\}>0$ for all ${\rho }_{\mathrm{eff}}\in [0,{\rho }_{max}]$:

$$G_M>{\displaystyle \frac{1}{\left|X_{M,min}\right|}}={\displaystyle \frac{3}{Z_0\left(2\sqrt{2}a{\rho }_{max}-(1+r)\right)}}.$$

(10)

Because $a\lesssim 1$, $r\ll 1$ and ${\rho }_{max}\approx 1$, the threshold (10) is modest and the instability condition is eliminated; the auxiliary path is unconditionally positive since $Z_A^{\left(0\right)}\left({\rho }_{\mathrm{eff}}\right)>0$ for all ${\rho }_{\mathrm{eff}}>0$.

2.2. Why a Quadrature Hybrid Yields Wider Doherty Bandwidth than a $\lambda /4$ Inverter

(1)

$\lambda /4$ transmission line (characteristic impedance $Z_0$, terminated in a real $Z_L$) [12]

The impedance seen at the input is

$$Z_{\mathrm{in}}\left(\theta \right)=Z_0{\displaystyle \frac{Z_L+j{Z}_{0}tan\theta }{Z_0+j{Z}_{L}tan\theta }}.$$

(11)

At the design frequency $f_0$, the line is a quarter-wave (${\theta }_0=\pi /2$) and (11) reduces to the ideal real inversion $Z_{\mathrm{in}}=Z_0^2/Z_L$. For a small fractional detuning, write $\theta =\frac{\pi }{2}+\Delta$ with

$$\Delta \triangleq {\displaystyle \frac{\pi }{2}}\left({\displaystyle \frac{f}{f_0}}-1\right),\hspace{1em}|\Delta |\ll 1.$$

(12)

Using $tan\left(\frac{\pi }{2}+\Delta \right)=-cot\Delta$ and the series $cot\Delta =\frac{1}{\Delta }-\frac{\Delta }{3}+O\left({\Delta }^3\right)$, the input impedance expands to first order as

$$Z_{\mathrm{in}}\left(\theta \right)\approx {\displaystyle \frac{Z_0^2}{Z_L}}+j\Delta Z_0\left(1-{\displaystyle \frac{Z_0^2}{Z_L^2}}\right)+O\left({\Delta }^2\right).$$

(13)

Implication: The $\lambda /4$ inverter accumulates a reactive error that is linear in frequency detuning ($\propto \Delta \propto f/f_0-1$). In a Doherty, this dispersive reactance corrupts the intended real load-modulation and 90° phasing as we move off $f_0$, rapidly collapsing back-off efficiency over wide fractional bandwidth.

(2)

Quadrature hybrid (3 dB, 90°) across frequency

The driving-point matrix seen at the PA drains (ports 1–2) is

$${\mathbf{Z}}_{\mathrm{hyb}}\left(f\right)={\displaystyle \frac{Z_0}{3}}\left[\begin{array}{cc}1& j2\sqrt{2}a\left(f\right)[1+\epsilon \left(f\right)]e^{j\Delta \varphi \left(f\right)}\\ j2\sqrt{2}a\left(f\right)[1+\epsilon \left(f\right)]e^{j\Delta \varphi \left(f\right)}& 1\end{array}\right],$$

(14)

where $a\left(f\right)\le 1$ is the common (voltage) insertion factor, $\epsilon \left(f\right)$ a small coupling-magnitude ripple, and $\Delta \varphi \left(f\right)$ the quadrature phase error. With Doherty phasing $I_A=j\rho I_M$ ($\rho \ge 0$), the active-seen main impedance is

$$Z_{\mathrm{M}}(f,\rho )={\displaystyle \frac{Z_0}{3}}\left[1-2\sqrt{2}a\left(f\right)[1+\epsilon \left(f\right)]\rho e^{j\Delta \varphi \left(f\right)}\right].$$

(15)

For small errors ($\left|\epsilon \right|\ll 1$, $|\Delta \varphi |\ll 1$),

$$\begin{array}{cc}\hfill \Re \left\{Z_{\mathrm{M}}\right\}& \approx {\displaystyle \frac{Z_0}{3}}\left[1-2\sqrt{2}a\left(f\right)\rho cos\Delta \varphi \left(f\right)\right],\hfill \end{array}$$

(16)

$$\begin{array}{cc}\hfill \Im \left\{Z_{\mathrm{M}}\right\}& \approx -{\displaystyle \frac{Z_0}{3}}2\sqrt{2}a\left(f\right)\rho sin\Delta \varphi \left(f\right).\hfill \end{array}$$

(17)

Implication: The hybrid’s frequency dependence enters only through the small variations $a\left(f\right)$ and $\Delta \varphi \left(f\right)$. The reactive error is first order in a small angle $sin\Delta \varphi \left(f\right)$ (typically a few degrees), not first order in the detuning $\Delta$ as in (13). Thus, the hybrid preserves the Doherty load-modulation trajectories and near-90° phase balance across substantially larger fractional bandwidth.

(3)

Quantitative comparison at 8–15 GHz

Let $f_0=\frac{8+15}{2}=11.5$ GHz. At the band edges

$$\left|\Delta \right|={\displaystyle \frac{\pi }{2}}\left|{\displaystyle \frac{f}{f_0}}-1\right|={\displaystyle \frac{\pi }{2}} · {\displaystyle \frac{15-11.5}{11.5}}\approx 0.477\mathrm{rad}(\approx 27.3^{°}).$$

(18)

(a) $\lambda /4$ inverter: using (13) with, e.g., $Z_L=Z_0/2$ (a typical inversion ratio in Doherty), the reactive error magnitude at the edge is

$$|\Im \left\{Z_{\mathrm{in}}\right\}|\approx |\Delta |Z_0\left|1-{\displaystyle \frac{Z_0^2}{Z_L^2}}\right|=0.477 · 50 · \left|1-4\right|\approx 71.6 \Omega .$$

(19)

(b) Hybrid: with $a\left(f\right)\approx 0.9$, $\Delta \varphi \left(f\right)\approx 5^{°}=0.087$ rad, and $\rho \approx 1$ near the mid–high-power region, (17) gives

$$|\Im \left\{Z_{\mathrm{M}}\right\}|\approx {\displaystyle \frac{Z_0}{3}} · 2\sqrt{2}a\rho sin\Delta \varphi \approx {\displaystyle \frac{50}{3}} · 2.828 · 0.9 · 0.087\approx 3.7 \Omega .$$

(20)

Result: For the same wide 8–15 GHz span, the $\lambda /4$ inverter accumulates a reactive error on the order of ∼70 $\Omega$ (case-dependent via $Z_L$), whereas the hybrid’s reactive error stays at only a few ohms— more than an order of magnitude smaller. This directly translates to a far less distorted load-line and a wider back-off efficiency plateau with the hybrid.

(4)

Takeaways for Doherty bandwidth

(i) The $\lambda /4$ inverter embeds the $tan\theta$ dispersion, yielding a reactive error $\propto \Delta \propto (f/f_0-1)$; Doherty load modulation and the 90° condition degrade rapidly away from $f_0$. (ii) The quadrature hybrid’s driving-point law (15) is almost frequency-invariant to the first order; only small $a\left(f\right)$ and $\Delta \varphi \left(f\right)$ ripples appear, so the Doherty trajectories and phase quadrature are preserved across large FBW. Consequently, quadrature-hybrid combining is intrinsically wider-band for Doherty operation than $\lambda /4$-based inversion.

2.3. The Proposed Quadrature-Hybrid Combiner: Layout and Characterization

The proposed hybrid, shown in Figure 3, is designed using a branch-line topology with stacked microstrip lines. For this implementation, Port-1 to Port-4 are connected to the output of the main amplifier, the output of the auxiliary amplifier, the load, and 50 $\Omega$ termination, respectively.

Figure 3. Layout of the quadrature-hybrid combiner.

Load modulation is realized by designing the hybrid combiner to transform the load impedance from $R_L$ to $R_L/2$ from the start of operation of the auxiliary amplifier at 6 dB back-off to $P_{sat}$, an impedance transformation ratio of 0.5, when the outputs of the main and auxiliary amplifiers maintain a 90° phase difference.

Figure 4a shows the simulated impedance transformation ratio at the drain of the main amplifier versus the phase difference in the signals at the output of the main and auxiliary amplifiers at 10 GHz. As indicated, a transformation ratio of 0.5 is obtained at 90° phase difference. Simulation results in Figure 4b show that the hybrid achieves an insertion loss below 1.2 dB and a phase imbalance within ±3° across frequency from 8 to 15 GHz. This phase imbalance is consistent with the theoretical calculations in Section 2.2.

Figure 4. Quadrature-hybrid simulations. (a) Impedance transformation ratio vs. input phase difference. (b) Insertion loss and I/Q phase imbalance across frequency.

To quantify the compactness advantage of the quadrature hybrid as an impedance inverter, we synthesized a CPW $\lambda /4$ transmission line at 10 GHz. Only a short segment is shown in Figure 5 because the full line is ≈4 mm long (the free-space quarter wavelength would be ∼7.5 mm but on-chip ${\epsilon }_{\mathrm{eff}}\approx 3.5$). The CPW employs a 10 µm signal strip with ground rails placed 5 µm away on each side (rail width 10 µm), giving a total width ≈40 µm and an area $A_{\lambda /4}\approx 4$ mm $\times 40$ µm = 0.16 mm². In contrast, the quadrature-hybrid combiner occupies only ∼600 µm in length with 20 µm lines, corresponding to $A_{\mathrm{hyb}}\approx 600$ µm $\times 20$ µm = 0.012 mm², i.e., a footprint reduction of ≈$1-A_{\mathrm{hyb}}/A_{\lambda /4}\approx$ 92.5% ($\sim 13\times$ smaller).

Figure 5. A segment of a CPW $\lambda /4$ transmission line.

EM simulation results shown in Figure 6 indicate that the synthesized $\lambda /4$ inverter exhibits ≈$2.2\mathrm{dB}$ insertion loss and maintains the 90° phase shift only at $f_0$; the phase deviates by ∼30° at the band edges, consistent with Equation (18).

Figure 6. $\lambda /4$ impedance inverter simulations across frequency. (a) Insertion loss. (b) Phase shift from the input to the output.

These observations support the conclusion that replacing $\lambda /4$ lines with a quadrature hybrid (splitter/combiner) is key to a wideband DPA design. Also, the hybrid splitter/combiner has been proved as a more compact replacement for those lossy and bulky transmission lines.

3. The Proposed DPA: Design Details

The Doherty power amplifier employing the proposed hybrid is depicted in Figure 7.

Figure 7. Schematic diagram of the proposed DPA.

3.1. The Driver Stage

The driver stage employs a two-stacked FET differential amplifier for effective AM–AM linearization, operating from a 3 V supply. The width ($M_{11}$–$M_{14}$) is half that of the main-stage FETs, ensuring a 3 dB drive margin and improved PAE. A linearization loop senses the RF input and adjusts the gate bias, compensating AM–AM distortion in both the driver and the DPA [13].

The linearizer in Figure 8 senses the RF envelope and raises the $g_m$-device bias so that the DC current ramps with input level. As the input power increases, the gate $V_{\mathrm{rms}}$ of the $g_m$ FET rises, steering a small current through $R_{L1}$ and $R_{L2}$. This reduces the currents in $M_{L1}$–$M_{L3}$, causing the node $v_x$ to drop and engaging the feedback path formed by $M_{L4}$–$M_{L3}$ and $R_{L3}$–$R_{L4}$. The reduced current in $R_{L3}$/$R_{L4}$ drives more current in $M_{L4}$, which lifts $v_s$ and, in turn, restores $v_x$ toward a higher steady-state value. Nodes $v_y$ and $v_z$ follow until they track the gate $V_{\mathrm{rms}}$. The loop thus settles with elevated $v_y$/$v_z$, increasing the bias of the $g_m$ FET and providing additional current ramping. As a result, AM–AM linearity is preserved to higher output-power levels.

Figure 8. Schematic diagram of the linearization loop.

Figure 9 illustrates the AM–AM characteristics of the proposed DPA at 10 GHz, comparing performance with and without linearization. The linearized response maintains a nearly flat gain across output-power levels, demonstrating effective distortion suppression for both the driver and the output stages. A noticeable kink at 9 dBm corresponds to the activation of the auxiliary amplifier. In contrast, the non-linearized curve shows significant gain compression beyond 13 dBm, degrading rapidly at higher powers. This highlights the linearizer’s role in preserving signal integrity and extending usable dynamic range.

Figure 9. Simulated AM–AM at 10 GHz with and without linearizer.

The driver output is converted to a single-ended signal by a BALUN and then split by an input quadrature hybrid (identical topology to the output hybrid) to feed the main and auxiliary paths with a nominal $3\mathrm{dB}$ split and 90° phase difference. Using a quadrature hybrid at the input is deliberate: it preserves amplitude/phase balance over the 8–15 GHz span, stabilizes the Doherty drive ratio with frequency, and provides port isolation that desensitizes the main/auxiliary excitation to device and matching dispersion. Since it is identical to the output combiner, it tracks any change affecting the output combiner ensuring robust DPA operation against process variations.

The passive input network exhibits ≈4 dB insertion loss. The driver output matching (C₂₁, C₂₄) is co-optimized with the BALUN and the input hybrid for near-conjugate matching at the DPA input, ensuring consistent auxiliary turn-on and robust active-load modulation across band.

3.2. The DPA Stage

3.2.1. Target Power and Architecture

We begin the output-stage design by setting the saturated output power target $P_{\mathrm{sat}}$. For X/Ku-band applications (e.g., phased arrays and broadband links), low-to-mid $20\mathrm{dBm}$ transmitters in CMOS are practical. We therefore target a Doherty $P_{\mathrm{sat}}=21\mathrm{dBm}$. In our implementation, the main amplifier is dimensioned for $P_{\mathrm{sat}}\approx 18\mathrm{dBm}$; the auxiliary path then provides the ∼$3\mathrm{dB}$ uplift at high drive, yielding the overall $21\mathrm{dBm}$ after combination.

3.2.2. Stacking and Reliability

To ensure reliable operation at the chosen $P_{\mathrm{sat}}$ and given the ednFET drain breakdown of ∼$2.2\mathrm{V}$ in the GF 22 nm FD-SOI process [14], both the main and auxiliary PAs use a three-stacked-FET configuration with $V_{\mathrm{DD}}=3\mathrm{V}$. With proper voltage sharing, each FET sustains roughly $\sim 2{\mathrm{V}}_{\mathrm{pp}}$, so the stack accommodates $\sim 6{\mathrm{V}}_{\mathrm{pp}}$ overall—sufficient for the main stage to reach ≈$18\mathrm{dBm}$ and for the Doherty to attain ≈$21\mathrm{dBm}$.

3.2.3. Bias Classes

Conventional DPAs employ a Class B or Class AB main stage. Because achieving acceptable EVM without DPD is a design target here, we bias the main in Class AB (improved linearity relative to Class B, at a modest efficiency cost) and the auxiliary in Class C such that it is activated only near high output levels.

3.2.4. Device Sizing and Current Density

For the main amplifier, the current density is 100 µA/µm, which is slightly below the peak Ft current density of 120 µA/µm. This margin is maintained to safely operate within the electro-migration limits, especially after current ramping. This current density is chosen to achieve the target gain per stage which is 10 dB including all passive losses of that stage. By applying this current density across various sizes of the three stacked ednFETs, it was determined that a total current of 9 mA through 90 µm/24 nm stacked FETs results in a maximum deliverable output power that equals 18 dBm, given that the current ramps due to biasing in class AB, with a reasonable value for the optimum impedance that the drain has to be matched to, as shown later on. Each of the three stacked FETs ($M_{21}$–$M_{23}$) is divided into three equally sized units to prevent self-heating from exceeding 20 degrees Celsius above ambient temperature. Capacitor values ($C_{22}$–$C_{26}$) and bias points (Vbias 1–Vbias 3) were chosen carefully to adjust the voltage swings equally over the three stacked FETs.

3.2.5. Auxiliary Amplifier Sizing

For a two-way Doherty, the back-off efficiency knee is set by

$$B_{\mathrm{OBO},\mathrm{peak}}=20{log}_{10}\left(1+\kappa n\right).$$

(21)

In the ideal conventional DPA, the sizing of the main and the auxiliary PAs should be equal to get $B_{\mathrm{OBO},\mathrm{peak}}=6$ dB but realistic non-idealities enforce the FET size of the auxiliary amplifier to be larger than that of the main amplifier to achieve peak PAE at 6 dB back-off yielding the theoretical asymmetric DPA to achieve the theoretical PAE of the symmetric DPA. Figure 10 shows the simulated DPA PAE at 10 GHz versus the ratio between the FET size of the auxiliary amplifier and the FET size of the main amplifier (n). Also, Figure 10 compares the simulated PAE of the proposed DPA to the PAE of the class B PA. Choosing n = 2 causes the DPA to have superior PAE compared to the DPA of n = 1 and class B PA.

Figure 10. Simulated power-added efficiency at 10 GHz versus $P_{out}$ for a DPA with $n=2$, DPA with $n=1$, and Class B PA.

3.2.6. Load–Pull and Impedance Transformation

The drain impedances seen by the main and auxiliary cores are, to the first order, set by the quadrature hybrid and by the main/aux drive ratio, as given by (3). In practice, unavoidable parasitics and layout effects shift these ideal values, so we refined them via large-signal load–pull with the two cores directly combined (bypassing the hybrid). The simulation was performed at 11.5 GHz (mid-band point). Because the input/output quadrature hybrids maintain small amplitude/phase error and modest insertion loss ripple across 8–15 GHz, the Doherty load-modulation mechanism remains effective over the band. Consequently, the mid-band load-pull terminations serve as a practical design point for the entire span; only minor corrections are expected toward the band edges. This is consistent with the measured broadband S-parameters and large-signal trends.

As shown in Figure 11, to transmit the maximum deliverable power from the FETs configuration that was adopted (18 dBm), the main PA requires $Z_{M,\mathrm{opt}}\approx (75+j25)\Omega$ when the auxiliary is inactive and $Z_{M,\mathrm{opt}}\approx (50+j10)\Omega$ when the auxiliary is active.

Figure 11. Load–pull of the main PA directly connected to the auxiliary PA.

With the quadrature combiner terminated in $50 \Omega$, the main port instead sees ≈$50 \Omega$ when the auxiliary is idle (point C in Figure 11) and ≈$25 \Omega$ when it is engaged (point A). Consequently, the main output match is synthesized to transform $C:50 \Omega \to D:(75+j25) \Omega$ when the auxiliary is off, and $A:25 \Omega \to B:(50+j10) \Omega$ when it is on—thereby following the intended Doherty load-modulation trajectory. The auxiliary matching network presents approximately $R_{\mathrm{opt}}/2$ to the auxiliary drain at peak power, ensuring effective load modulation.

3.2.7. Efficiency Estimation

With the key design parameters fixed, we can make a data-driven efficiency prediction for the proposed DPA before validating it by simulation and measurement.

• Assumptions and sizing: The main PA is biased in Class AB with an assumed peak drain efficiency of $60\%$. Its target $P_{\mathrm{sat}}$ is $18\mathrm{dBm}$ ($63\mathrm{mW}$), implying a DC draw of $P_{\mathrm{DC},\mathrm{main}}=63/0.60\approx 105\mathrm{mW}$. At $V_{\mathrm{DD}}=3\mathrm{V}$ this corresponds to $I_{\mathrm{DC},\mathrm{main}}\approx 35\mathrm{mA}$. The auxiliary device is sized for twice the main current at peak power, and the driver is budgeted at half the main current; hence,

  $$I_{\mathrm{DC},\mathrm{tot}}=I_{\mathrm{main}}+I_{\mathrm{aux}}+I_{\mathrm{drv}}=35 \mathrm{mA}+70 \mathrm{mA}+17.5 \mathrm{mA}=122.5 \mathrm{mA},$$

  $$P_{\mathrm{DC},\mathrm{tot}}=V_{\mathrm{DD}}{I}_{\mathrm{DC},\mathrm{tot}}=3 \mathrm{V}\times 122.5 \mathrm{mA}=367.5 \mathrm{mW}.$$
• Predicted peak efficiency: The combined two-path target is $P_{\mathrm{sat}}=21\mathrm{dBm}$ ($126\mathrm{mW}$), giving an idealized peak drain efficiency of

  $${\eta }_{\mathrm{pk}}={\displaystyle \frac{P_{\mathrm{sat}}}{P_{\mathrm{DC},\mathrm{tot}}}}={\displaystyle \frac{126}{367.5}}\approx 0.343=34.3\%.$$
• Realistic expectation: Accounting for the measured loss of the output match and quadrature combiner (hybrid) leads to a practical peak efficiency around ∼$23\%$. This figure is intentionally conservative and will track upward with incremental loss reduction in the passive network and minor bias/drive tuning.

4. Measurements

The micrograph of the PA implemented in GF 22 nm FD-SOI is shown in Figure 12. The two-stage PA occupies 0.5 mm². RF and dc biasing signals are applied and monitored using on-wafer probing to reduce losses and mismatches introduced by measurements. Differential GSGSG pads are employed for the input, while single-ended GSG pads are utilized for the output. Figure 13 shows measured and simulated S-parameters where a peak gain of 19.6 dB is achieved with 3 dB small-signal gain bandwidth from 8 to 15 GHz.

Figure 12. DPA micrograph.

Figure 13. Measured versus simulated $S_{21}$, $S_{11}$, and $S_{22}$ for the proposed DPA.

The large-signal sweeps indicate that the DPA maintains its characteristic back-off efficiency improvement across the band as shown in Figure 14. The curves exhibit the expected rise in PAE as the auxiliary engages, followed by a peak near saturation.

Figure 14. Measured PAE versus $P_{out}$ at 10–14 GHz.

$P_{sat}$, shown in Figure 15, remains broadly consistent across the band as the maximum value is 19.6 dBm while the minimum is approximately 18 dBm, confirming that the combining network presents an optimum load to the core devices from 8 to 15 GHz. In practical terms, this means the design does not trade bandwidth for a narrow efficiency/saturation peak. The measured 1 dB compression point, shown in Figure 16, follows the same gentle frequency dependence as $P_{sat}$ as it constrained between 17 and 18 dBm across the band.

Figure 15. Measured versus simulated $P_{\mathrm{sat}}$ across frequency.

Figure 16. Measured versus simulated P1dB across frequency.

Peak PAE, reported at P1dB, varies less than 2% across frequency and reaches its maximum (21%) near mid-band as shown in Figure 17. Together with $P_{sat}$, this figure confirms the core premise: the hybrid-based network yields practical broadband efficiency.

Figure 17. Measured versus simulated peak PAE across frequency.

As depicted in Figure 18, PAE at 6 dB back-off remains consistently high across 8–15 GHz (varies between 17% and 15%), demonstrating that the Doherty mechanism is active and effective over the full span, not just near saturation.

Figure 18. Measured versus simulated PAE—6 dB back-off across frequency.

The AM–AM curves, Figure 19, show near-flat gain in the small-signal region and a smooth roll-off approaching compression, with a distinct knee when the auxiliary turns on.

Figure 19. Measured AM–AM at 8–10–13–15 GHz.

Figure 20 shows that the measured AM-PM of the PA exhibits less than 9 degrees at the P1dB of the PA. Since EVM under complex modulation is highly sensitive to AM–AM and AM–PM, the bounded and repeatable behavior across tones supports the linearity results that follow and provides an intuition for the observed ACLR/EVM trends across the respective wideband of operation.

Figure 20. Measured AM–PM: normalized phase versus $P_{out}$ at 10–14 GHz.

For modulated signal measurements shown in Figure 21 at 10 GHz, the PA exhibits an ACPR of $-30$ dBc for a 100 MHz single carrier (SC) 256-QAM signal at an average $P_{out}$ of 12.5 dBm with 15% average PAE. The absence of unexpected spectral shoulders or asymmetry suggests that memory effects are limited within the modulation bandwidth.

Figure 21. Measured ACPR for 256 QAM SC.

For the proposed modulation scheme at 10 GHz, EVM degrades gracefully with increasing output power reaching a maximum of −24.3 dB at the average Pout (7 dB back-off) and this gets elevated to −24.1 dBc at 200 MHz modulation bandwidth as shown in Figure 22. The small delta between the 100- and 200 MHz cases implies that frequency-dependent gain/phase ripple and bias dynamics are not significantly exacerbated by the wider signal, which strengthens the argument for bandwidth robustness.

Figure 22. Measured EVM (dB) versus $P_{\mathrm{out}}$ for 100–200 MHz modulation BW.

As depicted in Figure 23, when the same waveform is applied at several carrier frequencies, the EVM curves retain levels below −23.5 dB. This multi-frequency view indicates that the DPA’s wideband efficiency does not come at the expense of constellation quality.

Figure 23. Measured EVM (dB) versus $P_{\mathrm{out}}$ for 100 MHz modulation BW at 8–10–13–15 GHz.

Discussion and Synthesis

The measured wideband performance corroborates the role of the proposed in/out quadrature-hybrid networks in preserving Doherty active-load modulation (ALM) across frequency. Unlike $\lambda /4$ inverters whose impedance rotation is strongly frequency-selective, the hybrid pair maintains a benign amplitude/phase trajectory at both the input and output, stabilizing the composite load lines seen by the main and auxiliary paths. As a result, the DPA sustains efficiency at back-off over the entire 8–15 GHz span. Under modulated stimulus (256-QAM, 200 MHz, PAPR 7 dB), the average efficiency and EVM are consistent with the hybrid-enabled ALM, indicating that the frequency-robust drive split and output combining limit dispersion of the Doherty load trajectory. Together, these results validate the paper’s objective: the compact quadrature-hybrid technique is an effective means to realize a wideband CMOS DPA with preserved back-off efficiency and competitive linearity. Table 1 summarizes performance against state-of-the-art CMOS DPAs.

Table 1. Comparison with state-of-the-art CMOS PAs.

Spec/Ref.	This Work	[15] †	[16]	[17]	[18] †	[19] †
Technology	22 nm FD-SOI	45 nm CMOS SOI	65 nm Bulk CMOS	65 nm Bulk CMOS	22 nm FD-SOI	28 nm Bulk CMOS
Frequency (GHz)	8–15	12–18	8.5–9.5	8–11.4	27–29	24.5–29.5
FBW (%)	61	40	11.1	35	7.1	18.5
Gain (dB)	19.6:17	16	23.2	24.4	26.1	16.5
$P_{sat}$ (dBm)	19.5:18	25.5	20.9	20.5	22.5	18.8
P1dB (dBm)	18:17	25	16.5	15.2	21.1	17.5
Peak PAE (%)	21:19	31.9	24	24.5	28.5	30
BO PAE (%)	17:15	23	N/A	9	22.1	20
Supply (V)	3	2/4.8	3.3	1.2	2.4	1.8
Modulation	256 QAM SC	64 QAM SC	256 QAM SC	N/A	256 QAM SC	64 QAM SC
Data rate (MSym/s)	100	200	600	N/A	800	100
EVM (dB)	−24.3	−25	−35.9	N/A	−30	−25
Pavg (dBm)	12.5	16.4	12.7	N/A	10.2	12.4
BO level at Pavg (dB)	7	9.1	8.2	N/A	12.3	6.4
PAE% at Pavg	15	15	4.58	N/A	9	20
Die size (mm2)	0.5	1	0.22	0.48	0.2	0.16

Entries annotated by † are DPAs, FBW $={\displaystyle \frac{f_{max}-f_{min}}{f_0}}$ with $f_0={\displaystyle \frac{f_{max}+f_{min}}{2}}$.

5. Conclusions

A compact 8–15 GHz Doherty PA was proposed in 22 nm FD-SOI CMOS using a quadrature-hybrid-based output combiner in place of $\lambda$/4 inverters. A detailed analysis was presented to demonstrate the validity of quadrature hybrids in DPAs and their impact on the operating bandwidth. The DPA achieved 19.6 dB gain, 18 dBm P1dB, 19.5 dBm $P_{sat}$, 21% peak PAE, 17% PAE at 6 dB back-off, and an EVM of $-24.3$ dB for a 100 MSym/s 256 QAM single-carrier signal. Compared with prior CMOS DPAs, the proposed design offered robust performance in a larger FBW, highlighting the effectiveness of quadrature-hybrid combiners in mitigating loss and enhancing load modulation for broadband applications. The presented architecture offered scalability to millimeter-wave bands. Future work may explore adaptive biasing techniques and digital predistortion integration to further enhance linearity and efficiency across wider bandwidths and dynamic operating conditions. Additionally, extending this architecture to multi-band or reconfigurable PA designs could support emerging standards in next-generation wireless systems.