Search Results (156)

The growing demand for energy-efficient memory systems in artificial intelligence (AI) accelerators has intensified research into novel device technologies and computing-in-memory (CIM) architectures. While conventional binary SRAM architectures using CMOS and FinFET devices have been widely explored, ternary-based designs offer potential benefits in terms of storage density and computational efficiency. This work presents a low-power analysis of a sense-amplifier embedded (SE) 9-transistor (9T) ternary SRAM architecture implemented using Carbon Nanotube Field-Effect Transistors (CNFETs) and Gate-All-Around Field-Effect Transistors (GAAFETs). The comparative results show a substantial reduction in total power consumption—from 109.2 $\mathsf{\mu }$W in FinFET to 26.73 $\mathsf{\mu }$W in GAAFET—and an ultra-low power of only 0.0004 $\mathsf{\mu }$W in CNFET, representing a 99% reduction compared to FinFET designs. Similarly, the total delay decreases from 0.01108 ns in FinFET to 0.004 ns in GAAFET, while the CNFET design shows a modest delay of 0.017 ns. Overall, GAAFET offers the best trade-off between power and delay, whereas CNFET achieves the lowest power consumption, making it highly suitable for ultra-low-power AI applications. These findings emphasize the superior energy efficiency and scalability potential of CNFET- and GAAFET-based designs over traditional FinFETs, offering a promising pathway toward next-generation ternary CIM-enabled SRAM architectures. Furthermore, fabrication challenges related to CNFET and GAAFET technologies are discussed, providing insights into their practical feasibility for large-scale integration. Full article

The parasitic Sub-Fin, beneath the stacked nanosheet FETs, limits both leakage and heat dissipation, acting as the bottleneck for improving the performance of NS-FETs. A Sub-Fin edit technology based on remote plasma etching is proposed to modulate the formation of the Sub-Fin. By controlling the process parameters, the Sub-Fin profile can be continuously modulated from “arrow-shaped” to “bell-shaped,” which provides the flexibility to improve the thermal resistance and reduce the parasitic Sub-Fin-induced degradation, making it suitable for low-power and high-performance applications, respectively. The Sub-Fin edit technology is fully compatible with mature Gate-All-Around (GAA) fabrication processes and offers a feasible approach to balancing the trade-off between Sub-Fin degradation and heat dissipation through the Sub-Fin. Full article

Electronic devices are now ubiquitous across both professional and personal domains, often containing sensitive information that should remain undisclosed to untrustworthy third parties. Consequently, there is an increased demand for effective security measures to prevent the leakage of confidential data. While some devices utilize mathematically secure algorithms to safeguard sensitive information, there remains a vulnerability to informational leaks through Side-Channel Attacks (SCAs) targeting hardware platforms. Non-profiled SCAs, including Correlation Power Analysis (CPA), are particularly practical since they require access only to the target device. In this study, we propose and investigate the use of Deep Learning (DL) techniques to enhance the effectiveness of non-profiled SCAs through an optimized Deep Learning Power Analysis (DLPA) algorithm. Optimized DLPA attacks are implemented using Multi-Layer Perceptron (MLP) and Convolutional Neural Network (CNN) models, and are applied to the PRIDE SBox-4 block across conventional CMOS-style circuits and secure Sense Amplifier-Based Logic (SABL) Dual Precharge Logic (DPL) structure circuits. Both FinFET and TFET device technologies are evaluated. The experimental results show that the optimized DLPA approach consistently outperforms traditional CPA attacks. The optimized DLPA method succeeds even against TFET-based SABL-DPL circuits, which are resistant to conventional techniques. These findings demonstrate the increased threat posed by DL-based SCAs and highlight the need for evaluating hardware security against advanced machine learning-based methods. Full article

This paper focuses on FinFET transistors. The degradation characteristics of FinFET devices after total ionizing dose (TID) radiation in low-temperature environments were investigated by means of a combination of experiments and TCAD simulations. By analyzing the electronic properties of radiation-induced defects in FinFET transistors under low-temperature conditions, the formation and evolution mechanisms of these defects are studied. A physical model for the low-temperature total dose effects of FinFET transistors is established, providing support for the radiation hardening and space applications of FinFET devices. Full article

This paper proposes a hardware–software co-design for adaptive lossless compression based on Hybrid Arithmetic–Huffman Coding, a table-driven approximation of arithmetic coding that preserves near-optimal compression efficiency while eliminating the multiplicative precision and sequential bottlenecks that have traditionally prevented arithmetic coding deployment in resource-constrained embedded systems. The compression pipeline is partitioned as follows: flexible software on the processor core dynamically builds and adapts the prefix coding (usually Huffman Coding) frontend for accurate probability estimation and binarization; the resulting binary stream is fed to a deeply pipelined systolic hardware accelerator that performs binary arithmetic coding using pre-calibrated finite state transition tables, dedicated renormalization logic, and carry propagation mitigation circuitry instantiated in on-chip memory. The resulting implementation achieves compression ratios consistently within 0.4% of the theoretical entropy limit, multi-gigabit per second throughput in 28 nm/FinFET nodes, and approximately 68% lower energy per compressed byte than optimized software arithmetic coding, making it ideally suited for real-time embedded vision, IoT sensor networks, and edge multimedia applications. Full article

NMOSFET, whose gate is on the top of the n-p-n junction with gate oxide in between, is called the n-channel transistor. This bipolar junction underneath the gate oxide may provide an n-n-n-conductive channel as the gate is applied with a positive bias over the threshold voltage (V_th). Conceptually, the definition of an n-type or p-type semiconductor depends on whether the corresponding Fermi energy is higher or lower than the intrinsic Fermi energy, respectively. The positive bias applied to the gate would bend down the intrinsic Fermi energy until it is lower than the original p-type Fermi energy, which means that the p-type becomes strongly inverted to become an n-type. First, the thickness of the inversion layer is derived and presented in a planar 40 nm MOSFET, a 3D 240 nm FinFET, and a power discrete IGBT, with the help of the p (1/m³) of the p-type semiconductor. Different ways of finding p (1/m³) are, thus, proposed to resolve the strong inversion layers. Secondly, the conventional formulas, including the triode region and saturation region, are already modified, especially in the triode region from a continuity point of view. The modified formulas then become necessary and available for fitting the measured characteristic curves at different applied gate voltages. Nevertheless, they work well but not well enough. Thirdly, the electromagnetic wave (EM wave) generated from accelerating carriers (radiation by accelerated charges, such as synchrotron radiation) is proposed to demonstrate phonon scattering, which is responsible for the Source–Drain current reduction at the adjoining of the triode region and saturation region. This consideration of reduction makes the fitting more perfect. Fourthly, the strongly inverted layer may be formed but not conductive. The existing trapping would stop carriers from moving (nearly no mobility, μ) unless the applied gate bias is over the threshold voltage. The quantum confinement addressing the quantum well, which traps the carriers, is to be estimated. Full article

This study presents a high-speed, 9-bit integrating-mode phase interpolator (IMPI) in a 12 nm FinFET process. The proposed slew-rate-tolerant design accepts bandwidth-limited inputs, relaxing the stringent need for high-slew-rate clocks found in prior research. This is primarily achieved through an optimized switch design that converts the sinusoidal voltage input into a quasi-square-wave current. A detailed theoretical model identifies asymmetrical clock feedthrough as the dominant nonlinearity, which is suppressed by a cancellation circuit. Furthermore, an adaptive biasing loop is employed to compensate for Process, Voltage, and Temperature (PVT)-induced P/N mismatch. This work is validated through comprehensive post-layout simulations; operating from a 0.8 V supply at 16 GHz, the PI achieves a peak-to-peak Integral Nonlinearity (INL) of 4.3 LSB (530 fs) while consuming 6.56 mW. Full article

In this review, we focus on group IV one-dimensional devices for quantum technology. We outline the foundational principles of quantum computing before delving into materials, architectures and fabrication routes, separately, by comparing the bottom-up and top-down approaches. We demonstrate that due to easily tunable composition and crystal/interface quality and relatively less demanding fabrications, the study of grown nanowires such as core–shell Ge-Si and Ge hut wires has created a very fruitful field for studying unique and foundational quantum phenomena. We discuss in detail how these advancements have set the foundations and furthered realization of SETs and qubit devices with their specific operational characteristics. On the other hand, top-down processed devices, mainly as Si fin/nanowire field-effect transistor (FET) architectures, showed their potential for scaling up the number of qubits while providing ways for very large-scale integration (VLSI) and co-integration with conventional CMOS. In all cases we compare the fin/nanowire qubit architectures to other closely related approaches such as planar (2D) or III–V qubit platforms, aiming to highlight the cutting-edge benefits of using group IV one-dimensional morphologies for quantum computing. Another aim is to provide an informative pedagogical perspective on common fabrication challenges and links between common FET device processing and qubit device architectures. Full article

Silicon-Based Physical Unclonable Functions (PUFs) exploit inherent manufacturing variations to produce a unique, random, and ideally unclonable secret key. As electronic devices are decommissioned and sent for End of Life (EOL) recycling, the encrypted critical program information remains within the device. However, conventional PUFs remain vulnerable to invasive attacks and reverse engineering that with sufficient time, resources, and effort can enable an adversary to bypass the security enclave of the system and extract this secret data. Recent research has started to explore techniques to respond to tamper attempts using electromigration (EM) and time-dependent dielectric breakdown (TDDB) to the PUF entropy source, preventing future authentication attempts with well-known semiconductor reliability failure mechanisms. This work presents a Pre-Amplifier Physical Unclonable Function (Pre-Amp PUF) with a self-corruption function designed and manufactured in a 3 nm FinFET technology. This PUF can perform a destructive read operation as an EOL anti-counterfeit measure against recycled and reused electronics. The destructive read utilizes an accelerated aging technique that exploits both Hot Carrier Injection (HCI) and Bias Temperature Instability (BTI) degradations directly at the PUF entropy source bitcell data. This work demonstrates a silicon proven ability to irreversibly corrupt the encryption key, invalidating the PUF key, and blocking future authentication attempts. By utilizing HCI and BTI aging effects rather than physical damage a PUF that can self-corrupt its own key without being detectable with imaging techniques is demonstrated for the first time. A feedback loop enables corruption of up to ~30% of the PUF entropy source, which is approximately 3× more data corruption than the prior state of the art self-corrupting PUF. Our technique reuses on-chip stable (repeatable) PUF bitcells identifying circuitry and thereby minimizes the area overhead to support this differentiated feature. Full article

As the integrated circuit process nodes are continuously reduced, higher complexity and accuracy requirements are imposed on the design rule checking (DRC) of standard cell layouts. Traditional manual repair methods are inefficient and prone to errors. A standard cell layout DRC automatic repair strategy based on an improved simulated annealing algorithm is proposed to address this issue. The proposed method quantifies the degree of graphic conflict by dynamically adjusting the annealing parameters; the high-conflict areas and repair paths are optimized. Meanwhile, the proposed method supports the repair of DRC rules at different process nodes ranging from MOSFET (28 nm) to FinFET (14 nm). Experiments results demonstrate that the proposed method outperforms traditional methods in both repair time and quality. Compared to manual repair, about 70% (MOSFET process) and 80% (FinFET process) of time can be saved by the proposed method, and new violations can be avoided during the repair process. Compared with traditional simulated annealing algorithms, approximately 40% (MOSFET process) and 50% (FinFET process) of the running time can be saved, and 100% elimination rate of DRC violations is achieved. The proposed method provides a fully automated and highly reliable DRC repair solution for integrated circuit layout design. Full article

Optimizing static random-access memory (SRAM) cells requires considering parasitic effects, as their impact on circuits in advanced nodes becomes increasingly complex. In this paper, Convolutional Neural Network-Informed Non-dominated Sorting Genetic Algorithms-II (CNN-Informed NSGA-II) was proposed to optimize 7 nm FinFET 6T-SRAM cells taking into account parasitic resistance. CNN-Informed NSGA-II uses a trained CNN model integrated into the conventional NSGA-II, thereby reducing its computational complexity. This approach provides a generally applicable solution that significantly improves the efficiency of circuits while balancing competitive performance metrics. Compared to the ideal (parasitic-free) 6T-SRAM cell design, the optimized 6T-SRAM cell design (considering parasitic effects) achieves a reduction of 81.60% in Write Dynamic Power and 64.65% in Write Time; HSNM and RSNM are improved by 11.92% and 6.42%, respectively. The optimized 7 nm FinFET 6T-SRAM cell structure in this paper outperforms the parasitic-free structure in terms of the performance parameters above, even when taking into account parasitic effects. Full article

Three-dimensional bulk fin-type field-effect transistors (FinFETs) have been the dominant devices since the sub-22 nm technology node. Electrical characteristics of scaled devices suffer from different process variation effects. Owing to the trapping and de-trapping of charge carriers, random interface traps (RITs) degrade device characteristics, and, to study this effect, this work investigates the impact of RITs on the DC/AC/RF characteristic fluctuations of FinFETs. Under high gate bias, the device screening effect suppresses large fluctuations induced by RITs. In relation to different densities of interface traps (D_it), fluctuations of short-channel effects, including potential barriers and current densities, are analyzed. Bulk FinFETs exhibit entirely different variability, despite having the same number of RITs. Potential barriers are significantly altered when devices with RITs are located near the source end. An analysis and a discussion of RIT-fluctuated gate capacitances, transconductances, cut-off, and 3-dB frequencies are provided. Under high D_it conditions, we observe ~146% variation in off-state current, ~26% in threshold voltage, and large fluctuations of ~107% and ~131% in gain and cut-off frequency, respectively. The effects of the random position of RITs on both AC and RF characteristic fluctuations are also discussed and designed in three different scenarios. Across all densities of interface traps, the device with RITs near the drain end exhibits relatively minimal fluctuations in gate capacitance, voltage gain, cut-off, and 3-dB frequencies. Full article

The paradigm shift from FinFET to gate-all-around nanosheet (GAA-NS) transistor architectures necessitates fundamental innovations in channel material engineering. This work addresses the critical challenge of pFET performance degradation in GAA-NS technologies through the development of an advanced selective etching process for strain-engineered SiGe channel formation. We present a systematic investigation of Si selective etching using CF₄/O₂/N₂ gas mixture in a remote plasma source reactor. It is demonstrated that the addition of N₂ to CF₄/O₂ plasmas significantly improves the selectivity of Si to SiGe (up to 58), by promoting NO* radical-induced passivation layer disruption on Si surfaces. Furthermore, an increase in the F:O ratio has been shown to mitigate stress-induced lateral micro-trenching (“Si-tip”), achieving near-zero tip length at high CF₄ flow (500 sccm) while retaining selectivity (>40). Transmission electron microscopy and energy-dispersive X-ray spectroscopy confirm the complete removal of the Si sacrificial layer with minimal SiGe channel loss, validating the process for high-performance SiGe GAA-NS FET integration. These findings provide critical insights into strain-engineered SiGe channel fabrication, enabling balanced NFET/PFET performance in next-generation semiconductor technologies. Full article

In this study, we propose a lateral power-reduced surface field FinFET (LPR-FinFET) to achieve high breakdown voltage and low on-resistance. We investigate the electric field distribution within the reduced surface field (RESURF) structure under reverse-biased conditions, as well as forward transfer and output characteristics using TCAD simulation. The proposed LPR-FinFET demonstrates a high breakdown voltage of 247 V and a low specific on-resistance of 0.255 mΩ·cm² with a high-power figure of merit of 239.3 MW/cm². The superior characteristics of our proposed LPR-FinFET show the potential for applications as a lateral power semiconductor using silicon-on-insulator (SOI) technology. Full article

The increasing demand for high-performance and low-power hardware in artificial intelligence (AI) applications—such as speech recognition, facial recognition, and object detection—has driven the exploration of advanced memory designs. Convolutional neural networks (CNNs) and deep neural networks (DNNs) require intensive computational resources, leading to significant challenges in terms of memory access time and power consumption. Compute-in-Memory (CIM) architectures have emerged as an alternative by executing computations directly within memory arrays, thereby reducing the expensive data transfer between memory and processor units. In this work, we present a 6T SRAM-based CIM architecture implemented using FinFET technology, aiming to reduce both power consumption and access delay. We explore and simulate three different SRAM cell structures—PLNA (P-Latch N-Access), NLPA (N-Latch P-Access), and SE (Single-Ended)—to assess their suitability for CIM operations. Compared to a reference 10T XNOR-based CIM design, our results show that the proposed structures achieve an average power consumption approximately 70% lower, along with significant delay reduction, without compromising functional integrity. A comparative analysis is presented to highlight the trade-offs between the three configurations, providing insights into their potential applications in low-power AI accelerator design. Full article