Next Article in Journal
Operation Flexibility Evaluation and Its Application to Optimal Planning of Bundled Wind-Thermal-Storage Generation System
Next Article in Special Issue
Determination of Complex Conductivity of Thin Strips with a Transmission Method
Previous Article in Journal
Modeling and Analysis of Wearable Antennas
Previous Article in Special Issue
AlGaN/GaN MIS-HEMT with PECVD SiNx, SiON, SiO2 as Gate Dielectric and Passivation Layer
Open AccessArticle

Partial Isolation Type Saddle-FinFET(Pi-FinFET) for Sub-30 nm DRAM Cell Transistors

1
School of Electronics and Computer Engineering, Chonnam National University, Gwangju 500-757, Korea
2
Department of Electrical and Control Engineering, Mokpo National University, Jeollanam-do 534-729, Korea
3
School of Electrical Engineering, Seoul National University, Seoul 151-742, Korea
4
The KEPCO Research Institute, Daejeon 305-760, Korea
*
Authors to whom correspondence should be addressed.
Electronics 2019, 8(1), 8; https://doi.org/10.3390/electronics8010008
Received: 1 November 2018 / Revised: 13 December 2018 / Accepted: 19 December 2018 / Published: 21 December 2018
(This article belongs to the Special Issue Nanoelectronic Materials, Devices and Modeling)
In this paper, we proposed a novel saddle type FinFET (S-FinFET) to effectively solve problems occurring under the capacitor node of a dynamic random-access memory (DRAM) cell and showed how its structure was superior to conventional S-FinFETs in terms of short channel effect (SCE), subthreshold slope (SS), and gate-induced drain leakage (GIDL). The proposed FinFET exhibited four times lower Ioff than modified S-FinFET, called RFinFET, with more improved drain-induced barrier lowering (DIBL) characteristics, while minimizing Ion reduction compared to RFinFET. Our results also confirmed that the proposed device showed improved drain-induced barrier lowering (DIBL) and Ioff characteristics as gate channel length decreased. View Full-Text
Keywords: gate-induced drain leakage (GIDL); drain-induced barrier lowering (DIBL); recessed channel array transistor (RCAT); on-current (Ion); off-current (Ioff); subthreshold slope (SS); threshold voltage (VTH); saddle FinFET (S-FinFET); potential drop width (PDW); shallow trench isolation (STI); source/drain (S/D) gate-induced drain leakage (GIDL); drain-induced barrier lowering (DIBL); recessed channel array transistor (RCAT); on-current (Ion); off-current (Ioff); subthreshold slope (SS); threshold voltage (VTH); saddle FinFET (S-FinFET); potential drop width (PDW); shallow trench isolation (STI); source/drain (S/D)
Show Figures

Figure 1

MDPI and ACS Style

Kim, Y.K.; Lee, J.S.; Kim, G.; Park, T.; Kim, H.J.; Cho, Y.P.; Park, Y.J.; Lee, M.J. Partial Isolation Type Saddle-FinFET(Pi-FinFET) for Sub-30 nm DRAM Cell Transistors. Electronics 2019, 8, 8.

AMA Style

Kim YK, Lee JS, Kim G, Park T, Kim HJ, Cho YP, Park YJ, Lee MJ. Partial Isolation Type Saddle-FinFET(Pi-FinFET) for Sub-30 nm DRAM Cell Transistors. Electronics. 2019; 8(1):8.

Chicago/Turabian Style

Kim, Young K.; Lee, Jin S.; Kim, Geon; Park, Taesik; Kim, Hui J.; Cho, Young P.; Park, Young J.; Lee, Myoung J. 2019. "Partial Isolation Type Saddle-FinFET(Pi-FinFET) for Sub-30 nm DRAM Cell Transistors" Electronics 8, no. 1: 8.

Find Other Styles
Note that from the first issue of 2016, MDPI journals use article numbers instead of page numbers. See further details here.

Article Access Map by Country/Region

1
Search more from Scilit
 
Search
Back to TopTop