Effects of Varying the Fin Width, Fin Height, Gate Dielectric Material, and Gate Length on the DC and RF Performance of a 14-nm SOI FinFET Structure

Abstract

The FinFET architecture has attracted growing attention over the last two decades since its invention, owing to the good control of the gate electrode over the conductive channel leading to a high immunity from short-channel effects (SCEs). In order to contribute to the advancement of this rapidly expanding technology, a 3D 14-nm SOI n-FinFET is performed and calibrated to the experimental data from IBM by using Silvaco TCAD tools. The calibrated TCAD model is then investigated to analyze the impact of changing the fin width, fin height, gate dielectric material, and gate length on the DC and RF parameters. The achieved results allow gaining a better understanding and a deeper insight into the effects of varying the physical dimensions and materials on the device performance, thereby enabling the fabrication of a device tailored to the given constraints and requirements. After analyzing the optimal values from different changes, a new device configuration is proposed, which shows a good improvement in electrical characteristics.

1. Introduction

The structure of the fin field-effect transistor (FinFET) has completely emerged as a promising design solution for CMOS logic and memory circuit design because of its good immunity to short channel effects (SCEs) [1,2,3]. This technology enables the creation of high-performance ultra-scaled, high-density integration, and high-performance silicon (Si) chips [1,2,3,4]. In the silicon industry, device miniaturization is still considered a key feature to achieve better short-channel performance. Currently, a great effort concerns the development of FinFET devices with dimensions below 5 nm that represent the target in the near future [4,5,6,7,8]. Despite the effort made to create devices with dimensions below 5 nm, many aspects still remain to be clarified and optimized, also with a view to a larger-scale application of the devices.

This paper presents an investigation of 3D 14-nm FinFET on thin silicon on insulator (SOI) wafer using Silvaco tools. The SOI technology shows significantly large improvement compared to the previous FinFET technology. For better Si channel controllability, hafnium oxide (HfO₂) was used to cover the Si channel as a gate dielectric. The impact of varying the fin width (W_fin = 4, 6.5, 15, and 20 nm), fin height (H_fin = 10, 15, 20, 25, 30, and 35 nm), gate dielectric materials (TiO₂, La₂O₃, HfO₂, Al₂O₃, Si₃N₄, and SiO₂), and gate length (L_g = 5, 10, 15, and 20 nm) on the DC and RF performance of the considered structure is carefully analyzed and discussed. The analysis is performed by investigating the following parameters: threshold voltage (V_th), subthreshold slope (SS), drain-induced barrier lowering (DIBL), on-state current (I_on), off-state current (I_off), I_on/I_off ratio, transconductance (g_m), gate capacitance (C_gg), and cut-off frequency (f_T). The development of a comparative analysis enables gaining a better understanding of how to improve device performance, depending on the given fabrication constraints and application requirements.

It should be underlined that the great interest in the FinFET technology is witnessed by the many papers that have been published over the years to investigate the FinFET performance by using both TCAD simulations [8,9,10,11,12,13] and measurements [14,15,16,17,18]. Although a measurement-based investigation is a mandatory step prior to the use of a device in real applications, the TCAD simulation is considered a powerful and costless type of analysis to optimize device performance. This is because the TCAD tool allows predicting how the device performance changes by varying the design parameters without the need for time-consuming and costly experiments [13].

The rest of this paper is structured as follows: Section 2 presents the device structure, Section 3 describes the developed model for the achieved simulations, Section 4 reports and discusses the obtained findings; and the last section concludes the paper.

2. Device Structure

The 3D 14-nm SOI FinFET device has been simulated using Silvaco TCAD. Figure 1 shows the 3D schematic diagram of the FinFET device with a physical gate length (L_g) of 20 nm. The geometrical parameters and material properties are specified in previously published papers [1,2,3]. HfO₂ is used as a gate dielectric material. The doping densities of the source (n-type), drain (n-type), and covered fin (p-type) region were 1 × 10²¹ cm⁻³, 1 × 10²¹ cm⁻³, and 1 × 10¹⁶ cm⁻³, respectively. The contact resistance of 1 × 10⁻⁹ Ω.cm² was selected for the source/drain region.

Table 1. Device parameters for a 14-nm n-FinFET.

Parameters	Values
Channel length, Lg	20 nm
Fin height, Hfin	26 nm
Fin width, Wfin	6.5 nm
S/D length, LS/D	50 nm
S/D extension length, LS/D	7 nm
Buried oxide (SiO2) thickness, tBOX	50 nm
Gate dielectric (HfO2) thickness, tox	4 nm
Channel doping (boron, p-type), Nch	1016 cm−3
S/D doping (arsenic, n-type), NS/D	1021 cm−3
S/D extension doping (arsenic, n-type)	1019 cm−3
Si substrate doping (boron, p-type)	1016 cm−3
Gate work function (TiN (Sn), Φm)	4.32 eV

illustrates the physical parameters of the investigated model.

3. Simulation Model

For device simulation, CVT, CCSMOB, ANALYTIC, BGN, SRH, and Auger recombination were also included. Fermi–Dirac distribution has been enabled. For quantum confinement, the BQP model was considered [13]. By considering a FinFET device based on using one single fin, the effective channel width can be estimated as follows

W_eff = 2H_fin + W_fin

(1)

where H_fin is the fin height and W_fin is the fin width.

The electron (n) and hole (p) densities with BQP equation can be expressed by [13]

$$n=N_c{\mathrm{e}}^{-\frac{\left(E_c+qQ\right)}{\mathrm{k}{T}_L}}$$

(2)

$$p=N_v{\mathrm{e}}^{-\frac{\left(\mathrm{qQ}-{\mathrm{E}}_{\mathrm{v}}\right)}{\mathrm{k}{T}_L}}$$

(3)

$$Q=\frac{-h^2}{2}\frac{\gamma \underset{\_}{\nabla }\left(M^{-1}\underset{\_}{\nabla }\left(n^{\alpha }\right)\right)}{n^{\alpha }}$$

(4)

N_c and N_v are the effective density of states for electrons and holes, respectively. E_c and E_v are the conduction and valence bands, respectively. k is the Boltzmann constant, T_L is the local lattice temperature, q is the electric charge, Q is the quantum potential, M⁻¹ is the inverse effective mass tensor, and γ and α are two adjustable parameters.

Device Validation

Initially, the investigated 14-nm SOI n-FinFET model was carefully calibrated according to the experimental data in [1]. In order to match the simulated I–V curves with the experimental data from IBM [1], some physical parameters such as the doping density, thickness, source/drain extension length, and gate work function were carefully adjusted. Figure 2 illustrates simulated I–V characteristics at two different values of V_ds: 0.05 V (linear) and 0.8 V (saturation). I–V model curves exactly match with the experimental as is observed at both bias conditions. The device characteristics of the investigated model are compared to the experimental outputs [1] and presented in

Table 2. Characteristics for the investigated FinFET model.

Device Characteristics	This Work	Ref. [1]	Ref. [2]
Vdd (mV)	800	800	800
Vth, lin (mV)	137	-	162
Vth, sat (mV)	120	-	147
Ion, lin (µA)	8.11	7.06	7.64
Ion, sat (µA)	53.6	-	58.15
Ioff, lin (nA)	1.89	2.51	1.43
Ioff, sat (nA)	4.22	-	2.51
Ion, lin/Ioff, lin	4.29 × 103	-	5.32 × 103
Ion, sat/Ioff, sat	1.27 × 104	-	2.32 × 104
SSlin (mV/dec)	61	67	62.83
SSsat (mV/dec)	64.91	-	63.45
DIBL (mV/V)	43.32	55	20.5

. To further validate the developed model, the simulation results were compared also to Sun’s work [2]. Figure 3 presents the output I–V characteristics of the investigated model at different gate-source voltages. Figure 3 shows a non-zero current for V_gs just above V_th and the increase in I_ds with increasing input voltage V_gs.

To evaluate the SCEs, the subthreshold slope (SS) and drain-induced barrier lowering (DIBL) are extracted as follows [4,11]

$$SS=\frac{d\left(V_{gs}\right)}{d\left[log\left(I_{ds,sat}\right)\right]}$$

(5)

$$DIBL=\frac{\left|V_{th, sat}-V_{th, lin}\right|}{V_{DD}-0.05V}$$

(6)

where V_gs is the gate-source voltage and I_ds,sat is the drain current (under saturated biasing condition). V_th,sat and V_th,lin are the threshold voltages under saturated and linear conditions, respectively. The values of SS and DIBL are, respectively, 61 mV/dec and 43.32 mV/V for the 14-nm n-FinFET. These parameters are approximately maintained the same as the ones reported in papers [1,2,3,4].

The cut-off frequency (f_T) is considered as a crucial RF parameter which defines the speed response of the RF circuit design. The f_T can be expressed by [14,15,16,17]

$$f_T=\frac{g_m}{2\pi C_{gg}}=\frac{g_m}{2\pi \left(C_{gs}+C_{gd}\right)}$$

(7)

where g_m is the transconductance, C_gg is the total gate capacitance, C_gs is the gate-source capacitance, and C_gd is the gate-drain capacitance.

4. Results and Discussion

In this section, the effects of changing the fin width, the fin height, the gate dielectric material, and the gate length on the device performance are analyzed and investigated for the SOI FinFET structure under study. The investigated tri-gate FinFET device has a 3D channel as illustrated in Figure 1. The model was calibrated with an agreement to IBM’s model (see Figure 2). The electrical characteristics of the FinFET device are evaluated at a room temperature of 300 K.

4.1. Effects of the Fin Width/Height on Device Performance

In this study, it is important to start by investigating the effect of different fin size ratios on device characteristics. To analyze the impact of the fin width on the device performance, the fin width of the studied structure was varied from 4 nm to 20 nm with the fin height kept fixed at 26 nm. It should be underlined that, although a larger fin width allows enlarging the total gate width (see Equation (1)), when the gate length shrinks, the W_fin width has to shrink as well in order to maintain an efficient suppression of the SCEs [19]. Figure 4 reports the effect of changing the fin width on the transfer I–V characteristics and the corresponding transconductance (Triangle symbols) for the investigated device. As can be clearly observed, the increase in the fin width leads to a reduction of the threshold voltage, in agreement with what is expected from previous studies [18]. In addition, owing to the increase of the total gate width (see Equation (1)), a larger fin width implies an increase in the drain current and transconductance [9,18]. Figure 5 shows the total gate capacitance versus V_gs for the studied device with different values of the fin width. As can be seen, as V_gs increases, C_gg increases until its value becomes roughly constant [4]. The value of C_gg decreases by decreasing the fin width, due to the reduction of the total gate width. Figure 6 shows f_T variation as a function of V_gs for the studied device with different values of the fin width. The peak in f_T increases as W_fin reduces. The behavior of f_T is mainly due to the impact of the fin width on C_gg rather than on g_m, as can be observed from Figure 4, Figure 5 and Figure 6. The peak point of f_T is 3.9 THz at V_gs = 0.21 V with a V_ds = 0.05 V for a device with a fin width of 4 nm.

The variations of the threshold voltage, subthreshold slope, on-current, and off-current with different values of the fin height (H_fin = 10, 15, 20, 25, 30, and 35 nm) and of the fin width (W_fin = 4, 6.5, 15, and 20 nm) are shown in Figure 7, Figure 8, Figure 9 and Figure 10, respectively. Figure 7 shows a reduction in the threshold voltage with increasing H_fin and/or W_fin. Figure 8 shows the impact of H_fin on the subthreshold slope for FinFET devices with different values of W_fin at V_ds = 0.05 V. This figure shows a slight impact of changing H_fin on SS when considering the lower values of the fin width (i.e., 6.5 nm and 4 nm), whereas a marked increase in SS is observed with increasing H_fin and/or W_fin when considering higher values of the fin width. It was observed that, for the studied FinFETs, a smaller fin width leads to better device performance in terms of SS. This confirms that studying the impact of varying fin width and fin height is essential for enabling technology development, since they can have a strong impact on the short channel effects. As expected, the increase in the gate width by increasing H_fin and/or W_fin leads to an increase in both on-state current and off-state current, as reported in Figure 9 and Figure 10. Figure 9 shows the impact of H_fin on the switching current (I_on) for FinFET devices with different W_fin at V_gs = V_ds = 0.8 V. It is achieved a rapid increase in I_on as W_fin and/or H_fin increase. Figure 10 shows the impact of H_fin on the leakage current (I_off) for FinFET devices with different W_fin at V_gs = 0 V and V_ds = 0.8 V. It is achieved a clear decrease in I_off as W_fin and/or H_fin decrease. In particular, Figure 10 shows a slighter impact of changing H_fin on I_off when considering the lower values of the fin width (i.e., 6.5 nm and 4 nm), whereas a more marked decrease in I_off is observed with decreasing H_fin and/or W_fin when considering higher values of the fin width. The electrostatic can be improved effectively with shorter fin width, which can report better mitigation of the leakage current for the nanoscale devices. This could be a good design strategy to enhance device performance, but it will be quite difficult to fabricate the pattern on the device with a very high aspect ratio (H_fin/W_fin). For a given variation in the fin height, the corresponding change in the device performance of the investigated FinFET model can be linked to what was reported and discussed in detail in Kurniawan’s work [20].

As is well-known, a higher I_on is well desired while the leakage current I_off should be kept low in order to minimize the static power consumption. Figure 11 shows the effect of varying the fin height and the fin width on the I_on/I_off ratio, which is a crucial figure of merit for digital applications. As shown in Figure 11, the I_on/I_off ratio decreases with increasing H_fin and/or W_fin. It should be noticed that the highest value of the I_on/I_off ratio occurs at the lowest height of 10 nm and then decreases approximately exponentially with increasing H_fin.

4.2. Impact of High-k Dielectric Materials on Device Performance

To analyze the effect of the gate dielectric materials on the device performance, the fin width, fin height, and gate length of the studied structure were fixed at 6.5, 26, and 20 nm, respectively. Figure 12 shows the total gate capacitance versus V_gs for different high-k dielectric materials. Under all of the studied cases, C_gg starts increasing as V_gs increases until saturation, and then it becomes roughly constant, as expected [4]. The value of C_gg increases with high-k dielectric material.

The change in transconductance and cut-off frequency with different gate dielectric materials is shown in Figure 13. The analyzed bias point is: V_gs = 0.2 V and V_ds = 0.05 V. As can be observed from the figure, a remarkable improvement of the device performance is achieved using higher-k material [4,21]. The value of g_m for TiO₂ material is higher compared to the values obtained by using the other dielectric materials, implying a higher amplification capability of the device [4,22]. The resultant behavior of f_T is mainly due to the impact of the high-k dielectric material on g_m rather than on C_gg, as can be noticed from Figure 12 and Figure 13. The highest f_T is obtained at V_gs = 0.2 V with V_ds = 0.05 V for a FinFET model with TiO₂ material, reflecting the better gate controllability over the channel fin region and hence higher transconductance.

In short channel devices, the leakage current can be problematic for switching speed in the circuit by leading to an increase in the I_on/I_off ratio. The use of a multigate design structure together with high-k dielectric materials proves good mitigation in device issues and demonstrates high switching speed in electric circuits [16,17,18,19,20,21,22]. Figure 14 shows the transfer I–V characteristics in a logarithmic scale of 14-nm SOI n-FinFET under on-state bias conditions (V_ds = 0.8 V). It is observed that the off-state current decreases, especially with high-k. As expected, using high-k dielectric such as TiO₂ is necessary for short channel devices to mitigate the leakage current. It is also observed that the current flow in the short channel can be improved by using high-k dielectric material. As reported in Figure 15, the highest value of I_on/I_off occurs at the highest dielectric constant. For many electronic circuit applications, such as amplifiers and digital circuits, the best I_on/I_off current ratio is at the highest value and therefore it implies better device performance.

4.3. Impact of the Gate Length on Device Performance

To analyze the effect of the gate length on the device performance, the fin width and fin height of the studied structure were fixed at 6.5 nm and 26 nm, respectively. Furthermore, the hafnium oxide was used as a gate dielectric material. There are full-node processes for FinFET technologies, such as 16, 14, 10, 7, 5, and 3 nm in R&D [1,2]. Thus, is very important to investigate the effect of the gate length on calibrated FinFET device performance. Varying device gate lengths can help in judging the numerical model’s accuracy in predicting the device characteristics. The change in transconductance with different gate lengths (from 5 nm to 20 nm) is shown in Figure 16. It can be observed from the figure that a remarkable limitation is achieved by scaling down the gate length. The g_m for 10 nm gate length device reaches higher values compared to other devices with different gate lengths [4,18]. The f_T behavior is mainly due to the gate length effect on g_m rather than on C_gg, as can be noticed from Figure 16, Figure 17 and Figure 18. The highest f_T is obtained at V_gs = 0.25 V with V_ds = 0.05 V for a device with 5 nm gate length, as illustrated in Figure 18. To find the effect of the gate length on the device’s I–V characteristics, the gate length was varying from 5 nm to 20 nm. Figure 19 illustrates the effects of the gate length on transfer I–V curves of the device. It is well seen from the figure that reducing the gate length leads to a decrease in the threshold voltage, but it causes an increase in the leakage current (at V_gs = 0 V). The variation of the threshold voltage, subthreshold slope, and I_on/I_off ratio at two gate lengths with different fin widths is shown in Figure 20, Figure 21 and Figure 22, respectively. As can be observed, V_th and SS are sensitive to W_fin for a small gate length due to the short channel effect as illustrated in Figure 20 and Figure 21, respectively [22,23,24,25,26,27]. As shown in Figure 22, the highest value of I_on/I_off occurs at the lowest fin width.

4.4. Device Optimization

Silicon material is used for the fabrication of an optimized FinFET device with a physical gate length of 15 nm. TiO₂ is used as gate dielectric material to replace HfO₂ for better controllability of the gate over the channel. As it is well-known, the electrostatic integrity can be improved by reducing the thickness of the gate oxide [26]. The high-k dielectric thickness is chosen to be 2 nm. Based on the previous investigation, the fin width and fin height are chosen to be equal to 4 nm and 35 nm, respectively. Fin width was scaled down in order to improve FinFET electrostatics. The source/drain spacers are fixed to 7 nm and covered by Si₃N₄. The contact resistivity at the S/D contact/silicon interface is fixed to 10⁻⁹ Ω.cm². The proposed device with the above characteristics shows a good improvement in electrical parameters such as I_on, SS, and DIBL compared to calibrated FinFET [1]. This proves that the improvement of SCEs in the FinFET device reduces sensitivity to the leakage current. It is also interesting to note that I_on/I_off ratio is approximatively two times greater than the calibrated FinFET. Better device switching (on/off) can result from steeping SS and a larger I_on/I_off ratio.

Table 3. Comparison of different 14-nm SOI n-FinFET device technologies.

Device Characteristics	Calibrated Device	Optimized Device	FinFET [28]	FinFET (IRDS 2020) [29]	FinFET [30]
Vdd (mV)	800	800	-	-	-
Vth, lin (mV)	137.31	143.6	-	-	-
Vth, sat (mV)	120	110.5	-	240	233.55
Ion, lin (µA)	8.11	17.49	-	-	-
Ion, sat (µA)	53.6	148.93	-	68.62	10.9 (/µA)
Ioff, lin (nA)	1.89	1.89	-	-	-
Ioff, sat (nA)	4.22	5.35	-	1.76	80.6 (/µA)
Ion, lin/Ioff, lin	4.29 × 103	9.24 × 103	-	-	-
Ion, sat/Ioff, sat	1.27 × 104	2.77 × 104	-	38.933	135.236
SSlin (mV/dec)	60.60	58.80	80	-	-
SSsat (mV/dec)	64.91	58.22	-	72	76.98
DIBL (mV/V)	43.32	22.65	75	50	68.57

illustrates a comparison of the optimized and calibrated device parameters with different 14-nm FinFET device technologies [28,29,30].

Finally, it should be highlighted that nowadays the interest for the FinFET technology is spreading more and more in many fields of application—such as single-molecule detection [31], pH sensing [32,33], biomedicine [34], label-free biosensing [35], 5G power amplifiers [36], energy harvesting [37], and space application [38], just to mention a few. This wide and ever-expanding range of applications makes evident the increasing need for an accurate optimization of the FinFET structure to satisfy the specific constraints and requirements.

5. Conclusions

In this study, the 3D 14-nm SOI n-FinFET was successfully simulated, performed, and calibrated to experimental data by using Silvaco tools. The effects of varying the fin width, fin height, gate dielectric material, and gate length on device performance were analyzed in terms of both DC and RF parameters. The results indicated that low leakage current and high I_on/I_off ratio can be obtained with small W_fin and H_fin. A cut-off frequency on the order of 1 THz was simulated and reported for the investigated FinFET model. The results indicated that this frequency is increased for smaller fin width and a subsequent reduction of gate transconductance. For the optimized device, a transconductance of 69.33 µS and a cut-off frequency of 4.22 THz were achieved at V_ds = 0.05 V with V_gs = 0.23 V and V_gs = 0.22 V, respectively, by using the TiO₂ as the gate dielectric at 15-nm gate length. The developed study provided some useful insights outlining the great potential of the FinFET technology nodes for RF applications with high performance and low power consumption.