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Open AccessArticle

Impacts of Work Function Variation and Line-Edge Roughness on TFET and FinFET Devices and 32-Bit CLA Circuits

Department of Electronics Engineering and Institute of Electronics, National Chiao-Tung University, 1001 University Road, Hsinchu 300, Taiwan
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The original of this paper had been presented in IEEE S3S Conference 2014.
Academic Editors: David Bol and Steven A. Vitale
J. Low Power Electron. Appl. 2015, 5(2), 101-115; https://doi.org/10.3390/jlpea5020101
Received: 23 February 2015 / Revised: 8 May 2015 / Accepted: 14 May 2015 / Published: 21 May 2015
(This article belongs to the Special Issue Selected Papers from IEEE S3S Conference 2014)
In this paper, we analyze the variability of III-V homojunction tunnel FET (TFET) and FinFET devices and 32-bit carry-lookahead adder (CLA) circuit operating in near-threshold region. The impacts of the most severe intrinsic device variations including work function variation (WFV) and fin line-edge roughness (fin LER) on TFET and FinFET device Ion, Ioff, Cg, 32-bit CLA delay and power-delay product (PDP) are investigated and compared using 3D atomistic TCAD mixed-mode Monte-Carlo simulations and HSPICE simulations with look-up table based Verilog-A models calibrated with TCAD simulation results. The results indicate that WFV and fin LER have different impacts on device Ion and Ioff. Besides, at low operating voltage (<0.3 V), the CLA circuit delay and power-delay product (PDP) of TFET are significantly better than FinFET due to its better Ion and Cg,ave and their smaller variability. However, the leakage power of TFET CLA is larger than FinFET CLA due to the worse Ioff variability of TFET devices. View Full-Text
Keywords: tunnel FET (TFET); FinFET; work function variation (WFV); line-edge-roughness (LER); carry-lookahead adder (CLA) tunnel FET (TFET); FinFET; work function variation (WFV); line-edge-roughness (LER); carry-lookahead adder (CLA)
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Chen, Y.-N.; Chen, C.-J.; Fan, M.-L.; Hu, V.P.-H.; Su, P.; Chuang, C.-T. Impacts of Work Function Variation and Line-Edge Roughness on TFET and FinFET Devices and 32-Bit CLA Circuits. J. Low Power Electron. Appl. 2015, 5, 101-115.

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