Suppression of STI-Induced Asymmetric Stress in FinFET by CESL Stressor

Abstract

With the continuous scaling of CMOS technology, stress engineering has become increasingly critical at advanced technology nodes, especially in tall and narrow FinFET structures. Asymmetric layout environments (such as dual-Fin structures or poly cuts) can introduce stress imbalance originating from shallow trench isolation (STI), which in turn affects device performance. In this study, TCAD simulations were performed on n-type FinFETs representative of the 10 nm technology node, with a physical gate length of 20 nm, to investigate the correlation between asymmetric stress and device drive current. As the Fin width decreases, the asymmetric stress from STI induces noticeable performance fluctuations, with the mobility enhancement under saturation bias reaching a maximum of 8.42% at W = 6 nm. Similarly, as the Fin body angle deviates from 90° and the Fin top narrows, with W_top = 6 nm and W_bottom = 8 nm, the mobility enhancement peaks at 7.65%. The simulation results confirm that STI-induced asymmetric stress has a significant impact on the Fin sidewall channel, while its effect on the top channel is minimal. To mitigate these effects, CESL stress engineering is proposed as an effective solution to amplify the top channel current, thereby reducing the influence of asymmetric stress on device performance. A CESL stress of 2.0 GPa is shown to improve device stability by approximately 20%.

1. Introduction

Strain engineering, as an important method for enhancing device performance, has been widely implemented in conventional bulk silicon MOSFETs and has become an indispensable element of CMOS scaling. Intentional channel stress, introduced through methods such as stress memorization technique (SMT) [1], embedded lattice-mismatched SiGe [2], and high-stress contact etch stop layers (CESL) [3], can significantly enhance device performance. However, due to factors such as layout-dependent effects or unintentional process-induced stress, device performance may vary [4]. Previous studies have shown that unintentional stress caused by STI can lead to performance variations of up to 19% at the 0.18 μm technology node [5]. Therefore, investigating the impact of STI stress on device performance is crucial.

Since the 22 nm technology node, FinFET technology has been widely adopted in advanced low-power and high-performance applications, replacing traditional planar silicon devices. To further improve device performance, FinFETs also incorporate techniques similar to strain engineering. STI and CESL stress engineering techniques remain effective means of improving carrier mobility and drive current in FinFET devices, even at technology nodes below 20 nm. STI-induced stress originates from mechanical interactions between the isolation trench and the active region and can be modulated through factors such as STI recess depth and active layout geometry. CESL stress, introduced via high-stress nitride liners deposited over the gate stack, can be adjusted to induce uniaxial tensile or com-pressive stress, enhancing electron or hole mobility depending on the device type. These methods have been widely adopted in modern FinFET technology as performance boosters when conventional scaling reaches its limits [6,7]. However, as technology nodes continue to scale down and FinFET structures become taller and narrower, device characteristics have become increasingly sensitive to asymmetric stress. Even with the same gate length (L) and Fin width (W), performance variation can still occur due to asymmetric stress. This is because asymmetric STI stress causes inconsistent carrier mobility within the Fin channel, resulting in variations in device current [8]. Despite the significant impact of asymmetric STI stress on FinFET performance fluctuations, this effect has not been thoroughly investigated.

Previous studies have demonstrated that STI-induced stress plays a critical role in FinFET performance, where the geometry of the STI recess significantly alters the local stress distribution and thus affects carrier transport characteristics. For example, variations in STI etch profiles can lead to measurable differences in drive current, especially for n-type FinFETs where tensile stress enhances electron mobility [9]. In addition, CESL stress engineering has been shown to further modulate stress states in FinFET structures, offering additional degrees of freedom for performance tuning [10]. However, these studies typically consider symmetric device structures and stress environments, such as balanced STI recess or uniformly applied CESL layers. In contrast, asymmetric stress conditions—common in advanced layouts due to design constraints or process variations—remain underexplored. In this work, we focus on isolated FinFET devices under deliberately introduced asymmetric STI-induced stress, aiming to reveal the unique impact on device-level electrical characteristics.

To accurately capture the relationship between asymmetric STI stress and the Fin structure, this paper employs TCAD simulations to model stress distribution and analyze the impact of asymmetric stress on 10 nm FinFETs. The study reveals that as the Fin width decreases, device performance deteriorates significantly under asymmetric STI stress, peaking at W = 6 nm. Additionally, the angle of the Fin body also affects the impact of asymmetric STI stress. The closer the Fin body angle is to 90°, the smaller the effect of asymmetry. Since asymmetric STI stress primarily affects the sidewall channels of the Fin and has a weaker impact on the top channel, this paper proposes utilizing CESL stress engineering to amplify the current contribution from the top channel, thereby mitigating the adverse effects of asymmetric STI stress on device performance [8].

2. Methods

2.1. Analysis of Asymmetric Stress

Previous studies have shown that in planar devices, due to the necessary series transistor layout, such as NMOS transistors in NAND gates, edge transistors are subject to strong asymmetric STI-induced stress, resulting in performance variations. Additionally, asymmetric stress can be introduced by single-sided poly cut fill materials. For both single-Fin and dual-Fin transistors, the poly cut layout is single-sided, leading to unidirectional tensile stress on the transistors. Due to the structure of the Fins, the asymmetric stress from STI and poly cut primarily concentrates on the sidewall channels, with minimal impact on the top channel. In single-Fin transistors, both the poly cut and STI stresses are imposed on the same Fin, resulting in stronger asymmetric stress in the FinFET. In contrast, for dual-Fin devices, these stresses are applied to different Fins, reducing stress asymmetry. However, the impact on device performance still remains significant [8].

Besides asymmetric stress from STI and poly cut, the layout of the active area also affects device characteristics. Studies have indicated that the active area length (from the gate edge to the STI edge) influences the threshold voltage (V_tℎ) and transconductance (g_m) of planar MOSFETs [5]. Although STI wall oxide nitridation and densification of STI fill oxide in a pure nitrogen environment can reduce STI-induced stress and help mitigate asymmetry effects, the shrinking device dimensions and increasingly tall and narrow Fin structures make devices more sensitive to asymmetric stress. STI stressors are widely used today as an effective technique to improve device performance [11], making asymmetric stress in FinFETs both inevitable and more pronounced than in planar devices. In this study, to facilitate simulation, we used STI with different stress doping to simulate an asymmetric stress environment, explore device performance variations, and propose optimization methods for asymmetric stress.

2.2. Simulation Setup

The FinFET structure and stress simulations were performed in Sentaurus TCAD, and the process flow was simulated by SPROCESS and evaluated for electrical performance using SDEVICE. In this work, all simulations are performed on n-type FinFET structures. Figure 1 shows the process flow of the FinFET device, including two stressors: CESL stressor and STI stressor. Positive stress values represent tensile stress, while negative values indicate compressive stress. Si:C (carbon-doped silicon) was selected for both the source and drain (S/D) regions to reflect current industrial practices in strained NMOS FinFETs. Si:C offers several key advantages: it effectively suppresses boron diffusion during high-temperature annealing, enabling the formation of abrupt and ultra-shallow junctions that are crucial for short-channel control. It also provides excellent thermal stability and is fully compatible with conventional CMOS process flows. Additionally, Si:C introduces uniaxial tensile stress, which enhances electron mobility in the channel [12]. This material choice ensures consistent stress transfer and improved performance in simulations involving CESL stressors.

Table 1. FinFET dimensions used in this work.

FinFET Dimensions
Fin height	27 nm
Fin top width	6–10 nm
Fin bottom width	6–10 nm
Gate length	20 nm
Poly pitch	32 nm
Fin pitch	45 nm
STI stress	2.0 GPa
CESL stress	0.5–2.0 GPa

summarizes the key device parameters used in the FinFET simulations. It is noted that the term “10 nm” used throughout this work refers to the technology node, which represents the overall scaling generation rather than a specific physical dimension. In our TCAD simulation, the gate length is set to 20 nm to reflect realistic FinFET device dimensions at the 10 nm node, ensuring both model accuracy and simulation stability.

In this study, to construct an asymmetric stress environment, we assigned distinct intrinsic stress values to the STI regions on the two sides of the Fin. Specifically, one side of the STI was assigned a defined intrinsic stress of 2.0 GPa, while the other side was treated as stress-free (0 GPa) due to material redefinition. Both STI regions are intrinsic and undoped. Considering a Poisson’s ratio of 0.16, the corresponding built-in stress is approximately 2.47 × 10¹⁰ dyne/cm². This asymmetry is the primary source of stress imbalance, which propagates into the channel region and influences carrier mobility.

The total mobility of the FinFET is calculated by averaging the stress tensor components σ_ii along the top and sidewall channels of the Fin:

$${\sigma }_{ii,av}={\displaystyle \frac{1}{L_G}}{\int }_{L_G}{\sigma }_{ii}·dz\hspace{1em}for\hspace{1em}ii=xx,yy,zz,$$

(1)

L_G represents the gate length, and z denotes the coordinate along the gate, from the source to the drain. The change in the average mobility, Δμ_top,side is calculated using the standard piezoresistive coefficient for n-type silicon:

$${d\mu }_{top,side}=\overrightarrow{\mathsf{\Pi }}·{\overrightarrow{\sigma }}_{av,top,side}$$

(2)

$\overrightarrow{\mathsf{\Pi }}$ is the piezoresistive conductivity tensor used for the <011>/(100) nFET channel, and the resulting mobility change, Δμ_top,side, is then used to calculate the effective mobility of the Fin channel:

$${\mu }_{top}={\mu }_{0,top}·\left[1+d{\mu }_{top}\right]$$

(3)

$${\mu }_{side}={\mu }_{0,side}·\left[1+d{\mu }_{side}\right]$$

(4)

The total mobility μ_total of the device is calculated using the following formula:

$${\mu }_{total}={\displaystyle \frac{\int {\mu }_{top}dy+\int {\mu }_{side}dx}{Wy+2·F_H}}$$

(5)

$${\mu }_{0,total}={\displaystyle \frac{{\mu }_{0,top}·W+2·{\mu }_{0,side}·F_H}{W+2·F_H}}$$

(6)

W and F_H are the width and height of the Fin, respectively, and μ_0,total is the carrier mobility of the unstrained Fin. The total mobility enhancement is calculated as:

$$\partial {\mu }_{total}={\displaystyle \frac{{\mu }_{total}-{\mu }_{0,total}}{{\mu }_{0,total}}}$$

(7)

3. Mechanical Stress Distribution and Different Shape of Fin

The stress distribution in the Fin channel under asymmetric STI stressors is shown in Figure 2. The Fin channel exhibits a significant asymmetric stress profile, primarily concentrated near the sidewall channels, with minimal impact on the top channel. This phenomenon is mainly attributed to the tall and narrow geometry of the Fin. Since STI is deposited along the channel direction, the asymmetric mechanical stress form STI has the greatest impact in the longitudinal direction, while the mechanical stress in the vertical direction remains nearly symmetric. The simulated mechanical stress distribution along both sidewalls of the Fin in the longitudinal direction is shown in Figure 2d, the distance refers to the x-direction along the vertical axis of the Fin, with the cutline positioned at a y-coordinate of 26.5 nm, perpendicular to the channel, the mechanical stress deviation between the two sidewalls reaches approximately 500 MPa. This results in carrier mobility variations in the sidewall channel, ultimately affecting device performance.

The stress distribution in the Fin channel also depends on the its width, as shown in Figure 3. Different Fin widths result in varying degrees of impact from asymmetric stress on device performance. The carrier mobility enhancement (∂μ_total) is used to characterize the offset in drain current caused by asymmetric stress. As shown in Figure 3, ∂μ_total increases from 3.62% to 8.30% in the linear region and from 3.27% to 8.42% in the saturation region as the Fin width decreases from 12 nm to 6 nm. As the Fin width increases, the mobility enhancement decreases significantly, indicating that tall and narrow Fin structures are more severely affected by asymmetric stress than wider Fins.

As shown in Figure 3, the mobility enhancement trends differ between the linear and saturation regions. This is because I_dlin, which is extracted in the linear region, is more directly influenced by low-field mobility variations, making it more sensitive to stress-induced changes. In contrast, I_dsat in the saturation region is governed by high-field effects, such as velocity saturation and channel length modulation, which can diminish the apparent impact of mobility changes. These physical distinctions result in the different trends observed between I_dlin and I_dsat under various stress conditions.

As shown in Figure 2, larger compressive stress extends from the STI to the sidewall channel of the Fin, diffusing toward the top and central regions. The asymmetric STI stress is mainly concentrated in the sidewall channel, with relatively little effect on the top channel. Consequently, as the Fin width continues to decrease, the proportion of current through the sidewall channel increases, leading to greater mobility enhancement and a stronger impact of asymmetric stress on the FinFET performance.

Additionally, a significant upward trend in mobility enhancement is observed for FinFETs with W = 6 nm. This is because, when the Fin is sufficiently wide, the top channel shows no significant dependence on asymmetric stress. The Stress YY of FinFETs with W = 6 nm and W = 8 nm is shown in Figure 4a,b, respectively. This asymmetry is primarily attributed to the two stress sources at the Fin corners, with a weaker influence on channel current. However, as the Fin width decreases, the stress sources at the Fin corners overlap, causing the top channel to become increasingly affected by asymmetric stress, becoming more similarly to the sidewall channel. This results in a sharp increase in mobility enhancement at W = 6 nm. Figure 4c,d show the distribution of Stress YY in the top channel of FinFETs with W = 6 nm and W = 8 nm, respectively. It can be observed that stress asymmetry in the top channel of the W = 6 nm FinFET is significantly higher than that of the W = 8 nm FinFET. These results indicate that as technology advances, Fins are evolving to become taller and narrower, making FinFET performance increasingly sensitive to asymmetric stress.

Moreover, it is well known that the Fin body angle also affects the performance of FinFET devices. Studies have shown that as the Fin body angle approaches 90°, both the drain-induced barrier lowering (DIBL) and subthreshold swing (SS) decrease accordingly [13,14]. Therefore, the research also investigated the relationship between the Fin body angle and the asymmetric stress introduced by STI.

As shown in Figure 5, as the top width of the Fin decreases from 8 nm to 6 nm, ∂μ_total increases from 5.59% to 7.45% in the saturation region, and from 5.86% to 7.65% in the linear region. This increase is primarily due to the narrowing of the FinFET top as the Fin body angle decreases. The trend of mobility enhancement mirrors the behavior observed with changes in Fin width. As the Fin body angle decreases, the impact of asymmetric stress on FinFET performance becomes more significant. A noticeable local decrease in mobility enhancement at a Fin body angle corresponding to a top width of 7 nm suggests a potential structural or electrostatic optimization at this geometry—possibly due to stress redistribution or increased surface scattering—which we plan to investigate further in future work. In practice, however, FinFET structures are influenced by the well-known miscut step phenomenon, rather than being ideally un-tapered and straight [15,16]. As a result, the deviation of the Fin body angle from 90° further exposes the device to the effects of asymmetric stress.

In addition to Fin width and CESL stress, the effect of Fin height on asymmetric stress performance is also worth noting. Since the STI-induced asymmetric stress primarily affects the sidewalls of the Fin channel, a taller Fin increases the relative contribution of the sidewall channel to the total current. This amplifies the influence of stress asymmetry on carrier transport and device variability. A more detailed investigation of Fin height effects on asymmetric stress will be conducted in our future work.

4. Mitigating the Impact of STI-Induced Asymmetric Stress

The impact of asymmetric stress introduced by STI on FinFETs is primarily concentrated in the sidewall channel, while the top channel current acts to counterbalance this effect. Therefore, to mitigate the effect of STI-induced asymmetric stress on device performance, a feasible process to enhance the top channel current is needed. Studies have shown that CESL stress engineering can significantly improve device performance [17].

As the first material layer deposited above the FinFET structure, CESL can efficiently transfer its intrinsic stress to the silicon channel. Due to the unique structure of FinFETs, CESL-induced stress is more effectively coupled to the top channel, while its influence on the sidewall channel is relatively weak [12]. This stress redistribution reduces the overall impact of STI-induced asymmetry on device behavior.

Figure 6 illustrates the dependence of mobility enhancement in the linear and saturation regions on the magnitude of CESL stress under different stress engineering conditions. As the intrinsic stress of CESL increases, the observed mobility enhancement decreases significantly. A lower CESL stress leads to higher measured mobility enhancement, as the CESL stress helps balance the STI-induced asymmetry. Therefore, the mobility enhancement does not reflect performance improvement, but rather stress imbalance. When the intrinsic stress of the CESL increases from 500 MPa to 2.0 GPa, the mobility enhancement decreases from 6% to 5%. The 2.0 GPa stress of the CESL contributes to a 20% improvement in device stability, reflecting better stress balance and reduced process-induced performance variation. These results demonstrate that CESL stress engineering is an effective approach to mitigating STI-induced asymmetric stress.

In fabrication processes, asymmetric stress introduced by STI is inevitable due to factors such as layout. However, thanks to the geometry of the Fin structure, CESL-induced stress is typically more symmetric. Therefore, using CESL stress engineering to counteract STI-induced asymmetric stress is considered feasible in actual manufacturing processes.

5. Conclusions

This paper provides an overview of the impact of STI-induced asymmetric stress on FinFET device performance through TCAD simulations. Due to the asymmetric stress introduced by STI, the stress distribution along the sidewall channels of the Fin becomes asymmetric, leading to variations in the carrier mobility caused by mechanical stress and ultimately degrading device stability. Furthermore, as the Fin width continues to decrease, the performance fluctuation caused by the asymmetric stress becomes more pronounced. At W = 6 nm, the maximum value of ∂μ_total in the saturation region reaches 8.42%.

In addition, as the Fin body angle deviates from 90° and the upper section narrows, asymmetric stress further amplifies performance variations, with ∂μ_total peaking at 7.65%. To mitigate these variations, CESL stress engineering is applied to counterbalance STI-induced asymmetric stress. A CESL stress of 2.0 GPa results in approximately 20% improvement in device stability, demonstrating the effectiveness of CESL stress engineering in suppressing performance fluctuation