Subthreshold Characteristics of AlGaN / GaN MIS-FinFETs with Controlling Threshold Voltages

: AlGaN / GaN metal-insulator-semiconductor ﬁeld-e ﬀ ect transistors with ﬁn structures (AlGaN / GaN MIS-FinFETs) were fabricated and characterized by changing ﬁn width and using di ﬀ erent dielectric layers. The FinFET with 20 nm-thick SiO 2 dielectric layer exhibits a very small subthreshold swing (SS) of 56 mV / decade. However, the threshold voltage of the device is too low to ensure low o ﬀ -state leakage current (at the gate voltage of 0 V), even though the ﬁn width of the device is reduced to 30 nm, which would not meet the requirement for low standby power consumption. On the other hand, the FinFET with a 10 nm-thick Al 2 O 3 dielectric layer and a much wider ﬁn width of 100 nm shows normally-o ﬀ operation with a threshold voltage of 0.8 V, SS of 63 mV / dec, and very low o ﬀ -state current of 1 nA / mm. When the ﬁn width is reduced to 40 nm, the threshold voltage of the FinFET is increased to 2.3 V and the SS is decreased to 52 mV / decade. These excellent switching performances convince us that the FinFETs might be promising either for low voltage logic or for e ﬃ cient power switching applications. The observed SS values, which are smaller than the theoretical Boltzmann limit (60 mV / decade), can be explained by the concept of the voltage-dependent e ﬀ ective channel width.


Introduction
AlGaN/GaN-based high electron mobility transistors (HEMTs) are very promising for high power and high-frequency applications due to their wide bandgap, large critical electric field, and high saturation velocity [1][2][3][4]. Recently, AlGaN/GaN metal-insulator-semiconductor field-effect transistors with fin structures (MIS-FinFETs) have been widely investigated to achieve better gate controllability and higher device linearity, compared with conventional planar HEMTs, which results in a great reduction of off-state leakage current (I OFF ), suppression of drain induced barrier lowering (DIBL), and improvement of subthreshold swing (SS) [5][6][7][8][9][10]. It is worth noting that the threshold voltage (V TH ) of the MIS-FinFET increases as the fin width (W fin ) decreases due to the lateral depletion of 2-dimensional electron gas (2DEG) channel by sidewall gate and eventually the device can show a normally-off operation when the W fin is reduced to a few tenths of a nanometer [11,12], without adapting additional process methods, such as recessed gate, P-GaN gate, thin AlGaN barrier layer, and cascode structure, usually applied to conventional planar HEMTs [13][14][15][16].
Our previous work demonstrated that AlGaN/GaN MIS-FinFETs with W fin of around 30 nm can show not only normally-off operation, but also extremely low I OFF as well as small SS (smaller than theoretical Boltzmann limit of < 60 mV/decade) [17]. These excellent performances of the AlGaN/GaN MIS-FinFETs suggest that the GaN-based materials, combined with novel nano-structure such as fin or nanowire, can offer an opportunity for a new possible low power logic device application [18][19][20], in addition to conventional efficient power switching device application which requires a relatively large positive V TH to ensure safe device operation as well as low standby power consumption. For low-power logic applications, however, it is better to keep the V TH of the device low as long as the off-state leakage current (I OFF ; at gate voltage, V G = 0 V) is low, which can be achieved with very steep SS.
In this work, two different AlGaN/GaN MIS-FinFETs with either 20 nm-thick SiO 2 or 10 nm-thick Al 2 O 3 dielectric layers were characterized to investigate the effects of the fixed oxide charge and the surface trap at the GaN/dielectric interface on the device performances with varying the W fin . In addition, the MIS-FinFETs with different sidewall planes, either steep m-plane or sloped plane (12 • off-angle to m-plane), were also characterized for the same purpose.

Device Fabrication
Epitaxial layers of 2 µm-thick highly resistive undoped GaN, 50 nm-thick GaN channel layer and 25 nm-thick Al 0.25 Ga 0.75 N barriers were sequentially grown on the sapphire substrate by using metal-organic chemical vapor deposition (MOCVD). The 2DEG density of 8.83×10 12 cm −2 and the electron mobility of 1800 cm 2 ·V −1 ·s −1 were estimated by Hall measurement. Figure 1a shows the schematic image of AlGaN/GaN MIS-FinFET. The fabrication processes of the FinFETs were similar to our previous work [17]. Figure 1b,c exhibit the cross-sectional TEM images for the fin with sloped and steep sidewall surface, respectively. It was found that the formation of fin shape depends on the etching time in anisotropic lateral etching tetramethylammonium hydroxide (TMAH: 25% solution at 85°C) solution. It was also found the slope of the dry-etched fin, prior to the TMAH wet etching, is important in determining the fin shape. However, the exact etching mechanism for the fin shape still remains unclear and further study is required. It is worth noting that, as shown Figure 1b, the sloped sidewall surface has~12 • off-angle to the m-plane, while the top AlGaN layer has a negatively sloped shape with almost the same off-angle as shown in both Figure 1b,c. This negative slope might be due to the existence of stress induced by lattice mismatch between AlGaN and GaN layers, which increases the etch rate at the interface during TAMH wet etching.
Electronics 2020, 10, x FOR PEER REVIEW 2 of 9 low-power logic applications, however, it is better to keep the VTH of the device low as long as the off-state leakage current (IOFF; at gate voltage, VG = 0 V) is low, which can be achieved with very steep SS. In this work, two different AlGaN/GaN MIS-FinFETs with either 20 nm-thick SiO2 or 10 nm-thick Al2O3 dielectric layers were characterized to investigate the effects of the fixed oxide charge and the surface trap at the GaN/dielectric interface on the device performances with varying the Wfin. In addition, the MIS-FinFETs with different sidewall planes, either steep m-plane or sloped plane (12˚ off-angle to m-plane), were also characterized for the same purpose.

Device Fabrication
Epitaxial layers of 2 μm-thick highly resistive undoped GaN, 50 nm-thick GaN channel layer and 25 nm-thick Al0.25Ga0.75N barriers were sequentially grown on the sapphire substrate by using metal-organic chemical vapor deposition (MOCVD). The 2DEG density of 8.83×10 12 cm -2 and the electron mobility of 1800 cm 2 •V -1 •s -1 were estimated by Hall measurement. Figure 1a shows the schematic image of AlGaN/GaN MIS-FinFET. The fabrication processes of the FinFETs were similar to our previous work [17]. Figure 1b,c exhibit the cross-sectional TEM images for the fin with sloped and steep sidewall surface, respectively. It was found that the formation of fin shape depends on the etching time in anisotropic lateral etching tetramethylammonium hydroxide (TMAH: 25% solution at 85 ℃) solution. It was also found the slope of the dry-etched fin, prior to the TMAH wet etching, is important in determining the fin shape. However, the exact etching mechanism for the fin shape still remains unclear and further study is required. It is worth noting that, as shown Figure 1b, the sloped sidewall surface has ~ 12° off-angle to the m-plane, while the top AlGaN layer has a negatively sloped shape with almost the same off-angle as shown in both Figure 1b,c. This negative slope might be due to the existence of stress induced by lattice mismatch between AlGaN and GaN layers, which increases the etch rate at the interface during TAMH wet etching. The dielectrics, 20 nm-thick plasma enhanced chemical vapor deposited (PECVD) SiO2 layer and 10 nm-thick atomic layer deposited (ALD) Al2O3 layer, were used to investigate the influence of different dielectric layer on device performance. The gate length (LG), which corresponds to fin length (Lfin), and the mesa width for all devices are 1 and 50 μm, respectively. Both of the gate to drain spacing LGD and the gate to source spacing LGS are 5 μm.  The dielectrics, 20 nm-thick plasma enhanced chemical vapor deposited (PECVD) SiO 2 layer and 10 nm-thick atomic layer deposited (ALD) Al 2 O 3 layer, were used to investigate the influence of different dielectric layer on device performance. The gate length (L G ), which corresponds to fin length (L fin ), and the mesa width for all devices are 1 and 50 µm, respectively. Both of the gate to drain spacing L GD and the gate to source spacing L GS are 5 µm. The fin height (H fin ) is 100 nm and the W fin varies from 30 to 150 nm. All the devices have a fin number (N fin ) of 45. Drain current (I D ) and transconductance (g m ) are normalized by gate width (W G ) = W f in + width o f GaN channel (50 nm) × 2 × N f in , and V TH is defined as the V G when drain current I D equals to 0.1 µA × The key parameters such as V TH , SS, g m peak value, full width at half maximum (FWHM) of g m , and hysteresis of all the devices are summarized and shown in Table 1. The V TH of the sloped FinFET with W fin is 150 nm is −1.9 V and it shifts to a positive direction as the W fin narrows, showing the V TH of 0.3 V when W fin is reduced to 30 nm. This positive shift of the V TH is due to lateral depletion of the 2DEG channel from the sidewall. The SS values for all devices are smaller than 72 mV/dec, which are relatively low compared to those of conventional AlGaN/GaN-based HEMTs [21][22][23]. For the wide FinFETs with W fin of 150 and 80 nm, the V TH of the 2DEG channel is much lower than that of the MOS channel at sidewall surface and hence the 2DEG channel current dominates the subthreshold current of the device. In this case, the SS (~70 mV/dec) for the device can be mainly determined from the trap capacitance at AlGaN/GaN interface (C it,AlGaN/GaN ) and the existence of the depletion capacitance (C dep ) in wide bottom fin body below the 2DEG channel, which is not completely depleted by the lateral electric field from the sidewall gate. Besides, the V TH difference between the 2DEG channel and MOS channel of these FinFETs with wide W fin are relatively large and the two-channel currents become merged as the gate voltage increases to have the broad g m curves as shown in Figure 2c, which is important in improving the device linearity [8,24]. The key parameters such as VTH, SS, gm peak value, full width at half maximum (FWHM) of gm, and hysteresis of all the devices are summarized and shown in Table 1. The VTH of the sloped FinFET with Wfin is 150 nm is −1.9 V and it shifts to a positive direction as the Wfin narrows, showing the VTH of 0.3 V when Wfin is reduced to 30 nm. This positive shift of the VTH is due to lateral depletion of the 2DEG channel from the sidewall. The SS values for all devices are smaller than 72 mV/dec, which are relatively low compared to those of conventional AlGaN/GaN-based HEMTs [21][22][23]. For the wide FinFETs with Wfin of 150 and 80 nm, the VTH of the 2DEG channel is much lower than that of the MOS channel at sidewall surface and hence the 2DEG channel current dominates the subthreshold current of the device. In this case, the SS (~ 70 mV/dec) for the device can be mainly determined from the trap capacitance at AlGaN/GaN interface (Cit,AlGaN/GaN) and the existence of the depletion capacitance (Cdep) in wide bottom fin body below the 2DEG channel, which is not completely depleted by the lateral electric field from the sidewall gate. Besides, the VTH difference between the 2DEG channel and MOS channel of these FinFETs with wide Wfin are relatively large and the two-channel currents become merged as the gate voltage increases to have the broad gm curves as shown in Figure 2c, which is important in improving the device linearity [8,24].    On the other hand, the narrow FinFET with W fin of 45 nm has a sharper and higher g m peak as can be seen in Figure 2c, which means that the V TH of the 2DEG channel and MOS channel are almost the same and hence both channels simultaneously turn on/off and the effective channel width of the device can be modulated with the gate voltage, which results in very small SS as low as 56 mV/dec, smaller than the theoretical Boltzmann limit of 60 mV/dec. As discussed in our previous work [17], the 2DEG channel will be generated at the center of the 2DEG channel and laterally spread until occupying the whole 2DEG channel as V G increases from the V TH of the 2DEG channel to just above it. Then, the MOS channel will instantaneously turn on because there is only a tiny V TH difference between the top 2DEG channel and the sidewall MOS channel. In other words, the channel width first spread laterally within the 2DEG channel and then immediately spread vertically into the MOS channel, which makes the concept of gate-dependent effective channel width modulation reasonable. This sub-60 mV/dec SS can be understood by considering the expression for new SS W(V G ) which includes the gate voltage-dependent channel width modulation [17] as shown below,

Results and Discussion
In these equations, ϕ s and Q ch (V, ϕ s ) are the surface potential and the channel charges in the subthreshold region, respectively. W (ϕ s ) is the surface potential-dependent effective channel width which is constant in conventional devices. I D,sub is the channel current in the subthreshold region and d(logI D,sub ) dV G is the differentiation of the logarithmic channel current. The first term is the channel width modulation and expressed as A in Equation (1). The third term is related to electron mobility and can be neglected. The inverse of the second term is SS con for conventional devices without channel width modulation. SS con can be expressed as, where k is the Boltzmann's constant, T is temperature, q is electronic charge, C ox is the capacitance for gate oxide, and C it is the trap capacitance either for the interface of AlGaN/GaN or dielectric/GaN. Normally, SS con is larger than 60 mV/dec and cannot explain the sub-60 mV/dec characteristic observed in this work. When W fin is further reduced to 30 nm, the SS of the device increases slightly above 60 mV/dec again. This is because the V TH of the 2DEG channel increases and hence the simultaneous turning on of these two channels tends to break to make the channel width modulation less effective. The V TH of the 2DEG channel becomes higher than that of the MOS channel and becomes positive to show normally-off operation with V TH of 0.3 V. In this case, the MOS channel current at sidewall surface dominates the subthreshold characteristics of the device and the SS can be determined mainly from the trap capacitance (C it, SiO 2 /GaN ) at SiO 2 /GaN interface, which leads to increased SS of 63 mV/dec. As a result, Figure 2c indicates that the g m of the FinFET with W fin of 30 nm becomes slightly broader and the peak value becomes lower again compared with that of FinFET with W fin of 45 nm. As can be seen in Figure 2a, SS first decreases below 60 mV/dec when W fin is reduced to 45 nm and then increases again above 60 mV/dec with further decreasing W fin , which depends on whether the 2DEG channel and MOS channel turn on at the same time or not as has already been discussed above. Correspondingly, with decreasing W fin , as shown in Figure 2c, g m curve becomes sharper as W fin decreases to 45 nm, but becomes broad again when W fin is reduced to 30 nm. Based on the tendency of SS and g m curves as decreasing W fin as shown in Figure 2a,b, it can be concluded that the g m peak becomes sharp showing excellent subthreshold characteristics with SS of sub-60 mV/dec, if 2DEG channel and MOS channel of a FinFET are simultaneously turned on/off. However, most of the FinFETs with SiO 2 dielectric layer investigated in this work exhibits normally-on operation, thus they are not adequate to be used as efficient power switching or low power logic application due to large I OFF , even though they exhibited excellent SS. A similar argument can be addressed even for the normally-off FinFET with W fin of 30 nm, because I OFF of the FinFET is still very high due to its low V TH . Figure 3a shows the comparison of the logarithmic transfer curves obtained from the FinFETs with sloped and steep sidewall surfaces. It is observed that the steep sidewall surface is m-plane and very smooth and uniform and has the lowest surface trap density, while the sloped sidewall has a rather rough and nonuniform surface, as shown in Figure 1b. The key parameters such as V TH , SS, g m peak value, and FWHM of g m of all the devices are summarized and shown in Table 2. Both devices, which have the same W fin of 30 nm and 20 nm-thick SiO 2 gate dielectric layer, exhibit normally-off operation, but the sloped sidewall device exhibits much higher I OFF of 100 nA/mm, measured at V G = 0 V, compared with that of steep sidewall device. The high I OFF of the sloped sidewall device is due to its lower V TH of 0.3 V, compared to V TH of 0.6 V of the steep sidewall device. The lower V TH of the sloped device is probably because the sidewall surface has a higher density of positive effective oxide charge at the GaN/SiO 2 interface as well as higher surface trap density caused by a relatively rough surface, compared to the steep m-plane sidewall surface [25]. This high positive oxide charge density in the sloped device lowers V TH of the sidewall MOS channel to increase I OFF . The SS of steep sidewall device is as low as 37 mV/dec due to the simultaneous turning on of 2DEG channel and MOS channel and the effective channel width modulation as discussed before [17]. On the other hand, the sloped sidewall device exhibits a relatively larger SS of 63 mV/dec, which could be explained by the existence of non-negligible C dep caused by the undepleted part at the wide fin bottom and relatively large C it, SiO 2 /GaN due to a rough sidewall surface [25], which increases both SS con and SS W(V G ) , while the C dep can be ignored for the device with a steep sidewall because the entire fin is narrow and completely depleted from the electric field of the sidewall gate at off-state. The schematic images of both sloped and steep sidewall fin structures with un-depleted/depleted areas are shown in Figure 3b. The steep sidewall device exhibits a sharper and higher g m peak, as shown in Figure 3b, which indicates that both the 2DEG channel and the MOS channel of the device simultaneously turn on almost at the same time.
Electronics 2020, 10, x FOR PEER REVIEW 5 of 9 IOFF, even though they exhibited excellent SS. A similar argument can be addressed even for the normally-off FinFET with Wfin of 30 nm, because IOFF of the FinFET is still very high due to its low VTH. Figure 3a shows the comparison of the logarithmic transfer curves obtained from the FinFETs with sloped and steep sidewall surfaces. It is observed that the steep sidewall surface is m-plane and very smooth and uniform and has the lowest surface trap density, while the sloped sidewall has a rather rough and nonuniform surface, as shown in Figure 1b. The key parameters such as VTH, SS, gm peak value, and FWHM of gm of all the devices are summarized and shown in Table 2. Both devices, which have the same Wfin of 30 nm and 20 nm-thick SiO2 gate dielectric layer, exhibit normally-off operation, but the sloped sidewall device exhibits much higher IOFF of 100 nA/mm, measured at VG = 0 V, compared with that of steep sidewall device. The high IOFF of the sloped sidewall device is due to its lower VTH of 0.3 V, compared to VTH of 0.6 V of the steep sidewall device. The lower VTH of the sloped device is probably because the sidewall surface has a higher density of positive effective oxide charge at the GaN/SiO2 interface as well as higher surface trap density caused by a relatively rough surface, compared to the steep m-plane sidewall surface [25]. This high positive oxide charge density in the sloped device lowers VTH of the sidewall MOS channel to increase IOFF. The SS of steep sidewall device is as low as 37 mV/dec due to the simultaneous turning on of 2DEG channel and MOS channel and the effective channel width modulation as discussed before [17]. On the other hand, the sloped sidewall device exhibits a relatively larger SS of 63 mV/dec, which could be explained by the existence of non-negligible caused by the undepleted part at the wide fin bottom and relatively large , 2 / due to a rough sidewall surface [25], which increases both and ( ) , while the can be ignored for the device with a steep sidewall because the entire fin is narrow and completely depleted from the electric field of the sidewall gate at off-state. The schematic images of both sloped and steep sidewall fin structures with un-depleted/depleted areas are shown in Figure  3b. The steep sidewall device exhibits a sharper and higher gm peak, as shown in Figure 3b, which indicates that both the 2DEG channel and the MOS channel of the device simultaneously turn on almost at the same time.    To investigate the effect of the gate dielectric on the device performances, the SiO 2 layer was replaced with 10 nm-thick Al 2 O 3 layers on the sloped sidewall FinFETs. All FinFETs with W fin varied from 130 to 40 nm exhibit normally-off operation as shown in Figure 4a,b. The key parameters such as V TH , SS, g m peak value, FWHM of g m , and hysteresis of all the devices are summarized and shown in Table 3. Similarly, V TH of the FinFET shifts to a positive direction as W fin decreases, but it increases up to a much higher value of 2.5 V for the FinFET with W fin of 40 nm, which is probably due to the existence of the negative effective oxide charge at the interface between the Al 2 O 3 dielectric layer and GaN [5,26,27].
Electronics 2020, 10, x FOR PEER REVIEW 6 of 9 as VTH, SS, gm peak value, FWHM of gm, and hysteresis of all the devices are summarized and shown in Table 3. Similarly, VTH of the FinFET shifts to a positive direction as Wfin decreases, but it increases up to a much higher value of 2.5 V for the FinFET with Wfin of 40 nm, which is probably due to the existence of the negative effective oxide charge at the interface between the Al2O3 dielectric layer and GaN [5,26,27].  It is also observed that the FinFETs show considerably low IOFF of ~ 0.1 nA/mm, except the FinFET with Wfin of 130 nm, which is essential for reducing the standby power consumption. Especially, the FinFET with Wfin of 40 nm exhibits excellent SS of 52 mV/dec, also smaller than the theoretically limited value of 60 mV/dec, which can be explained by the concept of effective channel width modulation and the simultaneous turn-on of 2DEG channel and MOS channel as discussed before. This fast switching characteristics of the device with its relatively high VTH of 2.5 V and low off-state leakage current would lead to improvement of efficiency and ensure the safety of power switching devices [28]. The gm peak becomes sharper as the Wfin of the FinFET decreases, as shown  It is also observed that the FinFETs show considerably low I OFF of~0.1 nA/mm, except the FinFET with W fin of 130 nm, which is essential for reducing the standby power consumption. Especially, the FinFET with W fin of 40 nm exhibits excellent SS of 52 mV/dec, also smaller than the theoretically limited value of 60 mV/dec, which can be explained by the concept of effective channel width modulation and the simultaneous turn-on of 2DEG channel and MOS channel as discussed before. This fast switching characteristics of the device with its relatively high V TH of 2.5 V and low off-state leakage current would lead to improvement of efficiency and ensure the safety of power switching devices [28]. The g m peak becomes sharper as the W fin of the FinFET decreases, as shown in Figure 4b, which is similar to the case of the FinFETs with SiO 2 gate dielectric layer and a similar argument can be also addressed for the reason.
According to the discussion above, it can be seen that it is a possible method to realize relatively high V TH , small SS, and low I OFF in AlGaN/GaN MIS-FinFETs by carefully adjusting W fin as well as choosing the sidewall plane, which corresponds to the controlling of threshold voltages. As W fin varies, the shape of g m curve becomes sharper as the V TH difference between the 2DEG channel and the MOS channel becomes closer.

Conclusions
In this work, AlGaN/GaN MIS-FinFETs were fabricated and characterized using 20 nm-thick SiO 2 and 10 nm-thick Al 2 O 3 as dielectric layers, respectively. The effects of the sidewall plane on device performance were also investigated. The sloped sidewall FinFET with 20 nm-thick SiO 2 dielectric layers and W fin of 45 nm shows the lowest SS of 56 mV/dec among the FinFETs which can be explained by the concept of effective channel width modulation and the simultaneous turn-on of 2DEG channel and sidewall MOS channel. The SS is further decreased to 37 mV/dec for the steep sidewall FinFET with W fin of 30 nm. However, the sloped sidewall FinFET with the same W fin of 30 nm, which has a relatively rough sidewall surface, show low V TH , large SS, and high I OFF probably due to the high density of positive effective fixed oxide charges and trap charges at the SiO 2 /GaN interface. On the other hand, the sloped sidewall FinFETs with 10 nm-thick Al 2 O 3 dielectric layer show normally-off operation with relatively high V TH , small SS, and low I OFF . In our opinion, these performances are probably due to the existence of negative effective fixed oxide charge at the Al 2 O 3 /GaN interface, even though the FinFETs have sloped sidewalls. The device with W fin of 40 nm exhibits SS of 52 mV/dec with V th of 2.3 V, which might be promising for efficient power switching application.