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J. Low Power Electron. Appl. 2015, 5(3), 165-182;

A Cross-Layer Framework for Designing and Optimizing Deeply-Scaled FinFET-Based Cache Memories

Department of Electrical Engineering, University of Southern California, Los Angeles, CA 90089,USA
This paper is an extended version of our paper published in The IEEE S3S Conference 2014, entitled “A Cross-Layer Design Framework and Comparative Analysis of SRAM Cells and Cache Memories using 7 nm FinFET Devices”.
Author to whom correspondence should be addressed.
Academic Editors: David Bol and Steven A. Vitale
Received: 3 March 2015 / Revised: 23 June 2015 / Accepted: 28 July 2015 / Published: 11 August 2015
(This article belongs to the Special Issue Selected Papers from IEEE S3S Conference 2014)
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This paper presents a cross-layer framework in order to design and optimize energy-efficient cache memories made of deeply-scaled FinFET devices. The proposed design framework spans device, circuit and architecture levels and considers both super- and near-threshold modes of operation. Initially, at the device-level, seven FinFET devices on a 7-nm process technology are designed in which only one geometry-related parameter (e.g., fin width, gate length, gate underlap) is changed per device. Next, at the circuit-level, standard 6T and 8T SRAM cells made of these 7-nm FinFET devices are characterized and compared in terms of static noise margin, access latency, leakage power consumption, etc. Finally, cache memories with all different combinations of devices and SRAM cells are evaluated at the architecture-level using a modified version of the CACTI tool with FinFET support and other considerations for deeply-scaled technologies. Using this design framework, it is observed that L1 cache memory made of longer channel FinFET devices operating at the near-threshold regime achieves the minimum energy operation point. View Full-Text
Keywords: memory design; FinFET devices; deeply-scaled technologies; cache memories memory design; FinFET devices; deeply-scaled technologies; cache memories

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This is an open access article distributed under the Creative Commons Attribution License which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited (CC BY 4.0).

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Shafaei, A.; Chen, S.; Wang, Y.; Pedram, M. A Cross-Layer Framework for Designing and Optimizing Deeply-Scaled FinFET-Based Cache Memories. J. Low Power Electron. Appl. 2015, 5, 165-182.

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