Effects of Varying the Fin Width, Fin Height, Gate Dielectric Material, and Gate Length on the DC and RF Performance of a 14-nm SOI FinFET Structure

The FinFET architecture has attracted growing attention over the last two decades since its invention, owing to the good control of the gate electrode over the conductive channel leading to a high immunity from short-channel effects (SCEs). In order to contribute to the advancement of this rapidly expanding technology, a 3D 14-nm SOI n-FinFET is performed and calibrated to the experimental data from IBM by using Silvaco TCAD tools. The calibrated TCAD model is then investigated to analyze the impact of changing the fin width, fin height, gate dielectric material, and gate length on the DC and RF parameters. The achieved results allow gaining a better understanding and a deeper insight into the effects of varying the physical dimensions and materials on the device performance, thereby enabling the fabrication of a device tailored to the given constraints and requirements. After analyzing the optimal values from different changes, a new device configuration is proposed, which shows a good improvement in electrical characteristics.


Introduction
The structure of the fin field-effect transistor (FinFET) has completely emerged as a promising design solution for CMOS logic and memory circuit design because of its good immunity to short channel effects (SCEs) [1][2][3]. This technology enables the creation of high-performance ultra-scaled, high-density integration, and high-performance silicon (Si) chips [1][2][3][4]. In the silicon industry, device miniaturization is still considered a key feature to achieve better short-channel performance. Currently, a great effort concerns the development of FinFET devices with dimensions below 5 nm that represent the target in the near future [4][5][6][7][8]. Despite the effort made to create devices with dimensions below 5 nm, many aspects still remain to be clarified and optimized, also with a view to a larger-scale application of the devices. This paper presents an investigation of 3D 14-nm FinFET on thin silicon on insulator (SOI) wafer using Silvaco tools. The SOI technology shows significantly large improvement compared to the previous FinFET technology. For better Si channel controllability, hafnium oxide (HfO 2 ) was used to cover the Si channel as a gate dielectric. The impact of varying the fin width (W fin = 4, 6.5, 15, and 20 nm), fin height (H fin = 10, 15, 20, 25, 30, and 35 nm), gate dielectric materials (TiO 2 , La 2 O 3 , HfO 2 , Al 2 O 3 , Si 3 N 4 , and SiO 2 ), and gate length (L g = 5, 10, 15, and 20 nm) on the DC and RF performance of the considered structure is carefully analyzed and discussed. The analysis is performed by investigating the following parameters: threshold voltage (V th ), subthreshold slope (SS), drain-induced barrier lowering (DIBL), on-state current (I on ), off-state current (I off ), I on /I off ratio, transconductance (g m ), gate capacitance (C gg ), and cut-off frequency (f T ). The development of a comparative analysis enables gaining a better understanding of how to improve device performance, depending on the given fabrication constraints and application requirements.
It should be underlined that the great interest in the FinFET technology is witnessed by the many papers that have been published over the years to investigate the FinFET performance by using both TCAD simulations [8][9][10][11][12][13] and measurements [14][15][16][17][18]. Although a measurement-based investigation is a mandatory step prior to the use of a device in real applications, the TCAD simulation is considered a powerful and costless type of analysis to optimize device performance. This is because the TCAD tool allows predicting how the device performance changes by varying the design parameters without the need for time-consuming and costly experiments [13].
The rest of this paper is structured as follows: Section 2 presents the device structure, Section 3 describes the developed model for the achieved simulations, Section 4 reports and discusses the obtained findings; and the last section concludes the paper.

Device Structure
The 3D 14-nm SOI FinFET device has been simulated using Silvaco TCAD. Figure 1 shows the 3D schematic diagram of the FinFET device with a physical gate length (L g ) of 20 nm. The geometrical parameters and material properties are specified in previously published papers [1][2][3]. HfO 2 is used as a gate dielectric material. The doping densities of the source (n-type), drain (n-type), and covered fin (p-type) region were 1 × 10 21 cm −3 , 1 × 10 21 cm −3 , and 1 × 10 16 cm −3 , respectively. The contact resistance of 1 × 10 −9 Ω.cm 2 was selected for the source/drain region. Table 1 illustrates the physical parameters of the investigated model.

Simulation Model
For device simulation, CVT, CCSMOB, ANALYTIC, BGN, SRH, and Auger nation were also included. Fermi-Dirac distribution has been enabled. For quant finement, the BQP model was considered [13]. By considering a FinFET device b using one single fin, the effective channel width can be estimated as follows where Hfin is the fin height and Wfin is the fin width.
The electron (n) and hole (p) densities with BQP equation can be expressed − ( + ) Figure 1. Structure of 3D 14-nm SOI n-FinFET device with a single fin.

Simulation Model
For device simulation, CVT, CCSMOB, ANALYTIC, BGN, SRH, and Auger recombination were also included. Fermi-Dirac distribution has been enabled. For quantum confinement, the BQP model was considered [13]. By considering a FinFET device based on using one single fin, the effective channel width can be estimated as follows where H fin is the fin height and W fin is the fin width. The electron (n) and hole (p) densities with BQP equation can be expressed by [13] N c and N v are the effective density of states for electrons and holes, respectively. E c and E v are the conduction and valence bands, respectively. k is the Boltzmann constant, T L is the local lattice temperature, q is the electric charge, Q is the quantum potential, M −1 is the inverse effective mass tensor, and γ and α are two adjustable parameters.

Device Validation
Initially, the investigated 14-nm SOI n-FinFET model was carefully calibrated according to the experimental data in [1]. In order to match the simulated I-V curves with the experimental data from IBM [1], some physical parameters such as the doping density, thickness, source/drain extension length, and gate work function were carefully adjusted. Figure 2 illustrates simulated I-V characteristics at two different values of V ds : 0.05 V (linear) and 0.8 V (saturation). I-V model curves exactly match with the experimental as is observed at both bias conditions. The device characteristics of the investigated model are compared to the experimental outputs [1] and presented in Table 2. To further validate the developed model, the simulation results were compared also to Sun's work [2]. Figure 3 presents the output I-V characteristics of the investigated model at different gate-source voltages. Figure 3 shows a non-zero current for V gs just above V th and the increase in I ds with increasing input voltage V gs .   To evaluate the SCEs, the subthreshold slope (SS) and drain-induced barrier lowering (DIBL) are extracted as follows [4,11] = ( )     To evaluate the SCEs, the subthreshold slope (SS) and drain-induced barrier lowering (DIBL) are extracted as follows [4,11] = ( ) To evaluate the SCEs, the subthreshold slope (SS) and drain-induced barrier lowering (DIBL) are extracted as follows [4,11] where V gs is the gate-source voltage and I ds,sat is the drain current (under saturated biasing condition). V th,sat and V th,lin are the threshold voltages under saturated and linear conditions, respectively. The values of SS and DIBL are, respectively, 61 mV/dec and 43.32 mV/V for the 14-nm n-FinFET. These parameters are approximately maintained the same as the ones reported in papers [1][2][3][4].
The cut-off frequency (f T ) is considered as a crucial RF parameter which defines the speed response of the RF circuit design. The f T can be expressed by [14][15][16][17] where g m is the transconductance, C gg is the total gate capacitance, C gs is the gate-source capacitance, and C gd is the gate-drain capacitance.

Results and Discussion
In this section, the effects of changing the fin width, the fin height, the gate dielectric material, and the gate length on the device performance are analyzed and investigated for the SOI FinFET structure under study. The investigated tri-gate FinFET device has a 3D channel as illustrated in Figure 1. The model was calibrated with an agreement to IBM's model (see Figure 2). The electrical characteristics of the FinFET device are evaluated at a room temperature of 300 K.

Effects of the Fin Width/Height on Device Performance
In this study, it is important to start by investigating the effect of different fin size ratios on device characteristics. To analyze the impact of the fin width on the device performance, the fin width of the studied structure was varied from 4 nm to 20 nm with the fin height kept fixed at 26 nm. It should be underlined that, although a larger fin width allows enlarging the total gate width (see Equation (1)), when the gate length shrinks, the W fin width has to shrink as well in order to maintain an efficient suppression of the SCEs [19]. Figure 4 reports the effect of changing the fin width on the transfer I-V characteristics and the corresponding transconductance (Triangle symbols) for the investigated device. As can be clearly observed, the increase in the fin width leads to a reduction of the threshold voltage, in agreement with what is expected from previous studies [18]. In addition, owing to the increase of the total gate width (see Equation (1)), a larger fin width implies an increase in the drain current and transconductance [9,18]. Figure 5 shows the total gate capacitance versus V gs for the studied device with different values of the fin width. As can be seen, as V gs increases, C gg increases until its value becomes roughly constant [4]. The value of C gg decreases by decreasing the fin width, due to the reduction of the total gate width. Figure 6 shows f T variation as a function of V gs for the studied device with different values of the fin width. The peak in f T increases as W fin reduces. The behavior of f T is mainly due to the impact of the fin width on C gg rather than on g m , as can be observed from Figures 4-6. The peak point of f T is 3.9 THz at V gs = 0.21 V with a V ds = 0.05 V for a device with a fin width of 4 nm.            The variations of the threshold voltage, subthreshold slope, on-current, and off-current with different values of the fin height (H fin = 10, 15, 20, 25, 30, and 35 nm) and of the fin width (W fin = 4, 6.5, 15, and 20 nm) are shown in Figures 7-10, respectively. Figure 7 shows a reduction in the threshold voltage with increasing H fin and/or W fin . Figure 8 shows the impact of H fin on the subthreshold slope for FinFET devices with different values of W fin at V ds = 0.05 V. This figure shows a slight impact of changing H fin on SS when considering the lower values of the fin width (i.e., 6.5 nm and 4 nm), whereas a marked increase in SS is observed with increasing H fin and/or W fin when considering higher values of the fin width. It was observed that, for the studied FinFETs, a smaller fin width leads to better device performance in terms of SS. This confirms that studying the impact of varying fin width and fin height is essential for enabling technology development, since they can have a strong impact on the short channel effects. As expected, the increase in the gate width by increasing H fin and/or W fin leads to an increase in both on-state current and off-state current, as reported in Figures 9 and 10. Figure 9 shows the impact of H fin on the switching current (I on ) for FinFET devices with different W fin at V gs = V ds = 0.8 V. It is achieved a rapid increase in I on as W fin and/or H fin increase. Figure 10 shows the impact of H fin on the leakage current (I off ) for FinFET devices with different W fin at V gs = 0 V and V ds = 0.8 V. It is achieved a clear decrease in I off as W fin and/or H fin decrease. In particular, Figure 10 shows a slighter impact of changing H fin on I off when considering the lower values of the fin width (i.e., 6.5 nm and 4 nm), whereas a more marked decrease in I off is observed with decreasing H fin and/or W fin when considering higher values of the fin width. The electrostatic can be improved effectively with shorter fin width, which can report better mitigation of the leakage current for the nanoscale devices. This could be a good design strategy to enhance device performance, but it will be quite difficult to fabricate the pattern on the device with a very high aspect ratio (H fin /W fin ). For a given variation in the fin height, the corresponding change in the device performance of the investigated FinFET model can be linked to what was reported and discussed in detail in Kurniawan's work [20]. shows a reduction in the threshold voltage with increasing Hfin and/or Wfin. Figure 8 shows the impact of Hfin on the subthreshold slope for FinFET devices with different values of Wfin at Vds = 0.05 V. This figure shows a slight impact of changing Hfin on SS when considering the lower values of the fin width (i.e., 6.5 nm and 4 nm), whereas a marked increase in SS is observed with increasing Hfin and/or Wfin when considering higher values of the fin width. It was observed that, for the studied FinFETs, a smaller fin width leads to better device performance in terms of SS. This confirms that studying the impact of varying fin width and fin height is essential for enabling technology development, since they can have a strong impact on the short channel effects. As expected, the increase in the gate width by increasing Hfin and/or Wfin leads to an increase in both on-state current and off-state current, as reported in Figures 9 and 10. Figure 9 shows the impact of Hfin on the switching current (Ion) for FinFET devices with different Wfin at Vgs = Vds = 0.8 V. It is achieved a rapid increase in Ion as Wfin and/or Hfin increase. Figure 10 shows the impact of Hfin on the leakage current (Ioff) for FinFET devices with different Wfin at Vgs = 0 V and Vds = 0.8 V. It is achieved a clear decrease in Ioff as Wfin and/or Hfin decrease. In particular, Figure 10 shows a slighter impact of changing Hfin on Ioff when considering the lower values of the fin width (i.e., 6.5 nm and 4 nm), whereas a more marked decrease in Ioff is observed with decreasing Hfin and/or Wfin when considering higher values of the fin width. The electrostatic can be improved effectively with shorter fin width, which can report better mitigation of the leakage current for the nanoscale devices. This could be a good design strategy to enhance device performance, but it will be quite difficult to fabricate the pattern on the device with a very high aspect ratio (Hfin/Wfin). For a given variation in the fin height, the corresponding change in the device performance of the investigated FinFET model can be linked to what was reported and discussed in detail in Kurniawan's work [20].    As is well-known, a higher Ion is well desired while the leakage current Ioff should be kept low in order to minimize the static power consumption. Figure 11 shows the effect of varying the fin height and the fin width on the Ion/Ioff ratio, which is a crucial figure of merit for digital applications. As shown in Figure 11, the Ion/Ioff ratio decreases with increasing Hfin and/or Wfin. It should be noticed that the highest value of the Ion/Ioff ratio occurs   As is well-known, a higher Ion is well desired while the leakage current Ioff should be kept low in order to minimize the static power consumption. Figure 11 shows the effect of varying the fin height and the fin width on the Ion/Ioff ratio, which is a crucial figure of merit for digital applications. As shown in Figure 11, the Ion/Ioff ratio decreases with increasing Hfin and/or Wfin. It should be noticed that the highest value of the Ion/Ioff ratio occurs   As is well-known, a higher Ion is well desired while the leakage current Ioff should be kept low in order to minimize the static power consumption. Figure 11 shows the effect of varying the fin height and the fin width on the Ion/Ioff ratio, which is a crucial figure of merit for digital applications. As shown in Figure 11, the Ion/Ioff ratio decreases with increasing Hfin and/or Wfin. It should be noticed that the highest value of the Ion/Ioff ratio occurs As is well-known, a higher I on is well desired while the leakage current I off should be kept low in order to minimize the static power consumption. Figure 11 shows the effect Electronics 2022, 11, 91 9 of 17 of varying the fin height and the fin width on the I on /I off ratio, which is a crucial figure of merit for digital applications. As shown in Figure 11, the I on /I off ratio decreases with increasing H fin and/or W fin . It should be noticed that the highest value of the I on /I off ratio occurs at the lowest height of 10 nm and then decreases approximately exponentially with increasing H fin .

Impact of High-k Dielectric Materials on Device Performance
To analyze the effect of the gate dielectric materials on the device performance, the fin width, fin height, and gate length of the studied structure were fixed at 6.5, 26, and 20 nm, respectively. Figure 12 shows the total gate capacitance versus Vgs for different highk dielectric materials. Under all of the studied cases, Cgg starts increasing as Vgs increases until saturation, and then it becomes roughly constant, as expected [4]. The value of Cgg increases with high-k dielectric material.
The change in transconductance and cut-off frequency with different gate dielectric materials is shown in Figure 13. The analyzed bias point is: Vgs = 0.2 V and Vds = 0.05 V. As can be observed from the figure, a remarkable improvement of the device performance is achieved using higher-k material [4,21]. The value of gm for TiO2 material is higher compared to the values obtained by using the other dielectric materials, implying a higher amplification capability of the device [4,22]. The resultant behavior of fT is mainly due to the impact of the high-k dielectric material on gm rather than on Cgg, as can be noticed from Figures 12 and 13. The highest fT is obtained at Vgs = 0.2 V with Vds = 0.05 V for a FinFET model with TiO2 material, reflecting the better gate controllability over the channel fin region and hence higher transconductance.

Impact of High-k Dielectric Materials on Device Performance
To analyze the effect of the gate dielectric materials on the device performance, the fin width, fin height, and gate length of the studied structure were fixed at 6.5, 26, and 20 nm, respectively. Figure 12 shows the total gate capacitance versus V gs for different high-k dielectric materials. Under all of the studied cases, C gg starts increasing as V gs increases until saturation, and then it becomes roughly constant, as expected [4]. The value of C gg increases with high-k dielectric material.
at the lowest height of 10 nm and then decreases approximately exponentially with increasing Hfin.

Impact of High-k Dielectric Materials on Device Performance
To analyze the effect of the gate dielectric materials on the device performance, the fin width, fin height, and gate length of the studied structure were fixed at 6.5, 26, and 20 nm, respectively. Figure 12 shows the total gate capacitance versus Vgs for different highk dielectric materials. Under all of the studied cases, Cgg starts increasing as Vgs increases until saturation, and then it becomes roughly constant, as expected [4]. The value of Cgg increases with high-k dielectric material.
The change in transconductance and cut-off frequency with different gate dielectric materials is shown in Figure 13. The analyzed bias point is: Vgs = 0.2 V and Vds = 0.05 V. As can be observed from the figure, a remarkable improvement of the device performance is achieved using higher-k material [4,21]. The value of gm for TiO2 material is higher compared to the values obtained by using the other dielectric materials, implying a higher amplification capability of the device [4,22]. The resultant behavior of fT is mainly due to the impact of the high-k dielectric material on gm rather than on Cgg, as can be noticed from Figures 12 and 13. The highest fT is obtained at Vgs = 0.2 V with Vds = 0.05 V for a FinFET model with TiO2 material, reflecting the better gate controllability over the channel fin region and hence higher transconductance.  The change in transconductance and cut-off frequency with different gate dielectric materials is shown in Figure 13. The analyzed bias point is: V gs = 0.2 V and V ds = 0.05 V. As can be observed from the figure, a remarkable improvement of the device performance is achieved using higher-k material [4,21]. The value of g m for TiO 2 material is higher compared to the values obtained by using the other dielectric materials, implying a higher amplification capability of the device [4,22]. The resultant behavior of f T is mainly due to the impact of the high-k dielectric material on g m rather than on C gg , as can be noticed from Figures 12 and 13. The highest f T is obtained at V gs = 0.2 V with V ds = 0.05 V for a FinFET model with TiO 2 material, reflecting the better gate controllability over the channel fin region and hence higher transconductance. In short channel devices, the leakage current can be problematic for switching speed in the circuit by leading to an increase in the Ion/Ioff ratio. The use of a multigate design structure together with high-k dielectric materials proves good mitigation in device issues and demonstrates high switching speed in electric circuits [16][17][18][19][20][21][22]. Figure 14 shows the transfer I-V characteristics in a logarithmic scale of 14-nm SOI n-FinFET under on-state bias conditions (Vds = 0.8 V). It is observed that the off-state current decreases, especially with high-k. As expected, using high-k dielectric such as TiO2 is necessary for short channel devices to mitigate the leakage current. It is also observed that the current flow in the short channel can be improved by using high-k dielectric material. As reported in Figure  15, the highest value of Ion/Ioff occurs at the highest dielectric constant. For many electronic circuit applications, such as amplifiers and digital circuits, the best Ion/Ioff current ratio is at the highest value and therefore it implies better device performance.  In short channel devices, the leakage current can be problematic for switching speed in the circuit by leading to an increase in the I on /I off ratio. The use of a multigate design structure together with high-k dielectric materials proves good mitigation in device issues and demonstrates high switching speed in electric circuits [16][17][18][19][20][21][22]. Figure 14 shows the transfer I-V characteristics in a logarithmic scale of 14-nm SOI n-FinFET under on-state bias conditions (V ds = 0.8 V). It is observed that the off-state current decreases, especially with high-k. As expected, using high-k dielectric such as TiO 2 is necessary for short channel devices to mitigate the leakage current. It is also observed that the current flow in the short channel can be improved by using high-k dielectric material. As reported in Figure 15, the highest value of I on /I off occurs at the highest dielectric constant. For many electronic circuit applications, such as amplifiers and digital circuits, the best I on /I off current ratio is at the highest value and therefore it implies better device performance.
bias conditions (Vds = 0.8 V). It is observed that the off-state current decreases, especially with high-k. As expected, using high-k dielectric such as TiO2 is necessary for short channel devices to mitigate the leakage current. It is also observed that the current flow in the short channel can be improved by using high-k dielectric material. As reported in Figure  15, the highest value of Ion/Ioff occurs at the highest dielectric constant. For many electronic circuit applications, such as amplifiers and digital circuits, the best Ion/Ioff current ratio is at the highest value and therefore it implies better device performance.

Impact of the Gate Length on Device Performance
To analyze the effect of the gate length on the device performance, the fin width and fin height of the studied structure were fixed at 6.5 nm and 26 nm, respectively. Furthermore, the hafnium oxide was used as a gate dielectric material. There are full-node processes for FinFET technologies, such as 16, 14, 10, 7, 5, and 3 nm in R&D [1,2]. Thus, is very important to investigate the effect of the gate length on calibrated FinFET device performance. Varying device gate lengths can help in judging the numerical model's accuracy in predicting the device characteristics. The change in transconductance with different gate lengths (from 5 nm to 20 nm) is shown in Figure 16. It can be observed from the figure that a remarkable limitation is achieved by scaling down the gate length. The gm for 10 nm gate length device reaches higher values compared to other devices with different gate lengths [4,18]. The fT behavior is mainly due to the gate length effect on gm rather than on Cgg, as can be noticed from Figures 16-18. The highest fT is obtained at Vgs = 0.25 V with Vds = 0.05 V for a device with 5 nm gate length, as illustrated in Figure 18. To find the effect of the gate length on the device's I-V characteristics, the gate length was varying from 5 nm to 20 nm. Figure 19 illustrates the effects of the gate length on transfer I-V curves of the device. It is well seen from the figure that reducing the gate length leads to a decrease in the threshold voltage, but it causes an increase in the leakage current (at Vgs = 0 V). The variation of the threshold voltage, subthreshold slope, and Ion/Ioff ratio at two gate lengths with different fin widths is shown in Figures 20-22, respectively. As can be observed, Vth and SS are sensitive to Wfin for a small gate length due to the short channel effect as illustrated in Figures 20 and 21, respectively [22][23][24][25][26][27]. As shown in Figure 22, the highest value of Ion/Ioff occurs at the lowest fin width.

Impact of the Gate Length on Device Performance
To analyze the effect of the gate length on the device performance, the fin width and fin height of the studied structure were fixed at 6.5 nm and 26 nm, respectively. Furthermore, the hafnium oxide was used as a gate dielectric material. There are full-node processes for FinFET technologies, such as 16, 14, 10, 7, 5, and 3 nm in R&D [1,2]. Thus, is very important to investigate the effect of the gate length on calibrated FinFET device performance. Varying device gate lengths can help in judging the numerical model's accuracy in predicting the device characteristics. The change in transconductance with different gate lengths (from 5 nm to 20 nm) is shown in Figure 16. It can be observed from the figure that a remarkable limitation is achieved by scaling down the gate length. The g m for 10 nm gate length device reaches higher values compared to other devices with different gate lengths [4,18]. The f T behavior is mainly due to the gate length effect on g m rather than on C gg , as can be noticed from Figures 16-18. The highest f T is obtained at V gs = 0.25 V with V ds = 0.05 V for a device with 5 nm gate length, as illustrated in Figure 18. To find the effect of the gate length on the device's I-V characteristics, the gate length was varying from 5 nm to 20 nm. Figure 19 illustrates the effects of the gate length on transfer I-V curves of the device. It is well seen from the figure that reducing the gate length leads to a decrease in the threshold voltage, but it causes an increase in the leakage current (at V gs = 0 V). The variation of the threshold voltage, subthreshold slope, and I on /I off ratio at two gate lengths with different fin widths is shown in Figures 20-22, respectively. As can be observed, V th and SS are sensitive to W fin for a small gate length due to the short channel effect as illustrated in Figures 20 and 21, respectively [22][23][24][25][26][27]. As shown in Figure 22, the highest value of I on /I off occurs at the lowest fin width. = 0.05 V for a device with 5 nm gate length, as illustrated in Figure 18. To find the effect of the gate length on the device's I-V characteristics, the gate length was varying from 5 nm to 20 nm. Figure 19 illustrates the effects of the gate length on transfer I-V curves of the device. It is well seen from the figure that reducing the gate length leads to a decrease in the threshold voltage, but it causes an increase in the leakage current (at Vgs = 0 V). The variation of the threshold voltage, subthreshold slope, and Ion/Ioff ratio at two gate lengths with different fin widths is shown in Figures 20-22, respectively. As can be observed, Vth and SS are sensitive to Wfin for a small gate length due to the short channel effect as illustrated in Figures 20 and 21, respectively [22][23][24][25][26][27]. As shown in Figure 22, the highest value of Ion/Ioff occurs at the lowest fin width.

Device Optimization
Silicon material is used for the fabrication of an optimized FinFET device with a physical gate length of 15 nm. TiO2 is used as gate dielectric material to replace HfO2 for better controllability of the gate over the channel. As it is well-known, the electrostatic integrity

Device Optimization
Silicon material is used for the fabrication of an optimized FinFET device with a physical gate length of 15 nm. TiO 2 is used as gate dielectric material to replace HfO 2 for better controllability of the gate over the channel. As it is well-known, the electrostatic integrity can be improved by reducing the thickness of the gate oxide [26]. The high-k dielectric thickness is chosen to be 2 nm. Based on the previous investigation, the fin width and fin height are chosen to be equal to 4 nm and 35 nm, respectively. Fin width was scaled down in order to improve FinFET electrostatics. The source/drain spacers are fixed to 7 nm and covered by Si 3 N 4 . The contact resistivity at the S/D contact/silicon interface is fixed to 10 −9 Ω.cm 2 . The proposed device with the above characteristics shows a good improvement in electrical parameters such as I on , SS, and DIBL compared to calibrated FinFET [1]. This proves that the improvement of SCEs in the FinFET device reduces sensitivity to the leakage current. It is also interesting to note that I on /I off ratio is approximatively two times greater than the calibrated FinFET. Better device switching (on/off) can result from steeping SS and a larger I on /I off ratio. Table 3 illustrates a comparison of the optimized and calibrated device parameters with different 14-nm FinFET device technologies [28][29][30]. Finally, it should be highlighted that nowadays the interest for the FinFET technology is spreading more and more in many fields of application-such as single-molecule detection [31], pH sensing [32,33], biomedicine [34], label-free biosensing [35], 5G power amplifiers [36], energy harvesting [37], and space application [38], just to mention a few. This wide and ever-expanding range of applications makes evident the increasing need for an accurate optimization of the FinFET structure to satisfy the specific constraints and requirements.

Conclusions
In this study, the 3D 14-nm SOI n-FinFET was successfully simulated, performed, and calibrated to experimental data by using Silvaco tools. The effects of varying the fin width, fin height, gate dielectric material, and gate length on device performance were analyzed in terms of both DC and RF parameters. The results indicated that low leakage current and high I on /I off ratio can be obtained with small W fin and H fin . A cut-off frequency on the order of 1 THz was simulated and reported for the investigated FinFET model. The results indicated that this frequency is increased for smaller fin width and a subsequent reduction of gate transconductance. For the optimized device, a transconductance of 69.33 µS and a cut-off frequency of 4.22 THz were achieved at V ds = 0.05 V with V gs = 0.23 V and V gs = 0.22 V, respectively, by using the TiO 2 as the gate dielectric at 15-nm gate length. The developed study provided some useful insights outlining the great potential of the FinFET technology nodes for RF applications with high performance and low power consumption.