Precision timing is a key requirement for emerging 4D particle tracking, Positron Emission Tomography (PET), beam and fusion plasma diagnostics, and other systems. Time-to-Digital Converters (TDCs) are commonly used to provide digital estimates of th...
It is well known that continuous-time Delta-Sigma modulators are very sensitive to clock jitter effects. In literature, a number of techniques have been proposed to cope with them. In this brief, we present a detailed review and comparison of the rep...
In this paper, a programmable clock divider with a 50% duty cycle and low jitter for analog-to-digital converters (ADCs) is presented. The proposed divider, using a 180 nm CMOS process, can handle an input clock range from 40 MHz to 1 GHz. It support...
This paper presents a charge-pump phase-locked loop (PLL) frequency-synthesizer-based low-jitter wideband clock generator for multi-protocol data communications applications. Automatic frequency calibration (AFC) using linear variable time window tec...
Phase jitter is one of the crucial factors in modern digital electronics, determining the reliability of a design. This paper presents a novel approach to designing a jitter comparison system and methodology for FPGA chips using a Tapped Delay Line (...
This paper presents a fast lock-in time clock frequency multiplier without using traditional clock generation circuits such as PLLs and DLLs. We propose a novel technique based on capacitive finite impulse response (FIR) filters to generate clock pha...
A referenceless digital clock and data recovery (D-CDR) circuit using a half-rate jitter-tolerant frequency detector (FD) and a multi-bit decimator is presented. For a referenceless configuration, we introduced a half-rate jitter-tolerant digital qua...
In this paper, an accurate linear model of the Mueller–Muller phase detector (MMPD)-based clock and data recovery circuit (MM-CDR) is proposed, which analyzes several critical points of the MM-CDR including the linearization of the MMPD and the gain...
With the development of high-speed analog-to-digital converter (ADC)-based wireline receivers, the Mueller–Muller clock and data recovery (MM-CDR) circuit has garnered increasing attention. But in the design stage, evaluating the loop performan...
This paper proposes a multichannel and high-bandwidth (BW) receiver for standard packaging die-to-die (D2D) interconnects. The receiver adopts forward clock (FCK) architecture of the high-density transmission standard, which consists of 16 high-speed...
We have employed a time-domain behavioral simulator to analyze how different design options for bang-bang Clock and Data Recovery (CDR) impact the Jitter Tolerance (JTOL) performance of High-Speed Serial Interfaces (HSSIs) with PAM-4 signaling. The s...
The time synchronization protocol is indispensable in various applications of wireless sensor networks, such as scheduling, monitoring, and tracking. Numerous protocols and algorithms have been proposed in recent decades, and many of them provide mic...
Direct time-of-flight (dTOF) image sensors require accurate and robust timing references for precise depth calculation. On-chip timing references are well-known and understood, but for imaging systems where several thousands of pixels require seamles...
A compact and low-power all-digital CMOS dual-loop jitter attenuator (DJA) for low-cost built-off-test (BOT) applications such as parallel multi-DUT testing is presented. The proposed DJA adopts a new digital phase interpolator (PI)-based clock recov...
As the PCIe 6.0 specification places higher requirements on signal integrity and transmission latency, it becomes especially important to improve signal transmission performance at the physical layer of the transceiver interface. Retimer circuits are...
An all-digital multiplying delay-locked loop (MDLL)-based clock multiplier featuring a time-to-digital converter (TDC) to achieve fast power-on capability is presented. The proposed MDLL adopts a new offset-free cyclic Vernier TDC to achieve a fast l...
Clocks are widely used in multimedia and electronic devices, and they usually have different frequency demands. This paper presents the design of a multi-output clock generator using an analog integer-N phase-locked loop (PLL) and open-loop fractiona...
This paper describes an all-digital clock and data recovery (CDR) circuit for implementing edge processing with a wireless body area network (WBAN). The CDR circuit performs delay-locked loop (DLL)-based and phase-locked loop (PLL)-based operations d...
An injection-locked ring oscillator-based phase-locked-loop targeting clock recovery for space application at 3.2 GHz is presented here. Most clock recovery circuits need a very low phase noise and jitter performance and are thus based on LC-type osc...
In this paper, we propose a novel circuit and system to optimize the spacing between optical channels in gridless (also called flexible-grid or elastic) networking. The method will exploit the beginning-of-life link margin by enabling the channel to...
We propose and implement a terahertz time-of-flight ranging system based on adaptive clock asynchronous optical sampling, where the timing jitter is corrected in real time to recover the depth information in the acquired interferograms after compensa...
This paper explores effective methods for taming rubidium atomic clocks with longwave timing signals. In an in-depth analysis of the time-difference data between the 1PPS timing signal output from the ground-wave signal received by a long-wave receiv...
Space-borne gravitational wave (GW) detection is poised to significantly advance the frontiers of astrophysics, gravitation, and cosmology, which might make it possible to measure the fundamental symmetries of space-time. A critical component in GW d...
17 December 2023
A low-power and low-jitter 1.2 GHz Integer-N PLL (INPLL) is designed in a 65 nm standard CMOS process. A novel high-gain sampling phase detector (PD), which takes advantage of a transconductance (Gm) cell to boost the gain, is developed to increase t...
In this paper, a low-power Injection-Locked Clock and Data Recovery (ILCDR) using a 28 nm Ultra-Thin Body and Box-Fully Depleted Silicon On Insulator (UTBB-FDSOI) technology is presented. The back-gate auto-biasing of UTBB-FDSOI transistors enables t...
This paper presents the design of a Delay-Locked Loop (DLL) with a simple architecture and a wide input clock duty cycle range. The design is tailored to meet the increasing data rate and stringent clock requirements of modern semiconductor chips, wi...
This paper analyzes the performance requirements that need to be met by a clock generator applied to a low-temperature quantum computer and analyzes the negative effects on the clock generator circuit under low-temperature conditions. In order to mee...
This paper proposes an all-digital duty cycle corrector with synchronous fast locking, and adopts a new quantization method to effectively produce a phase of 180 degrees or half delay of the input clock. By taking two adjacent rising edges input to t...
As the primary electronic payload of laser interferometry system for space gravitational wave detection, the core function of the phasemeter is ultra-high precision phase measurement. According to the principle of laser heterodyne interferometry and...
A digital adaptive mismatch calibration (DAMC) circuit is proposed to decrease the output jitter of phase-locked loop (PLL). After amplifying the phase error with a linear time amplifier (TA), the DAMC adopts a successive approximation pulse width ca...
This article describes a dual-controller dual-delay line delay lock loop (DC-DL DLL). The proposed DLL adopted a dual delay line structure, each delay line was composed of a coarse adjustment and a fine adjustment unit, and the dual delay lines had c...
A multiplying delay-locked loop (MDLL)-based all-digital clock generator with a programmable N/M-ratio frequency multiplication capability for digital SoC is presented. The proposed digital MDLL provides programmable N/M-ratio frequency multiplicatio...
The resampling of sensor signals to compensate for deviating sampling intervals, clock jitter, or missing samples is still challenging. Real-time applications demand low latency and restriction of the input data window to past samples. Furthermore, m...
As a module of the internet of things (IOT) information security system, the true random number generator (TRNG) plays an important role in overall performance. In this paper, a low-power TRNG based on dual oscillators is proposed. Two high-frequency...
This paper presents the first fully integrated radiation-tolerant All-Digital Phase-Locked Loop (PLL) and Clock and Data Recovery (CDR) circuit for wireline communication applications. Several radiation hardening techniques are proposed to achieve st...
A variable-gain time-to-digital converter (TDC)-based multiplying delay-locked loop (MDLL) clock multiplier featuring fast-locking and programmable N/M-ratio frequency multiplication capability is presented in this paper. The proposed all-digital pro...
Wireless surface electromyography (sEMG) sensors are very practical in that they can be worn freely, but the radio link between them and the receiver might cause unpredictable latencies that hinder the accurate synchronization of time between multipl...
The construction of the next-generation water Cherenkov detector Hyper-Kamiokande (HK) has started. It will have about a ten times larger fiducial volume compared to the existing Super-Kamiokande detector, as well as increased detection performances....
Wireless sensor networks (WSNs) have been widely used to collect valuable information in Structural Health Monitoring (SHM) of bridges, using various sensors, such as temperature, vibration and strain sensors. Since multiple sensors are distributed o...
Several industrial indoor positioning systems utilize LEDs as beacons and cameras as sensors: The LED beacons transmit their identity, using various means of visible light communication (VLC) techniques. To avoid flickering effects, the transmission...
A 3.0 Gsymbol/s/lane receiver is proposed herein to acquire near-grounded high-speed signals for the mobile industry processor interface (MIPI) C-PHY version 1.1 specification used for CMOS image sensor interfaces. Adaptive level-dependent equalizati...
A 100 Gb/s quad-lane SerDes receiver with a phase-interpolator (PI)-based quarter-rate all-digital clock and data recovery (CDR) is presented. The proposed CDR utilizes a multi-phase multiplying delay-locked loop (MDLL) to generate the eight-phase re...
This paper presents a highly configurable 16-channel TDC ASIC designed in a commercial 180 nm technology with the following features: time-of-flight and time-over-threshold measurements, 8.6 ps LSB, 7.7 ps jitter, 5.6 ps linearity error, up to 5 MHz...
In this article, we propose an evolved system design approach to ultra-wideband (UWB) radar based on pseudo-random noise (PRN) sequences, the key features of which are its user-adaptability to meet the demands provided by desired microwave imaging ap...
This paper presents a design of a 48 GHz CMOS phase-locked loop (PLL) for 60 GHz millimeter-wave (mmWave) communication systems. For the sliding intermediate frequency (sliding-IF) transceiver applications, a fundamental frequency PLL with quadrature...
In the automotive industry, system-on-chips are crucial for managing weak radio waves from space, known as satellite signals. Integer-N phase-locked loops have played a vital role in the operation of system-on-chips in recent history. Their clock fre...
Femtosecond lasers have evolved continuously over the past three decades, enabling the transition of research from fundamental studies in atomic and molecular physics to the realm of practical applications. In femtosecond laser amplifiers, to ensure...
This paper presents a fully integrated physical layer (PHY) transmitter (TX) suiting for multiple industrial protocols and compatible with different protocol versions. Targeting a wide operating range, the LC-based phase-locked loop (PLL) with a dual...
The Precision Time Protocol (PTP) plays a pivotal role in achieving precise frequency and time synchronization in computer networks. However, network delays and jitter in real systems introduce uncertainties that can compromise synchronization accura...
Theperformanceoftheglobalnavigationsatellitesystem(GNSS)canbeenhancedsignificantly by introducing the inter-satellite links (ISL) of a navigation constellation. In particular, the improvement of the position, velocity, and time accuracy, and the reali...
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