An Ultra Low Power Integer-N PLL with a High-Gain Sampling Phase Detector for IOT Applications in 65 nm CMOS
Abstract
:1. Introduction
2. Exploring a 1.2 GHz INPLL Design with High-Gain LSPD
2.1. Constraints of Traditional PFD-CP PLL
2.2. Noise Contributions in Conventional PFD-CP PLL
3. Design of the Proposed PLL Utilizing LSPD
3.1. Proposed High-Gain LSPD
3.2. Proposed Sampling Integer-N PLL
3.3. Lock Detector (LD) Block
3.4. Low-Power Class-C CMOS LC VCO
4. INPLL Simulation Results
5. Conclusions
Author Contributions
Funding
Data Availability Statement
Conflicts of Interest
References
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Corner & Temp. | Supply (V) | Power Consumption | Output Swing (mV) | Phase Noise @ 1 MHz (dBc/Hz) | Phase Noise @ 3 MHz (dBc/Hz) | FOM @ 3 MHz (dB) | (MHz/V) |
---|---|---|---|---|---|---|---|
TT, 27 | 1 | 150.1 | 380 | −119.6 | −129.5 | 189.7 | 153 |
1.05 | 152.4 | 383 | −120.4 | −129.6 | 189.8 | 155.1 | |
0.95 | 147.5 | 375 | −117.1 | −125 | 185.3 | 144 | |
FF, 85 | 1 | 150.5 | 300 | −117.5 | −127.4 | 187.6 | 129 |
1.05 | 152.9 | 303 | −118.2 | −127.6 | 187.7 | 131 | |
0.95 | 148.1 | 296.5 | −114.8 | −123 | 183.3 | 122.5 | |
FF, −40 | 1 | 150.1 | 343 | −122 | −131.8 | 192 | 150 |
1.05 | 152.5 | 346.5 | −122.7 | −131.9 | 192 | 152 | |
0.95 | 147.4 | 339 | −119.7 | −127 | 187.3 | 142 | |
SS, 85 | 1 | 151 | 348 | −119.1 | −128.8 | 189 | 155 |
1.05 | 153.4 | 351.5 | −117.3 | −127.3 | 187.5 | 157 | |
0.95 | 148.6 | 344 | −115.4 | −126.9 | 187.5 | 146.5 | |
SS, −40 | 1 | 151.5 | 412 | −123 | −131.8 | 192 | 181 |
1.05 | 154 | 416 | −121 | −130.2 | 190.4 | 183.5 | |
0.95 | 149 | 407.5 | −119.2 | −129.7 | 190 | 171 |
This Work | [11] | [12] | [13] | [14] | [3] | |
---|---|---|---|---|---|---|
PLL topology (INPLLs) | Analog | Sub-sampling | Analog | Type-I Analog | Sub-sampling | Sub-sampling |
Phase detection method | LSPD | SSPD | Conv. PFD-CP | XOR-PD & MSSF-LF | SSPD | SSPD |
Technology | 65 nm | 65 nm | 130 nm | 45 nm | 65 nm | 65 nm |
Supply voltage (V) | 1 | 0.935 | 1.2 | 1 | 1.2 | 1 |
Ref. Frequency (MHz) | 1 | 49.15 | 8.66 | 22.6 | 192 | 100 |
Output frequency (GHz) | 1.18–1.43 | 2.4 | 1.8 | 2.4 | 2.3 | 2.4 |
Power dissipation | 350 | 5860 | 740 | 4000 | 4600 | 900 |
IPN (dBc) (10 kHz to 10 MHz) | −37 | −44 | −18 | −39.6 | −42 | −55 |
Rms Jitter (ps) | 2.9 | 0.63 | 15.97 | 0.97 | 0.72 | 0.161 |
Reference spur (dBc) | −62 | −55.2 | −52 | −65 | −37 | −67 |
Channel Selection | Y | N | N | N | N | N |
[31] | −236.25 | −236.3 | −217.24 | −234.1 | −236 | −256 |
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Tavakoli, J.; Lavasani, H.M.; Sheikhaei, S. An Ultra Low Power Integer-N PLL with a High-Gain Sampling Phase Detector for IOT Applications in 65 nm CMOS. J. Low Power Electron. Appl. 2023, 13, 65. https://doi.org/10.3390/jlpea13040065
Tavakoli J, Lavasani HM, Sheikhaei S. An Ultra Low Power Integer-N PLL with a High-Gain Sampling Phase Detector for IOT Applications in 65 nm CMOS. Journal of Low Power Electronics and Applications. 2023; 13(4):65. https://doi.org/10.3390/jlpea13040065
Chicago/Turabian StyleTavakoli, Javad, Hossein Miri Lavasani, and Samad Sheikhaei. 2023. "An Ultra Low Power Integer-N PLL with a High-Gain Sampling Phase Detector for IOT Applications in 65 nm CMOS" Journal of Low Power Electronics and Applications 13, no. 4: 65. https://doi.org/10.3390/jlpea13040065