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Review and Comparison of Clock Jitter Noise Reduction Techniques for Lowpass Continuous-Time Delta-Sigma Modulators

by Hairong Chang 1,2,† and Hua Tang 2,*
1
Qualcomm Inc., San Diego, CA 92121, USA
2
Department of Electrical Engineering, University of Minnesota Duluth, Duluth, MN 55812, USA
*
Author to whom correspondence should be addressed.
was with Department of Electrical Engineering, University of Minnesota Duluth.
J. Low Power Electron. Appl. 2017, 7(3), 22; https://doi.org/10.3390/jlpea7030022
Received: 10 July 2017 / Revised: 14 August 2017 / Accepted: 23 August 2017 / Published: 6 September 2017
It is well known that continuous-time Delta-Sigma modulators are very sensitive to clock jitter effects. In literature, a number of techniques have been proposed to cope with them. In this brief, we present a detailed review and comparison of the reported techniques. While the effectiveness to reduce clock jitter effects may be of most importance in this comparison, we also consider other performance metrics such as circuit complexity and overhead to implement the technique, power consumption overhead of technique, synthesis complexity incurred in system-level design, extensibility of the technique from single-bit to multi-bit operation, and robustness to process variation. When clock jitter is relatively large, the fixed-width pulse feedback technique is most effective to reduce clock jitter effects among all techniques at high sampling frequency, while switched-capacitor-resistor and switched-shaped current techniques have best performance at medium frequency or below. View Full-Text
Keywords: Delta-Sigma modulators; continuous-time; lowpass; clock jitter; clock jitter noise reduction Delta-Sigma modulators; continuous-time; lowpass; clock jitter; clock jitter noise reduction
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Chang, H.; Tang, H. Review and Comparison of Clock Jitter Noise Reduction Techniques for Lowpass Continuous-Time Delta-Sigma Modulators. J. Low Power Electron. Appl. 2017, 7, 22.

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