A 6-Locking Cycles All-Digital Duty Cycle Corrector with Synchronous Input Clock
Abstract
:1. Introduction
2. State-of-the-Art
3. Circuit Architecture Design
4. Circuit Architecture
4.1. Half-Delay Line
4.2. Fine Detector and Fine Delay Line
5. Experimental Results
6. Conclusions
Funding
Acknowledgments
Conflicts of Interest
References
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[16] | [17] | [18] | [19] | [20] | [21] | [22] | This Work | |
---|---|---|---|---|---|---|---|---|
Process (μm) | 0.065 | 0.090 | 0.13 | 0.18 | 0.18 | 0.055 | 0.055 | 0.18 |
Supply voltage (V) | 1 | 1 | 1.2 | 1.8 | 1.8 | 1 | 1 | 1.8 |
Correction Range (%) | 14–86 | 9–86 | 10–90 | 30–70 | 20–80 | 20–80 | 38–54 | 20–80 |
Frequency Range (GHz) | 0.262–1.02 | 0.075–0.734 | 0.350–1 | 0.250–0.625 | 0.440–1.5 | 0.333–1 | 1–3 | 0.5–1 |
Locking Time (cycles) | 24 | <15 | 14 | <36 | 15 | <5 | <275 | <6 |
Duty-Cycle Error (%) | 1.4 | 1.78 | <1.4 | <1.6 | ±1.8 | 2 | 0.8 | <1.9 |
Phase error (ps) | 484 | 688.4 | NA | NA | –10.6 | NA | NA | 24.8 |
Active Area (mm2) | 0.01 | 0.0289 | 0.059 | 0.09 | 0.053 | 0.016 | 0.003 | 0.0613 |
Power Consumption (mW) | 6.5 | 4.59 | 5.6 | 10.8 | 43 | 2.09 | 2.08 | 10.1 |
FOM | 0.431 | 0.594 | 0.57 | 11.52 | 1.11 | 0.09 | 0.27 | 0.382 |
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Kao, S.-K. A 6-Locking Cycles All-Digital Duty Cycle Corrector with Synchronous Input Clock. Electronics 2021, 10, 860. https://doi.org/10.3390/electronics10070860
Kao S-K. A 6-Locking Cycles All-Digital Duty Cycle Corrector with Synchronous Input Clock. Electronics. 2021; 10(7):860. https://doi.org/10.3390/electronics10070860
Chicago/Turabian StyleKao, Shao-Ku. 2021. "A 6-Locking Cycles All-Digital Duty Cycle Corrector with Synchronous Input Clock" Electronics 10, no. 7: 860. https://doi.org/10.3390/electronics10070860
APA StyleKao, S.-K. (2021). A 6-Locking Cycles All-Digital Duty Cycle Corrector with Synchronous Input Clock. Electronics, 10(7), 860. https://doi.org/10.3390/electronics10070860