Phase Compensation Sensor for Ranging Consistency in Inter-Satellite Links of Navigation Constellation

The performance of the global navigation satellite system (GNSS) can be enhanced significantly by introducing the inter-satellite links (ISL) of a navigation constellation. In particular, the improvement of the position, velocity, and time accuracy, and the realization of autonomous functions require the ISL distance measurement data as the original input. For building a high-performance ISL, the ranging consistency between navigation satellites becomes a crucial problem to be addressed. Considering the frequency aging drift and the relativistic effect of the navigation satellite, the frequency and phase adjustment (FPA) instructions for the 10.23 MHz must be injected from the ground station to ensure the time synchronization of the navigation constellation. Moreover, the uncertainty of the initial phase each time the onboard clock equipment boots also results in a pseudo-range offset. In this Ref., we focus on the influence of the frequency and phase characteristics of the onboard clock equipment on the ranging consistency of the ISL and propose a phase compensation sensor design method for the phase offset. The simulation and experimental results show that the proposed method not only realized a phase compensation for the pseudo-range jitter, but, when the 1 PPS (1 pulse per second) falls in the 10.23 MHz skip area, also overcomes the problem of compensating the ambiguous phase by directly tracking the 10.23 MHz to ensure consistency in the ranging.


Introduction
Position, velocity, and time (PVT) accuracy, integrity, continuity, and availability are the four major performance indicators for satellite navigation systems [1]; innovations and upgrades in navigation systems are constantly being undertaken to technically enhance these properties. The accuracy of the global navigation satellite system (GNSS) has currently been improved from several tens of meters to a meter-level. Typical technical measures adopted include the differential global positioning system (DGPS), represented by a wide area augmentation system (WAAS), for reducing or eliminating GPS measurement errors using the high correlation of the GPS error sources in time and space, thereby improving the user's positioning accuracy to a meter or even a sub-meter level [2,3]; the integration of pseudolites with the GNSS improves the positioning geometric factors and coverage rate, enhancing the navigation and positioning accuracy [4,5]; usage of a three carrier ambiguity resolution (TCAR) technology and a binary offset carrier (BOC) signal system to improve the accuracy of the positioning solution [6][7][8][9], etc. Among the various techniques used to improve the GNSS performance, the inter-satellite link

Ranging Principle and Analyses of the Questions
The dual-one-way measurement of an ISL consists of two satellites alternately performing a pseudo-code phase ranging process and the mutual transfer of the measurement results. It contains two one-way pseudo-range measurements.
As shown in Figure 1, where T B is the measurement pseudo-range, ∆t is the system clock difference between satellite A and satellite B, t A is the transmitting circuit delay of satellite A, r B is the receiving circuit delay of satellite B, τ(t 1 , t 2 ) is the spatial delay, t 1 is the transmitting point time of satellite A, and t 0 and t 2 are the reception point time and the measurement point time of satellite B, respectively. Next, we describe two questions in the development of the ISL payload engineering prototype.

Question 1
As shown in Figure 2, the satellite time, t 0 , references the 1 PPS, which is the same as in Figure 1. In addition, t 0 is obtained by sampling the 1 PPS using the f c . A phase difference, ∆p, exists between t 0 and t 0 . Furthermore, t 2 is also referenced to the 1 PPS and t 2 is obtained by a count of the f c to the measurement point time after the commencement of t 0 . Likewise, a phase difference, ∆p, also exists between t 2 and t 2 . In general, the 1 PPS is obtained by a count of the 10.23 MHz and f c is obtained by the frequency multiplication of the 10 MHz onboard atomic clock. If there is no frequency or phase skew, ∆p remains fixed and can be calibrated in advance as the zero value of the equipment. However, with the FPA of the 10.23 MHz clock, a phase shift occurs between the 1 PPS and the f c . When the phase shift is not an integer multiple of f c , ∆p changes. Assuming that the 10.23 MHz is shifted forward or backward by the phase, φ A , then ∆p denotes ∆p after the phase shift. It can be expressed as: where rem (•) represents the function of the remainder. When the frequency adjustment of the 10.23 MHz occurs, ∆p denotes ∆p can be expressed as: where ∆ f represents the frequency adjustment size and t is the time after the commencement of the adjustment. According to Equations (2) and (3), the phase uncertainty between t 0 and t 0 can be up to one working clock cycle. As per Equation (1), the ranging error is increased to an f c clock cycle. If the ISL payload working clock frequency is larger, the range error is smaller. However, considering the power consumption and the timing reliability of the processing chip, it is impossible to increase the working frequency by a considerable margin.

Question 2
After the onboard time-frequency equipment is powered on, it provides the ISL payload with the fixed phase relationship of the 1 PPS and the 10.23 MHz, and the phase relationship always remains at the boot state. However, the phase relationship of the 1 PPS and the 10.23 MHz is not the same each time the onboard time-frequency equipment boots.
As shown in Figure 3, p 0 means that the system's 1 PPS falls at the 10.23 MHz preset inital phase, p 0 means that the 1 PPS falls at the 10.

Proposed Sensor Design Method
Through the analyses of questions 1 and 2, we can see that the ranging deviations are related to the phase of the 10.23 MHz. Therefore, we must establish the phase relationship between f c and the 10.23 MHz. A design of the phase detection and compensation sensor based a digital phase-locked loop (PLL) for ranging deviations is herein presented.
According to literature [22], an N order phase-locked loop can accurately track signals, whose phases change with respect time to the power of N − 1 or lower. Because the 10.23 MHz phase adjustment is equivalent to the phase step excitation, the frequency adjustment is equivalent to the frequency step excitation. Therefore, a second-order phase-locked loop can accurately track the phase changes after the FPA. The system function is [22] Here, T s is the data rate input to the loop filter, b 0 and b 1 are the loop filter parameters, ω n is the system natural frequency, and ξ is the damping coefficient. With the 10.23 MHz phase-locked loop, we can accurately locate the 10.23 MHz phase at the sampling time, t 2 . Assuming that the system's 1 PPS falls at the 10.23 MHz phase, p 0 and at a phase, p 0 , after a time-frequency equipment boot. It falls at a phase, p 1 , through the ISL payload f c 's sampling, and p 0 , p 0 , and p 1 are expressed as digital phases with bit widths of N. We then obtain: where p 1 is If the 1 PPS falls in the 10.23 MHz skip area, i.e., the region of one f c clock cycle (because the indefinite range of ∆p is an f c clock cycle) to the left of the 2π (digital phase: 2 N ) phase of the 10.23 MHz, as shown in Figure 4 and if the 10.23 MHz has a phase deviation from f c , the phase sampled at the rising edge of f c will be greater than 2 N . However, when the sum of the digital phase accumulator exceeds 2 N , it overflows and then accumulates from zero. Therefore, if the 10.23 MHz is tracked by the PLL directly, the clock phase, p 1 , of the 10.23 MHz at the sampling time, t 2 , is With the FPA of the 10.23 MHz, ∆p has a phase uncertainty of 2 N 10.23e6 f c . According to Equation (8), when p 0 + ∆p is greater than 2 N , the locked phase, p 1 , output at time t 2 will move up and down around the 2 N phase of the 10.23 MHz. As per Equation (6), p compensate will thus have a phase error of 2 N , namely, a 10.23 MHz clock period.
To avoid this error, we first divide the 10.23 MHz by n to obtain a frequency, f n , by a direct digital synthesizer (DDS), yielding Thus, the phase change of the 10.23 MHz is n times the phase change of f n , which is, Then, we preset the initial phase, φ 0 , between the 10.23 MHz and f n by the DDS, whose activation must be triggered by the 1 PPS or any other signal directly associated with the 1 PPS. According to Figure 4, to ensure that the 1 PPS does not fall in the skip area of f n , the lower boundary of φ 0 must be greater than a 10.23 MHz clock period and the upper bound must be less than 2 N minus an f c clock period. We can then After this approach, as per Equation (10), the skip area in Figure 4 becomes Then, we make f c track f n using the PLL. At the sampling time t 2 , it yields Thus, as per Equation (11), as long as n is greater than one, φ 0 will be greater than 2 N −p 0 −∆p n and a phase skip problem does not occur. Then, p compensate can be expressed as: The entire process flow of sensor is depicted in Figure 6. Through phase compensation and the conversion of p compensate to time, the revised pseudo-range ranging formula is where N represents the bit width of the numerically controlled oscillator (NCO) of the 10.23 MHz phase.

Phase Error Analysis
In this Ref., the phase error of the sensor is mainly derived from the thermal noise of the phase-locked loop and the phase jitter noise of the onboard atomic clock. The estimation formula for the thermal noise mean square error, σ t , is [22,23] where B L is the loop noise bandwidth: C/N 0 is the carrier-to-noise ratio of the input signal, T 0 is the input carrier period, and T Integral is the loop coherent integration time. The phase jitter noise, σ A , of the onboard clock is proportional to the Allan Deviation mean square error, σ A (τ) and the coherent integration time, T Integral Based on the above two partial error sources, the total phase jitter mean square error is Under normal circumstances, the onboard clock of the navigation satellite's C/N 0 is better than 120 dB·Hz (10 12 Hz) and σ A (τ) is 10 −12 . Consider B L as 20 Hz (we set the classic parameters ω n = 37.7 and ξ = 0.7) and T Integral is 1 ms. According to Equations (14), (16), and (17), σ total is approximately equal to 0.0696 ps. Set n equal to 4; as per Equation (12), the error of p compensate is 4σ total , namely, 0.278 ps, that is considerably lesser than the accuracy of the 0.5 ns pseudo-code ranging [24] and a 10.23 MHz clock cycle.

Experimental and Simulation Results
Assuming that the one-way measurement period of the ISL is 1.5 s (GPS assigns 1.5 s to each satellite in ISLs) [14]. The clock, f c , is 50 MHz and the system initial phase, p 0 , is 2 N−1 (namely, π). Assuming that the two satellites remain stationary, ∆t can be monitored in real-time; the inter-satellite pseudo-range delay is 78 ms, the pseudo-code ranging accuracy of the ISL is 0.5 ns, the coefficients ω n and ξ of the PLL's system function are 37.3 and 0.7, respectively, and the data update rate, T s , is 1 ms. Then, the response of the second-order PLL error system function under a frequency and phase step excitation is shown in the Figure 7.
Assuming that the DDS frequency division coefficient, n, is 4, the initial phase, φ 0 , is 2 N−1 + 2 N−1 n and the bit width of the phase accumulator, N, is 32. Then, the phase compensation of the ranging results in case of the FPA of the 10.23 MHz and the change in the p 0 of the 1 PPS are simulated. When the 1 PPS is in the non-skip-area, the pseudo-range measurement results with and without the phase compensation are shown in Figure 8. When the 1 PPS is in the skip area, the pseudo-range measurement results are shown in Figure 9. Table 1 lists the expansion of the abbreviations in Figures 8 and 9, and the FPA values of the 10.23 MHz and the initial phase values of the 1 PPS are listed in the headers of Figures 8 and 9.
As can be seen from Figure 7, the PLL only needs 200 ms to output the convergent locked phase after the FPA, which can guarantee the validity of the phase compensation data in a one-way measurement period (1.5 s).    From Figure 8, if there is no phase compensation, the pseudo-range values have an approximately 20 ns periodic jitter caused by the frequency adjustment as shown in Figure 8a, an approximately 12 ns fixed offset caused by the phase adjustment as shown in Figure 8b, an approximately 24.43 ns fixed offset caused by the change in the p 0 of the 1 PPS depicted in Figure 8c, and a 24.43 ns fixed offset and a 20 ns periodic jitter caused by the FPA and the changed p 0 as shown in Figure 8d. However, the ranging results with a phase compensation by tracking the 10.23 MHz directly or by tracking the f n are maintained at approximately 78 ms in Figure 8a-  Particularly, in Figure 9, when the 1 PPS is in the skip area, the measurement pseudo-range has an approximately 97.75 ns periodic jump with a phase compensation by directly tracking the 10.23 MHz. Nonetheless, after the proposed phase compensation sensor, the inter-satellite measurement results are maintained at approximately 78 ms.
To verify that the proposed phase compensation method is valid, we used an ISL engineering prototype for a field data acquisition and ranging comparison. We connected by coaxial cables the ISL ground simulation unit to the ISL engineering prototype via the intermediate frequency signal. The phase compensation sensor was realized by the field programmable gate array (FPGA) inside the prototype. The PLL setting parameters were the same as the simulation parameters. The experimental scenario is shown in Figure 10.
A single Stanford FS725 Rubidium Frequency Standard provided the ISL ground simulation unit with the 10 MHz and 1 PPS reference. The ISL engineering prototype 10 MHz reference was provided by another Stanford FS725. The latter one additionally provided the 10 MHz reference for two Agilent 81150A pulse function arbitrary generators (Agilent, Kuala Lumpur, Malaysia) The ISL prototype had a 50 MHz work clock, f c , from a single-channel 81150A . It obtained the 1 PPS and the 10.23 MHz input from a dual-channel 81150A. The frequency adjustment was realized by controlling the output frequency of the dual-channel 81150A 10.23 MHz and 1 PPS. Meanwhile, the phase adjustment was realized by simultaneously changing the cable length of the 10.23 MHz. Furthermore, the uncertainty of the initial phase, p 0 , was realized by repeatedly switching on the FS725 and measured by the Agilent DSO93004L digital storage oscilloscope.
In addition, DC power was supplied to the ISL prototype. The ranging results processing personal computer (PC) (Lenovo, Beijing, China) handled the prototype work instructions and measurement data acquisition. The Stanford SR620 time interval and frequency counter monitored the real-time clock error, ∆t , and output it to the ranging results processing PC. The initial connection state shown in Figure 10 was deemed an unexecuted the FPA state; its ranging value is shown in Figure 11a. We simultaneously extended the cable by 8 m (32.42 ns) to the 1 PPS and the 10.23 MHz of the ISL prototype and decreased the 10.23 MHz by 85 mHz. The pseudo-range measurement results with and without the phase compensation sensor are shown in Figure 11b,c, respectively.   As shown in Figure 11, the measured ranging data are in accordance with the simulation results. For question 2, we powered off and on the FS725 of the ISL prototype five times without the phase compensation sensor, as well as with the phase compensation sensor. Then, we collected the ranging data, as shown in Tables 2 and 3, respectively. The phase of the 1 PPS at the clock 10.23 MHz, p 0 , could be read by the digital storage oscilloscope DSO93004L. As per Tables 2 and 3, after phase compensation sensor, the five times of ranging results were maintained at approximately 773.385 ns, which ensured the consistency of ISL ranging.

Conclusions
This paper first analyzes the inter-satellite pseudo-range jitter caused by the FPA of the navigation reference frequency of 10.23 MHz and the uncertainty of the initial phase between the 1 PPS and the 10.23 MHz. It then proposes a real-time phase compensation sensor design method based on the integer-n frequency of the second-order phase-locked loop. Through simulation analysis and experimental verification, the designed sensor's phase detection error can reach the picosecond level, and the proposed phase compensation method not only realizes a phase compensation for the pseudo-range jitter caused by the FPA of the 10.23 MHz and the uncertainty of the initial phase between the 1 PPS and the 10.23 MHz, but also when the 1 PPS falls in the 10.23 MHz skip area, overcomes the problem of compensating the ambiguous phase by directly tracking the 10.23 MHz, guaranteeing the consistency of the ISL ranging.
In the near future, ISLs will be widely applied in all aspects of space services and will become another fundamental resource for navigation and communication satellites. To further improve the ranging consistency, accuracy, and applications of ISLs, we plan to consider incorporating ISL payload devices, space environments, and source transmitters in our analysis and design. We will also consider different constellations with different ISL ranging features rather than limiting our work to the navigation constellation.

Conflicts of Interest:
The authors declare no conflict of interest.