A 1-to-8 Programmable Clock Divider with a 50% Duty Cycle and Low Jitter for ADCs

Abstract

In this paper, a programmable clock divider with a 50% duty cycle and low jitter for analog-to-digital converters (ADCs) is presented. The proposed divider, using a 180 nm CMOS process, can handle an input clock range from 40 MHz to 1 GHz. It supports integer division ratios from 1 to 8, with programmable phase shifting corresponding to each division ratio. To address the issue of the non-50% duty cycle with odd division ratios, this design combines edge-triggered and level-triggered flip-flops to simultaneously perform logical operations during the falling edge and high-level periods of the input clock, ensuring that the output clock maintains an accurate 50% duty cycle under all integer division ratios. Moreover, a clock-edge synthesis technique is adopted: three dividing timing signals are first generated to extract the pure edges of the input clock, which suppresses the excess jitter introduced by conventional multi-stage flip-flop chains. Simulation results show that, with a 1 GHz input clock, the RMS value of the jitter is less than 85.12 fs under the worst process corner, and the power consumption is less than 3.037 mW.

1. Introduction

In modern mixed-signal systems, high-speed and high-precision ADCs are one of the core modules that determine the performance of the system. The clock divider, as a key circuit of the ADC clock management unit, needs to have flexible frequency division and phase-shift functions to convert a high-frequency input clock into a lower sampling clock suitable for ADC operation. If the signal output by the divider has excessive jitter or duty-cycle distortion, it will directly deteriorate the dynamic performance of the ADC, such as the signal-to-noise ratio (SNR).

In ADCs, clock dividers are commonly implemented using Current-Mode Logic (CML), True Single-Phase Clock (TSPC) logic, and CMOS logic. Among these, CML dividers can handle high-frequency clock signals up to tens of GHz, but their power consumption is relatively high [1,2,3]. The working frequency and power consumption of TSPC logic dividers [4,5,6] lie between those of CML and CMOS logic dividers. In contrast, at lower frequencies, CMOS logic dividers [7,8,9] are the best choice in terms of power. Regarding jitter performance, CML frequency dividers exhibit the lowest jitter due to their differential operation and immunity to common-mode noise; for instance, a 40 GHz CML divider achieves an RMS jitter of only 0.8 ps [10]. TSPC dividers offer moderate jitter performance [11,12]. In contrast, CMOS logic dividers suffer from higher jitter accumulation due to larger gate delays in multi-stage flip-flop chains [13].

The most efficient way to implement a clock divider in a given CMOS technology is often to synthesize it from Verilog HDL using standard cells [14,15,16]. However, this standard cell-based design approach exhibits several limitations compared to a full-custom design. Firstly, it supports only a limited input clock frequency. Secondly, its division logic, often based on synchronous counters, fails to generate a precise 50% duty-cycle output when odd division ratios are required. Moreover, significant additional jitter is introduced due to signal propagation through multi-stage flip-flop chains. Finally, it generally occupies a large circuit area. Therefore, designing a high-performance clock divider with low jitter, an accurate 50% duty cycle, and flexible frequency/phase control is essential for improving the overall performance of ADC systems.

This paper is organized as follows: Section 2 investigates and analyzes the key techniques for achieving a 50% duty cycle for odd division ratios and reducing output clock jitter. Section 3 introduces the specific circuits, mainly including the core division logic based on a counter and phase shifter, the dual flip-flop combination technique, and the clock-edge synthesis technique. Section 4 presents the circuit simulation results obtained under all process corners. Finally, Section 5 concludes the work presented in this paper.

2. Analysis of the Proposed Techniques

2.1. A 50% Duty Cycle for Odd Division Ratios

The sampling of an ADC usually occurs at the rising or falling edge of the clock signal. When the duty cycle of the clock signal deviates from 50%, the sampling points will shift, and additional harmonic distortion will be introduced, significantly degrading the Spurious-Free Dynamic Range (SFDR) of the SNR [17,18,19]. This effect is particularly severe when using Nyquist sampling or high-frequency under-sampling.

Ref. [20] proposed a configurable integer-N clock divider architecture with synchronous reset; the duty cycle of the output is 50% when using even division ratios and approaches 50% when using odd division ratios. Ref. [5] proposed a synchronously started divide-by-five clock divider; the output duty cycle is 40%. Ref. [21] designed a multi-frequency generator; they achieved an output of 50% through an additional duty-cycle correction circuit. Ref. [22] proposed a method of adjusting an equal number of rising edges and falling edges to achieve a 50% duty cycle, even in odd division ratios. While addressing the duty-cycle issue, the power consumption caused by the additional circuit also increases. Achieving a 50% duty cycle in odd division (e.g., division by 7) requires the output to toggle after half-integer input clock cycles (e.g., 3.5 cycles). However, conventional flip-flops can only toggle at integer multiples of the input clock period. To overcome this limitation, the proposed design combines both edge-triggered and level-triggered flip-flops. Specifically, it generates triggering actions on the falling edge and during the high-level period of the input clock, creating a half-cycle offset between toggling events. This technique enables precise 50% duty cycle generation for any odd division ratio without additional circuitry or power consumption.

Usually, frequency dividers based on synchronous counters and logical operations can easily achieve a 50% duty cycle when dividing by even ratios, but the duty cycle for odd division ratios can only approach 50%. At this time, the high level of the output will be one input clock cycle longer than the low level. Suppose that, if we can divide the extra clock cycle of the high level by half for the low level, then odd division ratios can also achieve a 50% duty cycle. As shown in Figure 1, both I1 and I2 employ complementary clock inputs (CK/CKN for I1; G/GN for I2), modified from conventional single-clock flip-flops. I1 operates as an edge-triggered flip-flop: on the rising edge of CK (the falling edge of CKN), Q follows D; otherwise, Q retains its previous state. I2 operates as a level-triggered flip-flop: during the high level of G (the low level of GN), Q follows D; otherwise, Q holds. To realize this scheme, the master input clock clkin is externally split into two complementary signals, ck and ckn, rather than generating the inverted clock internally within each flip-flop. This external generation simplifies the flip-flop design and enhances the overall operating speed. All flip-flops presented in this work adopt this configuration. As a result, I1 is triggered at the rising edge of ckn (corresponding to the falling edge of clkin), while I2 is transparent during the high period of ck (corresponding to the high period of clkin). Consequently, the two triggering instances are spaced exactly half a clock cycle (T/2) apart, as depicted by waveforms Q1 and Q2 in Figure 1.

2.2. The Clock-Edge Synthesis Technique

The jitter of a clock signal is a key indicator for assessing its time-domain stability, referring to the random deviation of the clock edge from its ideal position in time [23,24]. In ADCs, the degree of deterioration of the SNR caused by clock jitter can be approximately estimated using the following formula [25]:

$${SNR}_{jitter}\left(\mathrm{dB}\right)\approx -20{log}_{10}\left(2\pi f_{in}{t}_j\right)$$

(1)

where $f_{in}$ is the frequency of the analog input signal in Hertz (Hz), and $t_j$ is the jitter of the clock signal in seconds (s). It can be seen that, the higher the frequency of the analog input signal, or the greater the jitter of the clock signal, the worse the SNR of the ADC [26,27,28]. Therefore, for high-speed and high-precision ADCs, a sampling clock with extremely low jitter is of crucial importance.

Figure 2a shows the structure of a conventional clock divider, in which the divider can be synthesized from Verilog. The rising edge and the falling edge of the output clkout align with the rising edge of the input clkin, and the additional jitter of the clkout rising and falling edges is the jitter generated by the entire divider chain, usually consisting of multiple flip-flops. Refs. [16,22,29,30] minimize clock jitter by reducing and optimizing the length of the transmission chain.

Figure 2b presents the divider structure proposed in this paper. It employs the clock-edge synthesis technique commonly used in time-interleaved ADCs for generating multiphase clocks [31,32]. To minimize additional jitter caused by the multi-stage flip-flop chains, the output clock is not generated directly from the divider chain. Instead, the division circuit first generates three dividing timing signals, out1, out2, and out3, which are then processed through NAND logic operations with the input clock clkin to produce the output clkout. Furthermore, out1 and out2 are used to capture clean rising/falling edges of the input clock, while out3 controls the output toggling instant to achieve a precise 50% duty cycle. As shown in the waveforms in the upper right corner of Figure 2b, the rising/falling edge of the clkout aligns with the falling/rising edge of the clkin, and the additional jitter of the clkout rising and falling edge is the jitter of the NAND logic gates. The advantage of this approach is that the additional jitter introduced by the logic gates is much smaller than that introduced by multiple flip-flops. Furthermore, we can reduce the jitter of the output clock by increasing the width-to-length ratio (W/L) of the logic gate transistors.

3. Circuit Design

3.1. Counter and Phase Shifter

The circuit of a 3-bit binary synchronous counter is shown in Figure 3. The 3-bit division ratio control signal divr <2:0> implements the frequency division function by controlling the counting states of the counter. When divr <2:0> = N (where 0 ≤ N ≤ 7), the counter will cycle through N + 1 states sequentially and achieve N + 1 division. Furthermore, cntr <2:0> transmits the counter’s state to the subsequent phase shifter, which then cooperates to generate a phase-shifted carry pulse signal.

Figure 4 shows the circuit of the phase shifter. The signal rstn serves as an asynchronous reset input (active low). The three XNOR gates (I12, I13, and I14) detect whether the 3-bit phase control signal padj <2:0> has changed. If a change is detected, the signal alterph generates a high-level pulse at the third rising edge of ckn to reselect padj <2:0>. Figure 5a,b show the waveforms for the case where divr <2:0> = 010 (division ratio = 3) and padj <2:0> = 000 (phase shift = 0) or 001 (phase shift = 1). When the division ratio is 3, the counter’s output state cntr <2:0> cycles from 000 to 010 sequentially: If padj <2:0> = 000, the three XNOR gates (I16, I17, and I18) output 0 when and only when cntr <2:0> = 000; consequently, the signal co generates a high-level pulse at the immediately following rising edge of ckn. If padj <2:0> = 001, the three XNOR gates output 0 when and only when cntr <2:0> = 001; the signal co generates a high-level pulse at the second rising edge of ckn thereafter. Therefore, the signal co is a carry pulse that encapsulates both frequency division and phase-shift information. Since the circuit operates fully synchronously, with output transitions occurring only at the clock edge, and all logic gates have propagation delays significantly shorter than the clock period, any combinational logic settles well before the next active clock edge. Therefore, the phase-shift accuracy is not compromised.

To ensure correct phase-shift timing, an additional circuit must be designed at the output stage of the phase shifter to suppress the first potential incorrect high-level pulse on the signal co. In Figure 4, when the division ratio is 5, the counter’s output state cntr <2:0> cycles from 000 to 100 sequentially. And padj <2:0> needs four rising edges of ckn before it reaches I16, I17, and I18 for comparison with cntr <2:0>. At this point, cntr <2:0> has changed to 011. If padj <2:0> is 000 (phase shift = 0), 001 (phase shift = 1), or 010 (phase shift = 2), co will output a high-level pulse at the 7th, 8th, and 9th rising edges of ckn. However, if padj <2:0> is 011 (phase shift = 3), co will output a high-level pulse at the 5th rising edge of ck, which does not match the expected phase-shift timing. The modified circuit and waveforms are shown in Figure 6a,b. Here, I3 generates an inverted pulse of the signal alterph (Q3) at the 5th rising edge of ckn, thereby preventing the incorrect pulse of co from passing through I5 and I6. Thereafter, the output of I3 remains high, allowing co to pass normally. The signal co-delay is a version of co that is inverted and delayed by one clkin cycle; it masks the erroneous pulse from co at the 5th ckn rising edge and instead transmits the correct pulse occurring at the 10th ckn rising edge, thereby guaranteeing the correctness of the phase-shift timing.

3.2. Duty-Cycle Adjustment and Clock-Edge Synthesis

The carry pulse signal co-delay generated by the combination of the above counter and phase shifter has accomplished the functions of frequency division and phase shifting, but its duty cycle is close to 90%, which is not suitable for use by the ADC. The next step involves edge-triggered flip-flops with level-triggered flip-flops to first address the issue of the non-50% duty cycle during odd division ratios. Subsequently, the clean rising and falling edges of the input clock signal will be extracted to output a low-jitter clock signal.

First, using the signal co-delay, two signals, reg1 and reg2, with duty cycles close to 50% are generated based on the principle of a shift register [33,34,35]. Figure 7 shows the circuit of the multi-channel selective shift register, where the co-delay serves as the control terminals for the data selectors. The signal co-delay is generated by the phase shifter modified circuit and is updated at the falling edge of ck/clkin. When co-delay is low, the com-binational logic operation results of the division ratio control signal divr <2:0> are loaded into the shift register on the next clock edge; when co-delay is high, the register shifts the previously loaded data. The co-delay’s low pulse arrives at the select terminal of the multiplexer before the next falling edge of ck/clkin, thanks to the clk-to-q delay of the phase shifter flip-flops. This provides a stable select signal for the multi-channel shift register, ensuring proper data loading and shifting without timing violations. Figure 8a,b display the waveforms of the circuit for division ratios of 5 and 8. It can be seen that, within one cycle of reg1, if the division ratio is odd, the high level has one more clkin period than the low level, and the duty cycle is approximately 50%; if the division ratio is even, the duration of the high and low levels is equal, and the duty cycle is 50%. Furthermore, reg2 is the signal obtained by delaying reg1 by one clkin cycle and inverting it, which is used for subsequent circuits.

The signals generated in all the above circuits are based on the edge-triggered flip-flops. Next, level-triggers will be applied. The purpose is to make the signals differ by half-integer multiples of the clkin clock cycle so that, when using an odd division ratio, the extra high level of the signal reg1 can be evenly divided, thereby achieving a 50% duty cycle. The circuit is shown in Figure 9: I5, I6, and I7 are level-triggered flip-flops, reg1 and reg2 are based on edge-triggered flip-flops, and the signal divr <0> indicates whether the division ratio is odd or even (0 for odd division and 1 for even division). After logical operations, three dividing timing signals, out1, out2, and out3, are generated for use in extracting the pure edge of the input clock signal in the subsequent stage. Figure 10 shows the timing relationship of the input and output signals when the frequency is divided by 5 and 8. It can be observed that the timing of out2 and out3 differs from that of out1 by half-integer multiples of the clkin clock cycle.

The clock-edge synthesis circuit is shown in Figure 11: out1, out2, and out3 act as three ordered gates controlling the transmission of the input clock clkin. The additional jitter of the output clock clkout is caused only by logic gates I1 to I6, so we can increase their size as much as possible to reduce the jitter. Figure 12a,b show the waveforms of out1, out2, and out3, extracting the rising and falling edges of the input clock clkin and generating the output clock clkout when the division ratios are 5 and 8, and the delays introduced by out1, out2, and out3 during the generation process relative to the input clock signal are considered. It can be seen that, if the additional jitter introduced by logic gates I1 to I6 is ignored, then, for odd division ratios, the rising edge and falling edge of the output clock clkout are respectively the falling edge and rising edge of the input clock clkin; for even division ratios, the rising edge and falling edge of the output clock clkout are both the falling edge of the input clock clkin.

4. Simulation Results

4.1. Frequency Division

The simulation results were obtained using circuit simulations performed in Cadence Virtuoso, with subsequent data processing and visualization conducted in MATLAB R2018b. Figure 13, Figure 14 and Figure 15 present the simulation waveforms of the frequency division. In each case, the output clock frequency is 125 MHz. Specifically, Figure 13 shows the result with an input clock of 1000 MHz divided by 8; Figure 14 corresponds to an input of 600 MHz divided by 5; and Figure 15 demonstrates the case with a 125 MHz input and no division (or a division ratio of 1). As can be seen in these three figures, the proposed divider correctly performs the frequency division function for input frequencies up to 1000 MHz, and the output signal achieves a 50% duty cycle, even for odd division ratios.

4.2. Phase Shifting

Figure 16 shows the phase-shift capability of the proposed divider for a 625 MHz input clock with a division ratio of 5. Five output waveforms are shown for phase-shift settings of 0 through 4, where each step corresponds to a delay of one input clock period. The progressive and uniform delay between successive waveforms confirms that the phase-shift function is operating normally.

4.3. Performance

Figure 17, Figure 18 and Figure 19 show the relationship between the input clock frequency and the power consumption and the RMS jitter of the rising edge and falling edge of the output clock. Under a 1.8 V supply voltage, the performance was evaluated across five process corners: Typical (TT), Slow (SS), Fast (FF), Slow-NMOS-Fast-PMOS (SNFP), and Fast-NMOS-Slow-PMOS (FNSP). The results indicate that, across all process corners and frequency sweep conditions, the maximum power consumption is 3.037 mW. Regarding output timing jitter, the maximum value for the rising edge is 83.72 fs, while that for the falling edge is 85.12 fs.

Table 1. Performance comparison.

	Ref. [29]	Ref. [36]	This Work
Process	90 nm	45 nm	180 nm
	CMOS	CMOS	CMOS
Maximum Input Frequency	4.7 GHz	60 GHz	1 GHz
Power	2.4 mW	9.6 mW	3.037 mW
RMS Jitter	1 ps	2.5 ps	85.12 fs
Area	0.0832 mm2	0.01 mm2	0.0138 mm2 *

* The area of this work is the post-layout core area.

compares the performance of the proposed divider with that of other designs. The results show that our design has significant advantages in terms of power consumption and jitter.

5. Conclusions

This paper presents the design of a programmable frequency divider with an integer division ratio from 1 to 8, fabricated using a 180 nm CMOS process for high-speed ADC applications. An approach combining edge-triggered and level-triggered flip-flops is proposed to address the non-50% duty-cycle issue in odd division ratios, while a clock-edge synthesis technique is introduced to reduce signal jitter. Simulation results show that, under a 1.8 V supply voltage across various process corners, the maximum power consumption is 3.037 mW, and the RMS jitter of the output clock is at most 83.72 fs for the rising edge and 85.12 fs for the falling edge. The design demonstrates significant advantages in both power consumption and jitter performance. The design is optimized for ADC systems with a 125 MHz system clock, accepting input frequencies up to 1 GHz. Within this target frequency range, it demonstrates significant advantages in both power consumption and jitter performance for medium-speed data converter applications. Future work may explore higher-frequency operation through advanced process nodes or alternative topologies for ultra-high-speed applications.