In this study, a gate-stack engineering technique is proposed as a means of improving the performance of a 28 nm low-power (LP) high-k/metal-gate (HK/MG) device. In detail, it was experimentally verified that HfSiO thin films can replace HfSiON conge...
Semiconductor device dimensions have been decreasing steadily over the past several decades, generating the need to overcome fundamental limitations of both the materials they are made of and the fabrication techniques used to build them. Modern meta...
In order to detect biomolecules, a biosensor based on a dielectric-modulated stacked source trench gate tunnel field effect transistor (DM-SSTGTFET) is proposed. The stacked source structure can simultaneously make the on-state current higher and the...
L-shaped tunnel field-effect transistor (TFET) provides higher on-current than a conventional TFET through band-to-band tunneling in the vertical direction of the channel. However, L-shaped TFET is disadvantageous for low-power applications because o...
Besides the intensity and wavelength, the ability to analyze the optical polarization of detected light can provide a new degree of freedom for numerous applications, such as object recognition, biomedical applications, environmental monitoring, and...
The performance of an active-quenching single-photon avalanche diode (SPAD) array that is based on the tri-state gates of a field programmable gate array (FPGA) is presented. The array is implemented by stacking a bare 4 × 4 N-on-P SPAD array o...
Since its invention in the 1960s, one of the most significant evolutions of metal-oxide semiconductor field effect transistors (MOSFETs) would be the 3D version that makes the semiconducting channel vertically wrapped by conformal gate electrodes, al...
The channel fluorine implantation (CFI) process was integrated with the Si3N4 contact etch stop layer (SiN CESL) uniaxial-strained n-channel metal-oxide-semiconductor field-effect transistor (nMOSFET) with the hafnium oxide/silicon oxynitride (HfO2/S...
1 February 2026
Obstructive sleep apnea (OSA) is a common sleep disorder that impacts patient health and imposes a burden on families and healthcare systems. The diagnosis of OSA is usually performed through overnight polysomnography (PSG) in a hospital setting. In...
In this article, the performance of n-type junctionless (JL) double-gate (DG) MOSFET-based biosensors with and without gate stack (GS) has been studied. Here, the dielectric modulation (DM) method is applied to detect biomolecules in the cavity. The...
In this study, we designed a Ka-band two-stage differential power amplifier (PA) using a 65 nm RFCMOS process. To enhance the output power of the PA, a three-stack structure was utilized in the power stage, while the driver stage of the PA was design...
We show that transfer hysteresis for a pentacene thin film transistor (TFT) with a low-temperature solution-processed zirconia (ZrOx) gate insulator can be remarkably reduced by modifying the ZrOx surface with a thin layer of crosslinked poly(4-vinyl...
The vertical Gallium Nitride-on-Silicon (GaN-on-Si) trench metal-oxide-semiconductor field effect transistor (MOSFET) is a promising architecture for the development of efficient GaN-based power transistors on foreign substrates for power conversion...
This paper examines the performance of a Gate-Engineered Gate-All-Around Charge Plasma Nanowire Field Effect Transistor (GAA-DMG-GS-CP NW-FET) and the implementation of a common source (CS) amplifier circuit. The proposed GAA-DMG-GS-CP NW-FET incorpo...
In this paper, a dual metallic material gate heterostructure junctionless tunnel field-effect transistor (DMMG-HJLTFET) is proposed and investigated. We use the Si/SiGe heterostructure at the source/channel interface to improve the band to band tunne...
Carbon nanotube field-effect transistors (CNTFETs) are becoming a strong competitor for the next generation of high-performance, energy-efficient integrated circuits due to their near-ballistic carrier transport characteristics and excellent suppress...
A Gate Stack GAA FET using SiGe with a 2 nm gate underlap encapsulating a high-k spacer has been created, explored, and evaluated for improved performance in radio frequency applications. The chip shows significant improvements in electrical and radi...
The accurate characterization of nanolayered systems is an essential topic for today’s developments in many fields of material research. Thin high-k layers and gate stacks are technologically required for the design of current and future electronic d...
This paper develops a data-driven remaining useful life prediction model for solenoid pumps. The model extracts high-level features using stacked autoencoders from decomposed pressure signals (using complementary ensemble empirical mode decomposition...
For the formation of nano-scale Ge channels in vertical Gate-all-around field-effect transistors (vGAAFETs), the selective isotropic etching of Ge selective to Ge0.8Si0.2 was considered. In this work, a dual-selective atomic layer etching (ALE), incl...
With the development of new designs and materials for nano-scale transistors, vertical Gate-All-Around Field Effect Transistors (vGAAFETs) with germanium as channel materials have emerged as excellent choices. The driving forces for this choice are t...
Transgenic technology can transfer favorable traits regardless of reproductive isolation and is an important method in plant synthetic biology and genetic improvement. Complex metabolic pathway modification and pyramiding breeding strategies often re...
Named entity recognition (NER) is one of the fundamental tasks in building knowledge graphs. For some domain-specific corpora, the text descriptions exhibit limited standardization, and some entity structures have entity nesting. The existing entity...
The performance of strained silicon (Si) as the channel material for today’s metal-oxide-semiconductor field-effect transistors may be reaching a plateau. New channel materials with high carrier mobility are being investigated as alternatives and hav...
We investigated gated multilayer graphene with stacking order changes along the armchair direction. We consider that some layers cracked to release shear strain at the stacking domain wall. The energy cones of graphene overlap along the corresponding...
Accurate photovoltaic (PV) power forecasting degrades when models are deployed across sites or seasons, primarily due to distribution shift (amplitude bias and scale mismatch) and anomalous contamination—with pronounced amplitude–phase er...
The inner spacer module, which profoundly affects the final performance of a device, is a critical component in GAA NSFET (Gate-all-around Nanosheet Field Effect Transistor) manufacturing and necessitates systematic optimization and fundamental innov...
To improve the reliability and maintainability of the nuclear safety-class digital control system (DCS), this paper conducts a study on the fault prediction of critical components in the output circuit of the nuclear safety-class signal conditioning...
This paper introduces a new bidirectional integration approach that combines fiber sensor/free space optics (FSO) communication using an intensity and wavelength division multiplexer (IWDM) techniques-based long-distance fiber Bragg grating (FBG) sen...
Virtual currencies have been declared as one of the financial assets that are widely recognized as exchange currencies. The cryptocurrency trades caught the attention of investors as cryptocurrencies can be considered as highly profitable investments...
This work focuses on the effect of remote phonon arising from the substrate and high-κ gate dielectric on electron mobility in two-dimensional (2D) InSe field-effect transistors (FETs). The electrostatic characteristic under quantum confinement...
A new S/D trimming process was proposed to significantly reduce the parasitic RC of gate-all-around (GAA) nanosheet transistors (NS-FETs) while retaining the channel stress from epitaxy S/D stressors at most. With optimized S/D trimming, the 7-stage...
A metal-oxide-semiconductor high-electron-mobility transistor (MOS-HEMT) is proposed based on using a Al2O3/ZrO2 stacked layer on conventional AlGaN/GaN HEMT to suppress the gate leakage current, decrease flicker noise, increase high-frequency perfor...
This work performs a detailed comparison of the channel width folding effectiveness of the FinFET, vertically stacked nanosheet transistor (VNSFET), and vertically stacked nanowire transistor (VNWFET) under the constraints of the same vertical (fin)...
In this paper, the fabrication and electrical performance optimization of a four-levels vertically stacked Si0.7Ge0.3 channel nanowires gate-all-around transistor are explored in detail. First, a high crystalline quality and uniform stacked Si0.7Ge0....
In this paper, the optimizations of vertically-stacked horizontal gate-all-around (GAA) Si nanosheet (NS) transistors on bulk Si substrate are systemically investigated. The release process of NS channels was firstly optimized to achieve uniform devi...
The instability of transistor characteristics caused by charge trapping under positive bias temperature (PBT) stress in In0.7Ga0.3As metal oxide semiconductor field-effect transistors (MOSFETs) with single-layer Al2O3 and bi-layer Al2O3/HfO2 gate sta...
In this paper, a novel scheme for source/drain-first (S/D-first) full bottom dielectric isolation (BDI), i.e., Full BDI_Last, with integration of a sacrificial Si0.5Ge0.5 layer was proposed and demonstrated in a stacked Si nanosheet gate-all-around (...
To address the problem of sensor faults and measurement noise being misinterpreted as structural damage in structural health monitoring (SHM), this paper proposes a new framework for distinguishing sensor faults and structural damage based on stacked...
The progression of SiC MOSFET technology from planar to trench structures requires optimized gate oxide layers within the trench to enhance device performance. In this study, we investigated the interface characteristics of HfO2 and SiO2/HfO2 gate di...
Offline handwritten text recognition (HTR) is a long-standing research project for a wide range of applications, including assisting visually impaired users, humans and robot interactions, and the automatic entry of business documents. However, due t...
Silicon qubits based on specific SOI FinFETs and nanowire (NW) transistors have demonstrated promising quantum properties and the potential application of advanced Si CMOS devices for future quantum computing. In this paper, for the first time, the q...
We systematically investigate the combined impact of process variation effects (PVEs), metal gate work function fluctuation (WKF), and random dopant fluctuation (RDF) on the key electrical characteristics of sub-1-nm technology node gate-all-around s...
The interface passivation of the HfO2/Si0.7Ge0.3 stack is systematically investigated based on low-temperature ozone oxidation and Si-cap methods. Compared with the Al2O3/Si0.7Ge0.3 stack, the dispersive feature and interface state density (Dit) of t...
This paper presents a fully integrated high-voltage (HV) neural stimulator with on-chip HV generation. It consists of a neural stimulator front-end that delivers stimulation currents up to 2.08 mA with 5 bits resolution and a switched-capacitor DC-DC...
In this paper, we demonstrate a comprehensive study of NF3-based selective etching processes for inner spacer formation and for channel release, enabling stacked horizontal gate-all-around Si nanosheet transistor architectures. A cyclic etching proce...
Co-sputtering of SiO2 and high-κ Ta2O5 was used to make multicomponent gate dielectric stacks for In-Ga-Zn-O thin-film transistors (IGZO TFTs) under an overall low thermal budget (T = 150 °C). Characterization of the multicomponent layers a...
In this paper, the effect of atomic layer deposition-derived laminated interlayer on the interface chemistry and transport characteristics of sputtering-deposited Sm2O3/InP gate stacks have been investigated systematically. Based on X-ray photoelectr...
We demonstrated the performance of an Al2O3/SiO2 stack layer AlGaN/GaN metal–oxide semiconductor (MOS) high-electron-mobility transistor (HEMT) combined with a dual surface treatment that used tetramethylammonium hydroxide (TMAH) and hydrochloric aci...
The continuous down-scaling of complementary metal oxide semiconductor (CMOS) field effect transistors (FETs) had been suffering two fateful technical issues, one relative to the thinning of gate dielectric and the other to the aggressive shortening...
of 6