Ka-Band Three-Stack CMOS Power Amplifier with Split Layout of External Gate Capacitor for 5G Applications

Abstract

In this study, we designed a Ka-band two-stage differential power amplifier (PA) using a 65 nm RFCMOS process. To enhance the output power of the PA, a three-stack structure was utilized in the power stage, while the driver stage of the PA was designed with a common-source structure to minimize power consumption in the driver stage. The layout of an external gate capacitor for the stacked power stage was split to maximize the performance of the power transistor. With the proposed split layout of the external capacitor, gain, output power, and power-added efficiency (PAE) were improved. Additionally, a capacitive neutralization technique was applied to the power and driver stages to ensure the stability and enhance the gain of the PA. The measured P_1dB and the saturation power were 22.0 dBm and 23.3 dBm, respectively, while the peak PAE was 27.8% at 28.5 GHz.

1. Introduction

With the rapid development of mobile communications, millimeter wave (mmWave) circuits to support mobile communications have been actively studied [1,2]. Especially, 5G wireless communication using beamforming technology is accelerating the development of array RF systems. In general, RF circuits based on compound semiconductors have a superior performance compared to CMOS-based RF circuits [3,4,5]. The relatively low breakdown voltage, nonlinearity, and high substrate loss of CMOS are the main causes of performance degradation of CMOS-based RF circuits. In particular, the low breakdown voltage is one of the major obstacles to obtaining high output power at the power amplifier (PA). In addition, high substrate loss causes the efficiency of the PA to decrease. On the other hand, the CMOS process has the advantage of a high integration level compared to the compound semiconductor process. Given that the array RF systems require a high integrity level, despite the several drawbacks of CMOS technology, research on mmWave circuits based on CMOS has been actively conducted [6].

In general, one of the most challenging mmWave circuits based on CMOS technology is considered to be PA [7,8,9,10]. Although the PA should generate high output power, the low breakdown voltage characteristics of CMOS make it difficult to obtain the high output power [11,12]. Accordingly, to achieve sufficient output power of the PA, various power combining techniques have been reported [13,14]. Among the various power combining techniques, a stacking technique, which can implement a voltage combining technique without using bulky transformers, has recently been vigorously studied in the Ka-band CMOS PA [15,16,17]. One of the key design methodologies of the stacking technique is the usage of an external gate capacitor to allow RF voltages at the gates of the stacked transistors and, consequently, equalize the voltage drop applied to each transistor [15,16,17]. As a result, the effects of the external gate capacitor should be even across the transistors. However, this is not easy to achieve due to the large size of the power transistors.

In this study, to maximize the effect of the external gate capacitance of the stacked PA, we propose a layout technique of the external gate capacitor. In order to ensure that the effect of the external gate capacitor can be distributed equally to the power transistor, the external gate capacitor was divided into two. The divided external gate capacitors were placed on both sides of the power transistor. It was confirmed that the efficiency and output power of the designed PA were improved thanks to the divided external gate capacitors. The power stage was designed with a three-stacked structure for sufficient output power, while a common-source structure was adopted in the driver stage to suppress dc power consumption. Additionally, to achieve the stability of the PA, a capacitive neutralization technique was also utilized.

2. Design of External Gate and Neutralization Capacitors

In this study, we designed a Ka-band CMOS PA. In particular, among the various frequency bands of 5G mobile communication, the target of this study was 27.5 GHz to 29.5 GHz. In the target frequency band, the P_1dB and power-added efficiency (PAE) aimed to exceed 20.0 dBm and 20.0%, respectively.

Herein, we describe the design process of the Ka-band CMOS PA with a focus on the power stage. Throughout the design process, electromagnetic (EM) simulation was performed by default.

2.1. Determination of External Gate Capacitor Values

Figure 1 shows the designed schematic of the three stacked power stage. All six transistors used in the power stage have the same gate width of 480 μm, while having a gate length of 65 nm. As is well known from various previous studies, the optimum load impedance, Z_LOAD, and acceptable supply voltage become higher as the number of stacked transistors increases. Therefore, when the number of stacked transistors increases, the output power of the power stage also increases. This operation of the stacked structure is affected by gate bias and the external gate capacitors of transistors constituting the stacked structure. In particular, gate bias and external gate capacitors directly affect the voltage drop in each transistor, and consequently affect the output power. To obtain the optimized value of external gate capacitors (C_EX,2 and C_EX,3), we utilized the following equations [15,17]:

$$Z_{d,k-1}=\frac{C_{gs,k}+C_{EX,k}+C_{gd,k}\hspace{0.17em}\left(1+g_{m,k}\hspace{0.17em}{Z}_{d,k}\right)}{\left(g_{m,k}+s{C}_{gs,k}\right)\hspace{0.17em}\left(C_{gd,k}+C_{ex,k}\right)},\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}{Z}_{d,k}=k\hspace{0.17em}{R}_{OPT}$$

(1)

$$C_{EX,k}=\frac{C_{gs,k}+C_{gd,k}\hspace{0.17em}\left(1+g_{m,k}\hspace{0.17em}{R}_{OPT}\right)}{\left(k-1\right)\hspace{0.17em}{g}_{m,k}{R}_{OPT}-1},\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}k=2,\hspace{0.17em}\hspace{0.17em}3$$

(2)

where C_gs, C_gd, and g_m are the gate-source parasitic capacitance, gate-drain parasitic capacitance, and trans-conductance of the transistors, respectively. Z_d and R_OPT are the load impedance of the transistors and optimum load resistance, respectively. In this study, M_P,2 and M_P,3 are identical to each other. Accordingly, under the conditions of the appropriate gate bias (V_G,2 and V_G,3), C_gs,2 and C_gs,3 are identical, and g_m2 and g_m3 are identical. With the extracted R_OPT and g_m2 (= g_m3) of 10 Ω and 0.25 S, respectively, the ratio of C_EX,2 and C_EX,3 can be calculated as

$$\frac{C_{EX,2}}{C_{EX,3}}=\frac{2\hspace{0.17em}{g}_m\hspace{0.17em}{R}_{OPT}-1}{g_m\hspace{0.17em}{R}_{OPT}-1}\approx 2.3$$

(3)

With the result of Equation (3), the calculated and optimized values of C_EX,2 and C_EX,3 were 1.18 pF and 0.48 pF.

Figure 2 shows the simulated load-pull results with simple common-source, two-stacked, and three-stacked structures, with V_DD of 1 V, 2 V, and 3 V, respectively. The real part of the optimum load impedance related to the output power increases as the number of stacked transistors increases. This means that the required impedance transformation ratio of the output matching network is reduced as the number of stacked transistors increases. In this work, a three- stacked structure was chosen considering the target output power of the PA.

2.2. Determination of Neutralization Capacitor Values

In this study, as shown in Figure 1, a capacitive neutralization technique was utilized to ensure stability in the high gain PA [18,19,20]. In Figure 3, the equivalent half-circuit of the common-source stage of Figure 1 is shown. C_NEU is the capacitor for the capacitive neutralization technique. The value of C_NEU is directly related to the value of C_gd and can be calculated as follows [21]:

$$C_{NEU}=C_{gd}\left(1+r_g/R_S\right)$$

(4)

where r_g and R_S are the parasitic gate resistance and the equivalent resistance connected to the gate of M_P,1, respectively. The capacitive neutralization technique was used in the driver and power stages. Given that the transistors of the driver and power stages were 288 μm and 480 μm, respectively, the C_NEU of power stage should be larger than that of driver stage.

To obtain the optimum values of C_NEU for the power and driver stages, the maximum available gain (MAG) and k-factor according to the value of C_NEU for the driver and power stages are shown in Figure 4. Here, the C_NEU of the driver and power stages was defined as C_NEU,D and C_NEU,P, respectively. From the simulation results, we extracted the optimum values of C_NEU for the driver and power stages as 80 fF and 120 fF, respectively. As can be seen in Figure 4, with the extracted optimum values of C_NEU, the MAG and k-factor were simultaneously improved. Therefore, we designed the PA with the selected C_NEU,D and C_NEU,P at 80 fF and 120 fF, respectively. Under the selected C_NEU,D and C_NEU,P conditions, the driver and power stages were unconditionally stable, as shown in Figure 4. Figure 5 shows the stability circles of the driver and power stages in order to more clearly confirm that the driver and power stages are unconditionally stable with the selected C_NEU,D and C_NEU,P.

2.3. Design of Driver Stage

Figure 6 shows the schematic of the PA with the driver stage. The detail structure of the power stage of Figure 6 is shown in Figure 1. The output matching network of the power stage is completed with an output transformer and a capacitor, C_OUT.

Although the power stage is designed with the three-stack structure, the driver stage is designed with a differential common-source structure to reduce the dc power consumption with a relatively low supply voltage, resulting in the improving of the efficiency of overall PA. For the differential operation of the driver stage with a single-ended input signal, the transformer is used as a balun as well as a component of the input matching network. The transformer is also used for the inter-stage matching network, as shown in Figure 6.

3. Design of Proposed Three-Stacked Power Amplifier with Split External Gate Capacitor

The proposed three-stacked PA with the split external gate capacitor was designed. In general, an external gate capacitor is located on the one side of the power transistor, as shown in Figure 7a. However, as shown in the simplified equivalent circuit of Figure 7a, because of the parasitic components of the metal lines for the power transistor, the effect of the external gate capacitor does not appear evenly through the power transistor. Here, the parasitic inductance induced by the metal lines of the power transistor is indicated as L_g. To overcome the problem of the typical layout, we proposed a layout technique of dividing the external gate capacitor into both sides of the power transistor, as shown in Figure 7b. The proposed technique allows the effect of the external gate capacitor to appear evenly through the power transistor, compared to the typical technique, so that the performance of the power transistor can be improved.

Although the gate metal of the power transistor is the distributed type in the actual situation, the equivalent circuit of the power transistor is simplified, as shown in Figure 8 for convenience of analysis. Figure 8a shows an equivalent circuit of a gate node of the power transistor in an ideal case without L_g. In this case, the gate node voltage V_g,eff,IDEAL of the transistor may be expressed as the follows.

$$V_{g,eff,IDEAL}=\left(1-\frac{1/s{C}_{gs}}{1/s{C}_{EX}+1/s{C}_{gs}}\right)\hspace{0.17em}\hspace{0.17em}{V}_s$$

(5)

However, if L_g is considered, the V_g,eff,CON of Figure 8b is calculated as follows.

$$V_{g,eff,CON}=\left(1-\frac{1/s{C}_{gs}}{1/s{C}_{EX}+1/s{C}_{gs}+s{L}_g}\right)\hspace{0.17em}\hspace{0.17em}{V}_s$$

(6)

Comparing Equation (6) considering L_g with Equation (5) in an ideal case, it can be seen that the gate node voltage is distorted by L_g. In particular, if the power transistor is formed in a distributed type as shown in Figure 7, the gate voltages of the unit-transistors constituting the power transistor are formed differently, causing the performance degradation of the PA. In order to minimize the effect of L_g, it is necessary to minimize L_g in Equation (6) to approach Equation (5).

In the case where the proposed layout technique is applied, the equivalent circuit is shown in Figure 9. In this case, V_g,eff,PRO may be expressed as follows.

$$V_{g,eff,PRO}=\left(1-\frac{1/s{C}_{gs}}{1/s{C}_{EX}+1/s{C}_{gs}+s{L}_g/4}\right)\hspace{0.17em}\hspace{0.17em}{V}_s$$

(7)

From Equations (6) and (7), compared to the typical technique, the proposed technique reduces the effect of L_g, bringing the voltage of the gate node of the power transistor closer to the ideal case. As a result, it may be seen that the proposed layout technique successfully alleviates the influence of L_g.

Figure 10 shows the actual layout of M_P,2 and M_P,3 applying the proposed layout technique of the external gate capacitor. In particular, when applying proposed technique, although the layout complexity slightly increases compared to the typical structure, no additional chip area is required to implement the proposed technique.

We compared the load-pull characteristics between the cases of applying the typical and the proposed layout techniques. As can be seen in Figure 11, the optimum impedances for the output power and efficiency of the proposed technique are almost similar to those of the typical one. However, the maximum output power and PAE of the proposed technique is higher than those of the typical technique.

The load-pull result was converted into the power gain and efficiency characteristics according to output power, as illustrated in Figure 12a. The power gain, P_1dB, saturation power (P_sat), and peak PAE with the proposed layout technique were improved compared to those with typical one. Even if the degree of improvement was not dramatic, all major performance indicators of the PA can be improved by simply dividing the external gate capacitor into two without an additional chip area. Figure 12b shows the simulation results of the S-parameters and k-factor. It can be seen that the S-parameters in the two cases were very similar to each other while the k-factor of the proposed technique was improved compared to the typical technique.

4. Results and Discussion

To verify the feasibility of the proposed layout technique of the external gate capacitor, we designed a Ka-band PA using 65 nm RFCMOS process which provides six metal layers. Figure 13 shows a photograph of the designed CMOS PA.

Figure 14a shows measured gain and PAE according to the output power at the operating frequency of 28.5 GHz. The measured P_1dB and P_sat were 22.0 dBm and 23.3 dBm, respectively, while the measured peak PAE was 27.8%. A gain expansion of approximately 1 dB occurred in the output power range from 6.75 dBm to 17.75 dBm, as shown in Figure 14a. Comparing the simulation results of PAE, the measurement result of the maximum PAE was approximately 4.2% lower. Figure 14b shows the measured S-parameters and k-factor. As can be seen in Figure 14b, the measured PA was unconditionally stable. In Figure 15, we summarized the measured P_1dB, P_sat, gain, and PAE according to the operating frequency. The maximum performance was obtained at the frequency of 28.5 GHz. In the design process, power matching technique using load-pull simulation was performed at the center frequency of 28.5 GHz, so the performance of P_1dB and PAE was somewhat degraded as the operating frequency moved away from 28.5 GHz. In the frequency range of 27.5 GHz to 29.5 GHz, the flatness of the P_1dB, P_sat, gain, and PAE was lower than 1.2 dB, 0.8 dB, 2.8 dB, and 5.3%, respectively.

Figure 16 shows the error vector magnitude (EVM) and adjacent channel leakage ratio (ACLR) measured with 64-quadrature amplitude modulation (QAM), 100 MHz bandwidth, and 9.7 dB peak-to-average power ratio (PAPR) 5G new radio (NR) signal, respectively. In Figure 17, we summarized the measured maximum linear P_OUT and ACLR under the condition that the EVM value was −25 dB.

Table 1. Comparison with state-of-the-art of CMOS PAs.

	TMTT ’19 [22]	TCAS-II ’21 [23]	MWCL ’19 [24]	Proposed Work
Tech. (nm)	90	28	65	65
Freq. (GHz)	28.0	30.0	28.0	28.5
P1dB (dBm)	23.2	17.2	16.5	22.0
Gain (dB)	16.3	21.2	18.0	23.3
Peak PAE (%)	34.1	30.3	27.3	27.7
Modulation /Bandwidth	64-QAM /100 MHz	64-QAM /100 MHz	64-QAM /100 MHz	64-QAM /100 MHz
EVM (dBc)	−25.0	−25.0	−25.0	−25.0
POUT @EVM (dBm)	19.0	10.9	7.5	17.3
Core size (mm2)	0.401	0.82	0.456	0.36
Topology	1-stage Cascode	2-stage Cascode	2-stage Cascode	2-stage 3-stack

shows the performance of the Ka-band CMOS PAs available in the literature.

5. Conclusions

In this work, we proposed a split layout technique for the external gate capacitor of the stacked PA. In the typical and proposed structures, the effect of parasitic inductance that occurred in the gate node of the power transistor on the gate node voltage was analyzed. Through this, it was found that the proposed technique suppressed the influence of the parasitic inductance. By applying the proposed technique in the PA, the output power, gain, and PAE were simultaneously improved without the additionally required chip area. To verify the feasibility of the proposed technique, we designed a Ka-band three-stacked CMOS PA with a 65 nm RFCMOS process. The measured P_1dB and P_sat were 22.0 dBm and 23.3 dBm, respectively, while the maximum PAE was 27.8% at an operating frequency of 28.5 GHz. From the design and measurement results, it was successfully verified that the proposed technique could be easily applied to CMOS PA with a stacked structure.