Ta2O5/SiO2 Multicomponent Dielectrics for Amorphous Oxide TFTs

Co-sputtering of SiO2 and high-κ Ta2O5 was used to make multicomponent gate dielectric stacks for In-Ga-Zn-O thin-film transistors (IGZO TFTs) under an overall low thermal budget (T = 150 ◦C). Characterization of the multicomponent layers and of the TFTs working characteristics (employing them) was performed in terms of static performance, reliability, and stability to understand the role of the incorporation of the high-κ material in the gate dielectric stack. It is shown that inherent disadvantages of the high-κ material, such as poorer interface properties and poor gate insulation, can be counterbalanced by inclusion of SiO2 both mixed with Ta2O5 and as thin interfacial layers. A stack comprising a (Ta2O5)x(SiO2)100 − x film with x = 69 and a thin SiO2 film at the interface with IGZO resulted in the best performing TFTs, with field-effect mobility (μFE) ≈ 16 cm2·V−1·s−1, subthreshold slope (SS) ≈ 0.15 V/dec and on/off ratio exceeding 107. Anomalous Vth shifts were observed during positive gate bias stress (PGBS), followed by very slow recoveries (time constant exceeding 8 × 105 s), and analysis of the stress and recovery processes for the different gate dielectric stacks showed that the relevant mechanism is not dominated by the interfaces but seems to be related to the migration of charged species in the dielectric. The incorporation of additional SiO2 layers into the gate dielectric stack is shown to effectively counterbalance this anomalous shift. This multilayered gate dielectric stack approach is in line with both the large area and the flexible electronics needs, yielding reliable devices with performance suitable for successful integration on new electronic applications.


Introduction
Amorphous oxide (AO) thin films have greatly progressed in a relatively short time, having found market application in the display industry where materials such as indiumgallium-zinc oxide (IGZO) appear as an advantageous alternative to Si technologies [1,2]. Besides conventional electronics, their characteristics make them suitable for concepts such as transparent and flexible electronics [3][4][5] or even paper electronics [6][7][8][9], allowing for interesting applications in fields such as medical, security and item tracking [10,11], crucial under the scope of the Internet of Things (IoT). One of the main advantages of AO is their good properties even when fabricated at low temperatures, with temperatures below 200 • C being imposed when considering flexible substrates or even paper substrates. Lower annealing temperatures unavoidably result in poorer device performance and stability. When considering these lower annealing temperatures the IGZO properties are known to be strongly related to its processing conditions [12] and adjustment of the cation ratio in the material thus plays a major role in its optimization [13]. In addition, employing dielectrics with high dielectric permittivity, ε r , (high-κ dielectrics) can compensate for poorer performances by reducing driving voltages (e.g., as required in power-efficient applications within IoT) and improving gate voltage swing due to higher gate capacitances [14,15]. For low temperature deposition of dielectrics, physical techniques such as pulsed laser deposition (PLD) [16,17], thermal evaporation [18,19] and sputtering can be used, the latter allowing the deposition of most materials without any intentional substrate heating [20], at a large scale and with low contamination [21]. Several high-κ materials have been employed for gate dielectrics in low-temperature IGZO TFTs (or other ZnO-based TFTs) including: Al 2 O 3 [22][23][24], HfO 2 [25], Ta 2 O 5 [26,27], Y 2 O 3 [28][29][30] and ZrO 2 [31]. Nevertheless, high-κ materials present some disadvantages, aggravated by low thermal budgets, when compared to conventional dielectrics such as SiO 2 . While having a relatively low permittivity (ε r = 3.9), SiO 2 is stable, has a very high band gap (E g ) of 9 eV and has a low defect density making it a good insulator with a high breakdown voltage. Additionally, it is amorphous and has a good interface with IGZO. On the other hand, ionic bonds in high-κ dielectrics result in high defect concentrations with oxygen vacancies (V O ) being the primary source of traps. These can be a source of fixed charges or act as electron traps, scattering carriers in the channel (decreasing mobility), changing the threshold voltage (V th ) and assisting oxide breakdown and gate leakage mechanisms [32], decreasing device performance, stability and reliability. Furthermore, high-κ materials are often polycrystalline (even at low temperatures) with grain boundaries contributing both to degraded surface properties and acting as preferential paths for leakage current and impurity diffusion [33,34]. When choosing the dielectric material, band alignment should be considered as at least 1 eV of conduction/valence band offset is desirable for blocking electron/hole injection. ε r is normally inversely proportional to E g (Figure 1), and the band alignment of several dielectrics with IGZO can be found in the work of Hays et al. [35]. Electron. Mater. 2021, 2, FOR PEER REVIEW 2 ratio in the material thus plays a major role in its optimization [13]. In addition, employing dielectrics with high dielectric permittivity, εr, (high-κ dielectrics) can compensate for poorer performances by reducing driving voltages (e.g., as required in power-efficient applications within IoT) and improving gate voltage swing due to higher gate capacitances [14,15]. For low temperature deposition of dielectrics, physical techniques such as pulsed laser deposition (PLD) [16,17], thermal evaporation [18,19] and sputtering can be used, the latter allowing the deposition of most materials without any intentional substrate heating [20], at a large scale and with low contamination [21]. Several high-κ materials have been employed for gate dielectrics in low-temperature IGZO TFTs (or other ZnO-based TFTs) including: Al2O3 [22][23][24], HfO2 [25], Ta2O5 [26,27], Y2O3 [28][29][30] and ZrO2 [31]. Nevertheless, high-κ materials present some disadvantages, aggravated by low thermal budgets, when compared to conventional dielectrics such as SiO2. While having a relatively low permittivity (εr = 3.9), SiO2 is stable, has a very high band gap (Eg) of 9 eV and has a low defect density making it a good insulator with a high breakdown voltage. Additionally, it is amorphous and has a good interface with IGZO. On the other hand, ionic bonds in high-κ dielectrics result in high defect concentrations with oxygen vacancies (VO) being the primary source of traps. These can be a source of fixed charges or act as electron traps, scattering carriers in the channel (decreasing mobility), changing the threshold voltage (Vth) and assisting oxide breakdown and gate leakage mechanisms [32], decreasing device performance, stability and reliability. Furthermore, high-κ materials are often polycrystalline (even at low temperatures) with grain boundaries contributing both to degraded surface properties and acting as preferential paths for leakage current and impurity diffusion [33,34]. When choosing the dielectric material, band alignment should be considered as at least 1 eV of conduction/valence band offset is desirable for blocking electron/hole injection. εr is normally inversely proportional to Eg (Figure 1), and the band alignment of several dielectrics with IGZO can be found in the work of Hays et al. [35]. Incorporation of higher Eg materials with high-κ dielectrics effectively increases EG and can result in amorphous materials to much higher temperatures due to their increased disorder [36]. Regarding low temperature (T < 200 °C) ZnO-based TFTs with multicomponent dielectrics, sputtered Bi1.5Zn1.0Nb1.5O7 showed εr ≈ 51 but was polycrystalline at room-temperature (RT) [37] while sputtered Ba0.5Sr0.5TiO3 (εr ≈ 28) was amorphous at RT but presented significant leakage [38]. The insertion of MgO into the latter dielectric improved insulation at the expense of εr (to close to 18) and it was applied to IGZO TFTs with good performance on plastic substrates [39]. In previous studies conducted by our group, sputtered HfO2 was combined with SiO2 or AlOx effectively preventing the crystallization  [35], with the permission of AIP Publishing.
Incorporation of higher E g materials with high-κ dielectrics effectively increases E G and can result in amorphous materials to much higher temperatures due to their increased disorder [36]. Regarding low temperature (T < 200 • C) ZnO-based TFTs with multicomponent dielectrics, sputtered Bi 1.5 Zn 1.0 Nb 1.5 O 7 showed ε r ≈ 51 but was polycrystalline at room-temperature (RT) [37] while sputtered Ba 0.5 Sr 0.5 TiO 3 (ε r ≈ 28) was amorphous at RT but presented significant leakage [38]. The insertion of MgO into the latter dielectric improved insulation at the expense of ε r (to close to 18) and it was applied to IGZO TFTs with good performance on plastic substrates [39]. In previous studies conducted by our group, sputtered HfO 2 was combined with SiO 2 or AlO x effectively preventing the crystallization Electron. Mater. 2021, 2 3 of the material at RT [20,40]. Similarly, Ta 2 O 5 was combined with SiO 2 or AlO x resulting in TFTs with good insulation and good performance at T ≤ 150 • C [14,27]. Another approach to reduce leakage is the use of multilayered gate dielectric stacks in which SiO 2 layers (or other low defective materials) are employed at the dielectric/semiconductor interface. In general, these layers result in lower trap densities at the interface improving device performance and stability while imposing a higher barrier for carrier injection. Sputtered HfO x N y /HfO 2 /HfO x N y [41] and HfO 2 /SiO 2 [21,42] stacks showed improved interface quality and insulation properties when compared to the respective single layer high-κ dielectrics. Hsu et al. showed excellent flexible IGZO TFTs fabricated at RT with electron beam evaporated SiO 2 /TiO 2 /SiO 2 [43]. Solution based processes can also be used for depositing high-κ dielectrics such as HfO 2 , ZrO 2 , and Ta 2 O 5 , permitting devices with very good performance [44,45] and multilayered stacks with these processes were shown to be promising even when considering low temperatures (T < 150 • C), as shown by Carlos et al. [46], while others have shown that this approach can even improve mechanical flexibility [47]. While masking some of the high-κ dielectrics disadvantages, these approaches can significantly decrease the effective oxide ε r . Moreover, while the multicomponent and multilayer concepts in dielectrics were already demonstrated, the dielectric layer composition and the gate dielectric stack architecture need to be carefully considered to obtain the best combination of performance and reliability. This is particularly relevant when imposing low thermal budgets (T ≈ 150 • C), given that in such cases the usual benefits of high temperature annealing to improve film quality cannot be considered. These low temperatures are extremely relevant in the current scenario of flexible electronics, where aspects such as hybrid integration with temperature sensitive technologies as organics or usage of unconventional substrates as paper are considered [7,11,48]. Within this context, this work presents a study of the effect of composition in multicomponent dielectric layers composed both by sputtered Ta 2 O 5 (a high-κ dielectric with ε r = 25) and sputtered SiO 2 . Besides having a high dielectric permittivity and an amorphous structure, Ta 2 O 5 can be deposited by sputtering with a good growth rate without requiring the application of very high power [14]. A low thermal budget (T ≤ 150 • C) was considering in this work, for compatibility with flexible substrates. Multilayered stacks comprising these multicomponent layers and SiO 2 layers were also studied and IGZO TFTs employing these dielectrics were assessed in terms of performance, stability, and reliability.

Device Fabrication
IGZO TFTs were fabricated with a staggered bottom gate structure on Corning glass by using standard photolithography patterning procedures, with UV patterning on a Suss MA6 aligner (SUSS MicroTec, Garching, Germany). All layers were produced by radio frequency (RF) magnetron sputtering in an AJA ATC-1300F system (AJA International Inc., North Scituate, MA, USA) without intentional substrate heating. The gate electrodes were sputtered from a Mo target in an oxygen free atmosphere with an RF power density of 3.8 W/cm 2 resulting in a final thickness of 60 nm. The multicomponent dielectric films were produced by co-sputtering from 2 inch ceramic targets of Ta 2 O 5 and SiO 2 under an argon + oxygen atmosphere and the power applied to the Ta 2 O 5 target was varied between 50 and 150 W, while power of 150 W to the SiO 2 target was kept fixed, resulting in films with different Ta 2 O 5 :SiO 2 contents. A substrate bias of 84 V during the dielectric depositions was used as it is known to result in denser and smoother films [21]. A dielectric film of only Ta 2 O 5 was also produced for investigating the role of the SiO 2 incorporation in the high-κ dielectric stacks. The 40 nm semiconductor film was sputtered from a 2 inch multicomponent ceramic target of IGZO 2:1:2 (In 2 O 3 :Ga 2 O 3 :ZnO mol) with an RF power density of 4.9 W/cm 2 in an argon + oxygen atmosphere, resulting in an amorphous film with a 4:2:1 (In:Ga:Zn) atomic ratio [49]. The source and drain electrodes were sputtered in the same way as the gate dielectric. All layers were patterned by lift-off technique with the exception of the dielectric which was patterned by plasma etching in SF 6 atmosphere.
Resulting TFTs had a width-to-length ratio (W/L) of 320/20 (µm/µm). The devices were annealed on a hot plate at 150 • C for 1 h. A schematic of the device cross-section is shown in Figure 2a. For capacitance analysis, metal-insulator-semiconductor (MIS) devices with the same dielectric layers were produced using p-type Si wafers as substrates and Mo top contacts with areas of 1.88 × 10 −3 cm 2 . The multicomponent dielectrics were also deposited in p-type Si wafers for Rutherford backscattering spectrometry (RBS) for compositional analysis and for spectroscopic ellipsometry (SE). tance analysis, metal-insulator-semiconductor (MIS) devices with the same dielectric layers were produced using p-type Si wafers as substrates and Mo top contacts with areas of 1.88 × 10 −3 cm 2 . The multicomponent dielectrics were also deposited in p-type Si wafers for Rutherford backscattering spectrometry (RBS) for compositional analysis and for spectroscopic ellipsometry (SE).
Additionally, devices employing gate dielectrics consisting of a stack of a multicomponent layers and a SiO2 layer where also fabricated. In these stacks the multicomponent layer was produced with a power of 100 W in the Ta2O5 target and a power of 150 W in the SiO2 target, with expected thickness of 200 nm for this layer. The SiO2 layer in these stacks is employed either at the gate/dielectric interface or at the dielectric/semiconductor interface by sputtering with a power of 150 W before or after the multicomponent layer, respectively, and without breaking vacuum during the entire dielectric stack deposition, with a nominal thickness of 15 nm for the SiO2 layer. These dielectric stacks and the multicomponent single layer dielectrics are schematized in Figure 2a.

Films and Devices Characterization
The stoichiometry of the dielectrics was assessed by Rutherford backscattering spectrometry (RBS) using a 2 MeV He beam delivered by a 2.5 MV van de Graaf accelerator. Two solid state detectors placed at 140° and 165° were used to collect the backscattered particles. The RBS spectra were analyzed with IBA DataFurnace NDF software [50]. A HORIBA-Jobin Yvon spectroscopic ellipsometry system was used with an incident angle of 70° in a spectral range between 1.5 and 6.5 eV. The acquired data was analyzed with DeltaPsi 2 software (v2.6.6.212, Horiba, Bensheim, Germany) and fitted using the Additionally, devices employing gate dielectrics consisting of a stack of a multicomponent layers and a SiO 2 layer where also fabricated. In these stacks the multicomponent layer was produced with a power of 100 W in the Ta 2 O 5 target and a power of 150 W in the SiO 2 target, with expected thickness of 200 nm for this layer. The SiO 2 layer in these stacks is employed either at the gate/dielectric interface or at the dielectric/semiconductor interface by sputtering with a power of 150 W before or after the multicomponent layer, respectively, and without breaking vacuum during the entire dielectric stack deposition, with a nominal thickness of 15 nm for the SiO 2 layer. These dielectric stacks and the multicomponent single layer dielectrics are schematized in Figure 2a.

Films and Devices Characterization
The stoichiometry of the dielectrics was assessed by Rutherford backscattering spectrometry (RBS) using a 2 MeV He beam delivered by a 2.5 MV van de Graaf accelerator. Two solid state detectors placed at 140 • and 165 • were used to collect the backscattered particles. The RBS spectra were analyzed with IBA DataFurnace NDF software [50]. A HORIBA-Jobin Yvon spectroscopic ellipsometry system was used with an incident angle of 70 • in a spectral range between 1.5 and 6.5 eV. The acquired data was analyzed with DeltaPsi 2 software (v2.6.6.212, Horiba, Bensheim, Germany) and fitted using the Tauc-Lorentz dispersion formula [51]. TFTs and MISs were characterized using a Keysight

Multicomponent Dielectric Properties
RBS analysis was performed on the multicomponent films sputtered with different powers applied to the Ta 2 O 5 target. The RBS spectra are presented in Figure 2b, in which the barrier for each element is indicated by vertical arrows. It is noticeable that with the increase of the power in the Ta 2 O 5 target the Ta barrier height increases whereas the Si barrier decreases. Analysis of this data allowed assessing of the stoichiometry of the films, confirming the different Ta 2 O 5 and SiO 2 contents within the dielectrics as summarized in Table 1. RBS revealed some incorporation of Ar (values presented in Table S1) across all film compositions, as is common for films sputtered in Ar rich atmospheres [52]. Figure S1 presents the Ar content in the dielectric for different Ta 2 O 5 contents, showing clearly that the Ar incorporation is more pronounced for higher Ta 2 O 5 contents. Nevertheless, the Ar content across all compositions (4.3 ± 0.7%) does not change significantly (from 3.4% to 5.5%) and the Ta 2 O 5 and SiO 2 contents presented in Table 1 are thus normalized to 100%, for simplicity. According to the normalized Ta 2 O 5 and SiO 2 compositions the multicomponent dielectric layers are denominated as "T x S 100 − x " where x is the approximate Ta 2 O 5 percentage of the material, and 100 − x is thus the approximate SiO 2 percentage. "T" and "S" thus correspond to Ta 2 O 5 and SiO 2 , respectively, under this nomenclature. For clarity, when the dielectric is based on a single cation, the usual chemical formulas are employed, namely, Ta 2 O 5 or SiO 2 . For each of these layers its thickness was extracted from the analysis of the SE data, with values in the 200−250 nm range [53]. As for the multilayered gate dielectric stacks, their multicomponent layers have "T 69 S 31 " composition and are then denominated "SiO 2 /T 69 S 31 " and "T 69 S 31 /SiO 2 ", according to the position of the SiO 2 layer in the gate dielectric stack, as schematized in Figure 2a. Knowing the areal density extracted from RBS and the thicknesses from SE (Table S1), the atomic density for each composition can be calculated. It was shown in a previous work that at least for the range of power used here, the Ta 2 O 5 density is independent of the power density in the Ta 2 O 5 target [53] and since the SiO 2 target power density is kept for all compositions, the atomic densities for each composition can be assumed to depend linearly on the content of each material as per (1) where the approximate percentages of Ta 2 O 5 and SiO 2 are x and 100 − x, respectively. Figure 2c shows the atomic density for the different dielectric compositions. From the linear fitting of the data, the oxides' atomic densities are estimated as ρ SiO 2 = (6.40 ± 0.10) × 10 22 cm −3 and ρ Ta [55] . Regarding surface roughness, SiO 2 films are known to be smooth and even with the increase of Ta 2 O 5 content in the multicomponent material, ellipsometry and AFM showed that these films are still smooth with T 69 Si 31 layers and Ta 2 O 5 films presenting roughness below 0.5 nm and 1.1 nm, respectively [53,56]. Furthermore, XRD characterization showed that these films are amorphous up to 900 • C [56].
From the C-V characterization of the MIS structures ( Figure S2), the dielectric permittivity (ε r ) was calculated for the different multicomponent dielectrics, as presented in Figure 2d and in Table 1. As expected, by incorporating Ta 2 O 5 the dielectric constant can be greatly increased when compared to that of pure SiO 2 . Assuming that ε r depends linearly on the content of each material as per (2) where x and 100 − x are the approximate percentages of Ta 2 O 5 and SiO 2 , respectively, each oxides' permittivity can be estimated as ε r,SiO 2 = 1.29 ± 1.06 and ε r, Ta  The performance of TFTs employing the different dielectric compositions was evaluated and a transfer curve for the T 60 S 40 composition is presented in Figure 3a as an example. Figure 3b summarizes the field-effect mobilities (µ FE ) and subthreshold slopes (SS) obtained with the different T x S 100 − x dielectrics. With the addition of Ta 2 O 5 content, a slight degradation of the mobility from ≈ 16.3 to 14.8 cm 2 ·V −1 ·s −1 is observed. This can be justified by the decrease of quality of the T x S 100 − x /IGZO interface with the addition of Ta 2 O 5 , where defects such as fixed charges can cause the scattering of carriers, decreasing their mobility. The trap density at the interface (D it ) was extracted from (3) in which k, T, and e have their usual physical meanings and C is the dielectric capacitance.
As presented in Figure 3c, D it tends to increase with the addition of Ta 2 O 5 content, showing that the high-κ oxide results in poorer interface quality with IGZO when compared to SiO 2 . Nevertheless, for the studied range of Ta 2 O 5 incorporation, all the devices show good performance with mobilities above 14 cm 2 ·V −1 ·s −1 , SS lower than 0.3 V/dec, on/off ratios close to 1 × 10 7 and gate leakage currents (I G ) close to 1 pA. Regarding the devices employing the multilayered gate-stacks, for the SiO 2 /T 69 S 31 , dielectric properties close to that of the T 69 S 31 were found, which should be related to the similar T 69 S 31 /IGZO interface. For the TFTs employing a T 69 S 31 /SiO 2 layer, mobility was slightly higher than most T x S 100 − x compositions, and a great improvement is shown in SS (0.15 V/dec) and consequently D it , showcasing the significantly better quality of the SiO 2 /IGZO interface. Electron

Insulation Reliability
Arising from higher defect densities and lower band gaps, employing high-κ dielectrics can often result in high IG. In fact, TFTs employing a Ta2O5 dielectric layer revealed poor insulation which compromised the extraction of their transfer characteristics. Regarding the TxS100 − x dielectrics, while IG was below 1 pA for TFTs considered to be working properly (see Figure 3a), in some devices an abrupt increase of IG is seen with the increase of gate voltage. To quantify the dielectric reliability for each TxS100 − x composition (and for the multilayered structures), a leakage probability (PLeak) was determined as the frequency of TFTs presenting gate leakage out of 18 similar devices. In practice, IG was either in the noise level (for properly working TFTs) or higher than several nA (considered as leakage). Figure 4a presents the leakage probability for TFTs with channel widths and lengths of 320 µm and 20 µm, respectively. Whereas a good reliability is seen for Ta2O5 contents of 60% and lower, it decreases abruptly for contents of 69% and higher. This can be attributed either to an increase of the conductivity of the dielectric layer or to a decrease of the conduction band offset (∆EC) between IGZO and the dielectric layer, allowing the injection of carriers into the dielectric trough conduction mechanisms such as thermionic emission and field emission [57]. The band gaps of the TxS100 − x dielectrics, obtained from ellipsometry measurements [53] are

Insulation Reliability
Arising from higher defect densities and lower band gaps, employing high-κ dielectrics can often result in high I G . In fact, TFTs employing a Ta 2 O 5 dielectric layer revealed poor insulation which compromised the extraction of their transfer characteristics. Regarding the T x S 100 − x dielectrics, while I G was below 1 pA for TFTs considered to be working properly (see Figure 3a), in some devices an abrupt increase of I G is seen with the increase of gate voltage. To quantify the dielectric reliability for each T x S 100 − x composition (and for the multilayered structures), a leakage probability (P Leak ) was determined as the frequency of TFTs presenting gate leakage out of 18 similar devices. In practice, I G was either in the noise level (for properly working TFTs) or higher than several nA (considered as leakage). Figure 4a presents the leakage probability for TFTs with channel widths and lengths of 320 µm and 20 µm, respectively.

Insulation Reliability
Arising from higher defect densities and lower band gaps, employing high-κ dielectrics can often result in high IG. In fact, TFTs employing a Ta2O5 dielectric layer revealed poor insulation which compromised the extraction of their transfer characteristics. Regarding the TxS100 − x dielectrics, while IG was below 1 pA for TFTs considered to be working properly (see Figure 3a), in some devices an abrupt increase of IG is seen with the increase of gate voltage. To quantify the dielectric reliability for each TxS100 − x composition (and for the multilayered structures), a leakage probability (PLeak) was determined as the frequency of TFTs presenting gate leakage out of 18 similar devices. In practice, IG was either in the noise level (for properly working TFTs) or higher than several nA (considered as leakage). Figure 4a presents the leakage probability for TFTs with channel widths and lengths of 320 µm and 20 µm, respectively. Whereas a good reliability is seen for Ta2O5 contents of 60% and lower, it decreases abruptly for contents of 69% and higher. This can be attributed either to an increase of the conductivity of the dielectric layer or to a decrease of the conduction band offset (∆EC) between IGZO and the dielectric layer, allowing the injection of carriers into the dielectric trough conduction mechanisms such as thermionic emission and field emission [57]. The band gaps of the TxS100 − x dielectrics, obtained from ellipsometry measurements [53] are Whereas a good reliability is seen for Ta 2 O 5 contents of 60% and lower, it decreases abruptly for contents of 69% and higher. This can be attributed either to an increase of the conductivity of the dielectric layer or to a decrease of the conduction band offset (∆E C ) between IGZO and the dielectric layer, allowing the injection of carriers into the dielectric trough conduction mechanisms such as thermionic emission and field emission [57]. The band gaps of the T x S 100 − x dielectrics, obtained from ellipsometry measurements [53] are Electron. Mater. 2021, 2 8 shown in Figure 4b. For all compositions, the band gaps are much closer to that of Ta 2 O 5 (≥4 eV [58,59]) than that of SiO 2 (8.9 eV), a trend that has been seen before for other highκ/SiO 2 mixtures [14,20,35]. Nevertheless, the increase of band gap with the incorporation of SiO 2 is still relevant: to block charge injection, a conduction band offset above 1 eV is desirable and while the valence band offset to IGZO is unknown, the measured T x S 100 − x band gaps are very close to 1 eV above the IGZO's band gap (as represented in Figure 4b). This means that the slight band gap increase by the incorporation of SiO 2 may play a critical role in blocking the injection of charge. Leakage probabilities for the multilayered dielectrics are also presented in Figure 4a, and these are compared to the T 69 S 31 single layer. The SiO 2 layer at the gate/dielectric interface (SiO 2 /T 69 S 31 ) significantly reduces the leakage probability, demonstrating the good insulation properties of this stack. Nevertheless, with the SiO 2 layer at the dielectric/IGZO interface (T 69 S 31 /SiO 2 ), this is even further enhanced, with no leaking devices being found. Compared to the SiO 2 /T 69 S 31 layer, this improvement can be attributed to a decrease of charge injection from the IGZO to the gate dielectric stack (e.g., hot electron injection) due to either the higher ∆E C , better interface quality, or both. This shows that multilayered gate dielectric stacks are a viable approach to improve device performance without sacrificing reliability.

Stability
It is interesting to notice that the transfer curves for these devices present counterclockwise hysteresis. When employing SiO 2 dielectrics the hysteresis is known to be clockwise resulting from electron trapping in the dielectric/semiconductor interface trap-sites. Nevertheless, this counterclockwise hysteresis has been previously reported at times for some high-κ dielectrics, as will be discussed later. This device hysteresis was shown to increase with decreasing V GS step (which increases measurement time) as shown in Figure 5a for the T 60 S 40 composition. Considering V On the V GS for I DS ≈ 100 pA, the measured hysteresis (∆V On ) for different V GS steps for the different T x S 100 − x compositions is presented in Figure 5b. Counterintuitively, the hysteresis is higher (in magnitude) for higher SiO 2 content and this will be addressed later. As for the multilayered gate dielectric stacks, the hysteresis was shown to be close to that of the corresponding single layer (T 69 S 31 ), even in the case of a SiO 2 /IGZO interface.
Electron. Mater. 2021, 2, FOR PEER REVIEW 8 shown in Figure 4b. For all compositions, the band gaps are much closer to that of Ta2O5 (≥4 eV [58,59]) than that of SiO2 (8.9 eV), a trend that has been seen before for other high-κ/SiO2 mixtures [14,20,35]. Nevertheless, the increase of band gap with the incorporation of SiO2 is still relevant: to block charge injection, a conduction band offset above 1 eV is desirable and while the valence band offset to IGZO is unknown, the measured TxS100 − x band gaps are very close to 1 eV above the IGZO's band gap (as represented in Figure 4b). This means that the slight band gap increase by the incorporation of SiO2 may play a critical role in blocking the injection of charge. Leakage probabilities for the multilayered dielectrics are also presented in Figure 4a, and these are compared to the T69S31 single layer. The SiO2 layer at the gate/dielectric interface (SiO2/T69S31) significantly reduces the leakage probability, demonstrating the good insulation properties of this stack. Nevertheless, with the SiO2 layer at the dielectric/IGZO interface (T69S31/SiO2), this is even further enhanced, with no leaking devices being found. Compared to the SiO2/T69S31 layer, this improvement can be attributed to a decrease of charge injection from the IGZO to the gate dielectric stack (e.g., hot electron injection) due to either the higher ∆EC, better interface quality, or both. This shows that multilayered gate dielectric stacks are a viable approach to improve device performance without sacrificing reliability.

Stability
It is interesting to notice that the transfer curves for these devices present counterclockwise hysteresis. When employing SiO2 dielectrics the hysteresis is known to be clockwise resulting from electron trapping in the dielectric/semiconductor interface trap-sites. Nevertheless, this counterclockwise hysteresis has been previously reported at times for some high-κ dielectrics, as will be discussed later. This device hysteresis was shown to increase with decreasing VGS step (which increases measurement time) as shown in Figure 5a for the T60S40 composition. Considering VOn the VGS for IDS ≈ 100 pA, the measured hysteresis (∆VOn) for different VGS steps for the different TxS100 − x compositions is presented in Figure 5b. Counterintuitively, the hysteresis is higher (in magnitude) for higher SiO2 content and this will be addressed later. As for the multilayered gate dielectric stacks, the hysteresis was shown to be close to that of the corresponding single layer (T69S31), even in the case of a SiO2/IGZO interface. The hysteresis' direction is usually tied with the direction of the Vth shift seen during positive gate bias stress (PGBS), unless different mechanisms play a role in these [60]. TFTs with the different dielectrics where submitted to PGBS with a gate voltage of 10 V The hysteresis' direction is usually tied with the direction of the V th shift seen during positive gate bias stress (PGBS), unless different mechanisms play a role in these [60]. TFTs with the different dielectrics where submitted to PGBS with a gate voltage of 10 V for 1 h, followed by 1 h of recovery at V GS = 0 V. During both, a drain voltage of 0.1 V was applied allowing addressing of the value of V th by (4), which was fairly consistent with the V th extracted from transfer curves before and after stress and recovery.
The threshold voltage shift (∆V th ) for the different compositions is shown in Figure 6a. Similarly to the devices' hysteresis, V th also shifts towards more negative values during PGBS, as opposed to the typically reported positive V th shift associated with electron trapping at the interface. V th shifts with higher magnitude are once again observed for the SiO 2 -richer compositions, as summarized in Figure 6b. Interestingly, in the same time frame, V th shows only a partial recovery (for V GS = 0 V), unlike in the faster relaxations typical of cases dominated by electron (de)trapping, whereas applying a negative gate bias (V GS = −10 V) resulted in a fast recovery of the threshold voltage ( Figure S3a).
Electron. Mater. 2021, 2, FOR PEER REVIEW 9 for 1 h, followed by 1 h of recovery at VGS = 0 V. During both, a drain voltage of 0.1 V was applied allowing addressing of the value of Vth by (4), which was fairly consistent with the Vth extracted from transfer curves before and after stress and recovery.
The threshold voltage shift (∆Vth) for the different compositions is shown in Figure  6a. Similarly to the devices' hysteresis, Vth also shifts towards more negative values during PGBS, as opposed to the typically reported positive Vth shift associated with electron trapping at the interface. Vth shifts with higher magnitude are once again observed for the SiO2-richer compositions, as summarized in Figure 6b. Interestingly, in the same time frame, Vth shows only a partial recovery (for VGS = 0 V), unlike in the faster relaxations typical of cases dominated by electron (de)trapping, whereas applying a negative gate bias (VGS = −10 V) resulted in a fast recovery of the threshold voltage ( Figure S3a). In Figure 6b, the Vth shift for the T69S31/SiO2 layer is also shown. While its shift magnitude is significantly lower than that of the TxS100 − x/IGZO interfaces, it is still negative, suggesting that this anomalous shift is not an interface phenomena and it is in competition with the electron-trapping at the SiO2/IGZO interface during the PGBS [60].
Considering conventional applications (for which Vth shifts are undesirable), Ta2O5-richer compositions present as better alternatives both by resulting in higher dielectric permittivities and for lower Vth shifts. While these compositions can be unreliable in terms of gate leakage, it was demonstrated that thin SiO2 layers at the dielectric/semiconductor interface successfully prevent gate leakage even for thinner overall gate dielectric stacks (with effectively higher capacitances). This shows that the multicomponent and multilayered approach can be a feasible method for achieving high device performance by incorporation of high-κ dielectrics without sacrificing device reliability. In fact, while the presented Vth shift magnitudes are considerably high, further addition of SiO2 layers can be used to counterbalance this anomalous shift. This approach permits achieving devices with lower and positive Vth shift magnitude, while still maintaining desirable values for effective εr of 10-15. This is shown in Figure 7, for devices previously reported by our group [60] which employed similar multilayered gate dielectric stacks with an increased number of SiO2 layers as shown in the inset of Figure 7b, resulting in εr ≈ 13. While positive Vth shifts in transfer curves measured after discrete periods of gate bias stress suggest the charge trapping mechanism only (Figure 7a), closer inspection along the duration of the stress by monitoring the drain current (Figure 7b) allows observing In Figure 6b, the V th shift for the T 69 S 31 /SiO 2 layer is also shown. While its shift magnitude is significantly lower than that of the T x S 100 − x /IGZO interfaces, it is still negative, suggesting that this anomalous shift is not an interface phenomena and it is in competition with the electron-trapping at the SiO 2 /IGZO interface during the PGBS [60].
Considering conventional applications (for which V th shifts are undesirable), Ta 2 O 5richer compositions present as better alternatives both by resulting in higher dielectric permittivities and for lower V th shifts. While these compositions can be unreliable in terms of gate leakage, it was demonstrated that thin SiO 2 layers at the dielectric/semiconductor interface successfully prevent gate leakage even for thinner overall gate dielectric stacks (with effectively higher capacitances). This shows that the multicomponent and multilayered approach can be a feasible method for achieving high device performance by incorporation of high-κ dielectrics without sacrificing device reliability. In fact, while the presented V th shift magnitudes are considerably high, further addition of SiO 2 layers can be used to counterbalance this anomalous shift. This approach permits achieving devices with lower and positive V th shift magnitude, while still maintaining desirable values for effective ε r of 10-15. This is shown in Figure 7, for devices previously reported by our group [60] which employed similar multilayered gate dielectric stacks with an increased number of SiO 2 layers as shown in the inset of Figure 7b, resulting in ε r ≈ 13. While positive V th shifts in transfer curves measured after discrete periods of gate bias stress suggest the charge trapping mechanism only (Figure 7a), closer inspection along the duration of the stress by monitoring the drain current (Figure 7b) allows observing that the anomalous shift of V th occurs during the first few minutes of stress. This clearly shows that the two mechanisms are in competition with charge trapping dominating, eventually resulting in an overall V th shift of 1.3 V after 1 h of bias stress. Similar devices were successfully applied for a flexible radiation sensing system, both for timing signals generation for addressing the sensors in the irradiated matrix [61] and for a high-gain transimpedance amplifier for amplification and voltage transduction of the sensors current signal [10], with both implementations requiring robust device operation.
Electron. Mater. 2021, 2, FOR PEER REVIEW 10 that the anomalous shift of Vth occurs during the first few minutes of stress. This clearly shows that the two mechanisms are in competition with charge trapping dominating, eventually resulting in an overall Vth shift of 1.3 V after 1 h of bias stress. Similar devices were successfully applied for a flexible radiation sensing system, both for timing signals generation for addressing the sensors in the irradiated matrix [61] and for a high-gain transimpedance amplifier for amplification and voltage transduction of the sensors current signal [10], with both implementations requiring robust device operation.

Mechanism of the Anomalous Vth Shift
A discussion of the mechanisms involved in the observed anomalous Vth shifts is now presented. While these have been reported for TFTs employing high-κ gate dielectrics (such as Ta2O5 [62][63][64], ZrO2 [9] and HfO2 [65]), other reports often show normal shift directions. High-κ dielectrics are known to be prone to have high defect density (probably playing a role in the anomalous shift) and it should be expected that different processing methodologies can result in distinct material qualities, leading to different device behaviors. The mechanisms that are normally used to explain anomalous Vth shifts [34] are: charge (de)trapping from the gate dielectric [62,65] ionic migration within the dielectric [63] (understandable as a slow polarization of the dielectric material [64]) and defect creation [66]. Regarding defect creation, it can lead to an increase in the carrier concentration, resulting in the decrease of the Vth, and it was shown before for poor quality semiconductors [66]. In this case, this can be disregarded as no change in the transfer curves' SS was observed, demonstrating the stability of the semiconductor (even considering the low thermal budget employed here). Furthermore, it is expected that the involved mechanism is dielectric related as this anomalous shift is not observed in our IGZO TFTs when employing other dielectrics. Regarding the charge trapping mechanisms, a positive net charge change is required for a negative Vth shift. Hole trapping at the dielectric/semiconductor interface can be disregarded as the voltage polarity is opposite to what would be required, and wide band gap n-type oxides require optical excitation for holes to be generated in the first place. Then, electron detrapping from the dielectric to the gate must be considered (e.g., from negatively charged oxygen interstitials: IOor IO 2- [65]). However, detrapping at this interface cannot change the electron concentration at the semiconductor, and thus cannot explain the anomalous shift if charge migration is not assumed [34,64]. To investigate the mechanism, the time dependency of the threshold voltage shift during the gate bias stress was studied and a power-law dependence (Δ ∝ ) was found, as shown in Figure 8a for the T39S61 and T75S25 compositions. While exponential dependencies are seen when charge (de)trapping is the relevant pro-

Mechanism of the Anomalous V th Shift
A discussion of the mechanisms involved in the observed anomalous V th shifts is now presented. While these have been reported for TFTs employing high-κ gate dielectrics (such as Ta 2 O 5 [62][63][64], ZrO 2 [9] and HfO 2 [65]), other reports often show normal shift directions. High-κ dielectrics are known to be prone to have high defect density (probably playing a role in the anomalous shift) and it should be expected that different processing methodologies can result in distinct material qualities, leading to different device behaviors. The mechanisms that are normally used to explain anomalous V th shifts [34] are: charge (de)trapping from the gate dielectric [62,65] ionic migration within the dielectric [63] (understandable as a slow polarization of the dielectric material [64]) and defect creation [66]. Regarding defect creation, it can lead to an increase in the carrier concentration, resulting in the decrease of the V th , and it was shown before for poor quality semiconductors [66]. In this case, this can be disregarded as no change in the transfer curves' SS was observed, demonstrating the stability of the semiconductor (even considering the low thermal budget employed here). Furthermore, it is expected that the involved mechanism is dielectric related as this anomalous shift is not observed in our IGZO TFTs when employing other dielectrics. Regarding the charge trapping mechanisms, a positive net charge change is required for a negative V th shift. Hole trapping at the dielectric/semiconductor interface can be disregarded as the voltage polarity is opposite to what would be required, and wide band gap n-type oxides require optical excitation for holes to be generated in the first place. Then, electron detrapping from the dielectric to the gate must be considered (e.g., from negatively charged oxygen interstitials: I O or I O 2- [65]). However, detrapping at this interface cannot change the electron concentration at the semiconductor, and thus cannot explain the anomalous shift if charge migration is not assumed [34,64]. To investigate the mechanism, the time dependency of the threshold voltage shift during the gate bias stress was studied and a power-law dependence (∆V th ∝ t n ) was found, as shown in Figure 8a for the T 39 S 61 and T 75 S 25 compositions. While exponential dependencies are seen when charge (de)trapping is the relevant process, power dependencies are often related to reaction-diffusion mechanisms. For the compositions presented in Figure 8a, the exponent n changed from ≈0.5 to ≈0.6 after approximately 1 min. For the intermediate T x S 100 − x compositions, the exponent changed from ≈0.33 to ≈0.5 after approximately 1-5 min ( Figure S4a,b). Similar dependencies were noted for the multilayered stacks ( Figure S4c), further suggesting that the mechanism is not dominated by either of the interfaces. Power law time dependency of ∆V th is known for the diffusion of H species in MOSFETs during negative bias temperature stress, where exponents of 1/3 and 1/2 are associated to trapgeneration and diffusion of the charged species H + and H 2 + , respectively [67]. Aleksandrov et al. also associated n = 1 to first-order chemical-reaction kinetics and n closer to 0.5 to diffusion and drift kinetics of H + ions [68]. While further investigation is needed to understand the involved species in our devices, it is interesting to notice that Ta 2 O 5 dielectrics are known for their ionic conductivity, with H + and V O migration in its bulk being known [69] and partly responsible for their application as resistive switching layers [70]. Regarding the V th recovery (for V GS = 0 V in Figure 6a), an exponential dependency with time is apparent: while recovering quickly initially, it seems that, at least in the presented time frame, V th is slowly tending to values significantly larger than the initial ones. Charge migration is often ruled out when fast recoveries are seen (as without driving force the species cannot quickly return to their initial positions), but the relatively small recovery seen across all compositions seems to imply that migration has to be considered. For further evaluation, the full recovery for the dielectric composition presenting the higher V th shift (T 39 S 61 ) was studied and is shown in Figure 8b. The recovery took place in a much larger time frame (>1 month) than that of the stress process (1 h) and followed an exponential behavior with a time constant τ ≈ 8 × 10 5 s which suggests a different recovery process than that seen up to 1 h immediately after the stress. As stated before, applying a negative V GS resulted in a much faster recovery of V th (Figure S3a), of just a few minutes. This is in agreement with negative bias stress measurements made in as-fabricated devices (Figure S3b), where a fast increase of V th is observed for the first minutes of stress, with the reverse ∆V th direction in relation to the applied gate bias. Afterwards, V th is fairly stable along the stress time, given the absence of photoinduced holes (measurements under dark conditions) to sustain the commonly observed negative V th shifts under negative bias illumination stress (NBIS) [71].
cess, power dependencies are often related to reaction-diffusion mechanisms. For the compositions presented in Figure 8a, the exponent n changed from ≈0.5 to ≈0.6 after approximately 1 min. For the intermediate TxS100 − x compositions, the exponent changed from ≈0.33 to ≈0.5 after approximately 1-5 min (Figure S4a,b). Similar dependencies were noted for the multilayered stacks ( Figure S4c), further suggesting that the mechanism is not dominated by either of the interfaces. Power law time dependency of ΔV is known for the diffusion of H species in MOSFETs during negative bias temperature stress, where exponents of 1/3 and 1/2 are associated to trap-generation and diffusion of the charged species H + and H2 + , respectively [67]. Aleksandrov et al. also associated n = 1 to first-order chemical-reaction kinetics and n closer to 0.5 to diffusion and drift kinetics of H + ions [68]. While further investigation is needed to understand the involved species in our devices, it is interesting to notice that Ta2O5 dielectrics are known for their ionic conductivity, with H + and VO migration in its bulk being known [69] and partly responsible for their application as resistive switching layers [70]. Regarding the Vth recovery (for VGS = 0 V in Figure 6a), an exponential dependency with time is apparent: while recovering quickly initially, it seems that, at least in the presented time frame, Vth is slowly tending to values significantly larger than the initial ones. Charge migration is often ruled out when fast recoveries are seen (as without driving force the species cannot quickly return to their initial positions), but the relatively small recovery seen across all compositions seems to imply that migration has to be considered. For further evaluation, the full recovery for the dielectric composition presenting the higher Vth shift (T39S61) was studied and is shown in Figure 8b. The recovery took place in a much larger time frame (>1 month) than that of the stress process (1 h) and followed an exponential behavior with a time constant τ 8 × 10 s which suggests a different recovery process than that seen up to 1 h immediately after the stress. As stated before, applying a negative VGS resulted in a much faster recovery of Vth ( Figure S3a), of just a few minutes. This is in agreement with negative bias stress measurements made in as-fabricated devices ( Figure  S3b), where a fast increase of Vth is observed for the first minutes of stress, with the reverse ∆Vth direction in relation to the applied gate bias. Afterwards, Vth is fairly stable along the stress time, given the absence of photoinduced holes (measurements under dark conditions) to sustain the commonly observed negative Vth shifts under negative bias illumination stress (NBIS) [71].
These results point to the anomalous shift being related to the migration of charge within the dielectric, but the nature of the migrating species or type of defects involved is not understood yet.  These results point to the anomalous shift being related to the migration of charge within the dielectric, but the nature of the migrating species or type of defects involved is not understood yet.
While Ta 2 O 5 is known to have a considerable defect density, tending to form suboxides, the V th instability was found to be more pronounced for SiO 2 -richer T x S 100 − x compositions, implying these are more defective. Oxygen displacement in the network due to Si's higher oxygen affinity than Ta is a possible mechanism. In fact, SiO 2 /high-κ dielectrics interfaces are known to form defects, such as dipoles (V O -I O pairs) caused by oxygen displacement (due to deferring oxygen areal densities in these materials [72,73], or oxygen vacancies [74,75]. Note, that the oxygen vacancy formation energy in Ta 2 O 5 is low compared to other high-k dielectrics [76]. Detrapping from either these defects to the gate, their migration inside the dielectric layer, activated by gate bias, or both, can result in the observed anomalous V th shifts. Another possible mechanism is proton migration though the bulk of Ta 2 O 5 [77][78][79], but in this case it would be expected that the anomalous V th shift would have to increase with increased Ta 2 O 5 content, contrary to our findings. Further investigation should be conducted to determine the nature of the charged species involved in the anomalous V th shift.

Conclusions
Multicomponent gate dielectric stacks comprised of both SiO 2 and high-κ Ta 2 O 5 were explored for oxide TFTs with low thermal budgets, compatible with flexible electronics (T = 150 • C). Co-sputtering of both materials as well as the addition of single SiO 2 layers in the gate dielectric stack were considered. While the incorporation of Ta 2 O 5 effectively increases the relative permittivity, the resultant gate dielectric stacks present poor insulation for Ta 2 O 5 contents ≥69%, due to either their poorer insulation capability or poorer band misalignment with the semiconductor. The multilayered approach of including a thin SiO 2 layer at the gate/dielectric interface improved the device reliability by decreasing the probability of devices having significant leakage current (P Leak ) from 56% to 17% when comparing devices with similar multicomponent layers (T 69 S 31 ). Nevertheless, including a thin SiO 2 layer at the IGZO/dielectric interface not only blocks the charge injection into the dielectric, resulting in very reliable gate insulation (P Leak = 0%), but also results in devices with better mobility (16 cm 2 ·V −1 ·s −1 ) and SS (0.15 V·dec −1 ), due to the superior interface between IGZO and SiO 2 than between IGZO and T x S 100 − x mixtures (SS > 0.2 V·dec −1 ), with Ta 2 O 5 richer compositions presenting the poorer interface properties (µ FE = 14.8 cm 2 ·V −1 ·s −1 and SS ≈ 0.25 V·dec −1 for T 75 S 25 ). Counterclockwise hysteresis of the transfer curves and anomalous V th shifts seen during PGBS were, unexpectedly, higher in magnitude for SiO 2 richer compositions, with ∆V th ≈ −102 V and −30 V, after 1 h stress, for the T 39 S 61 and the T 75 S 25 compositions, respectively. Similar behavior of devices employing IGZO/SiO 2 interfaces discarded the interface dominance of the processes while the power law time dependency of V th during gate bias stress, with exponents ≈ 0.5, points towards reaction-diffusion processes. Additionally, the recovery process was very slow, presenting a very high time constant, >8 × 10 5 s. These results imply that the anomalous shift is caused by the migration of charged species inside the dielectric. The increase of V th shift magnitude with the SiO 2 content may suggest that it promotes oxygen vacancies in the mixture by displacing oxygen from Ta 2 O 5 due to its higher oxygen affinity. Regardless, the anomalous shift can be effectively counterbalanced by the inclusion of additional SiO 2 layers in the gate dielectric stack: ∆V th (at 1 h of PGBS) for the T 69 S 31 and T 69 S 31 /SiO 2 stacks are ≈ −41 V and −24 V, respectively, while for the stack with increased number of SiO 2 layers a positive shift of only 1.3 V is obtained. This multilayer approach enables devices that are both reliable and present good performance (mobility = 16 cm 2 ·V −1 ·s −1 , ε r ≈ 13) and that can be successfully implemented into novel flexible electronic applications.
Supplementary Materials: The following are available online at https://www.mdpi.com/2673-3 978/2/1/1/s1, Figure S1. Ar concentration as a function of the Ta 2 O 5 concentration, Figure S2. C-V curves of the MIS employing the T x S 100 − x dielectric layers. The composition and geometrical properties of the MIS are presented in the table, Figure S3. (a) V th shift measured during gate biasing with V GS = 10 V, V GS = 0 V and V GS = −10 V, sequentially, for the T 69 S 31 composition. (b) V th shift measured during negative gate biasing with V GS = −10 V for an as-fabricated device with the T 39 S 61 composition, Figure S4. ∆V th during positive gate bias stress (V GS = 10 V) for the (a) T 60 S 40 , (b) T 69 S 31 and (c) T 69 S 31 /SiO 2 compositions, showing power law time dependencies, Table S1. Molar concentrations and film density obtained by RBS analysis of Ta 2 O 5 , SiO 2 and Ar in the thin films deposited using different powers in the Ta 2 O 5 and SiO 2 targets. Thickness of the films extracted by SE from [53].

Institutional Review Board Statement: Not applicable.
Informed Consent Statement: Not applicable.

Data Availability Statement:
The data presented in this study are available on request from the corresponding authors.