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Micromachines 2018, 9(12), 631; https://doi.org/10.3390/mi9120631

Modeling of Gate Stack Patterning for Advanced Technology Nodes: A Review

Institute for Microelectronics, Technische Universität Wien, Vienna 1040, Austria
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Received: 7 November 2018 / Revised: 20 November 2018 / Accepted: 25 November 2018 / Published: 29 November 2018
(This article belongs to the Special Issue Miniaturized Transistors)
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Abstract

Semiconductor device dimensions have been decreasing steadily over the past several decades, generating the need to overcome fundamental limitations of both the materials they are made of and the fabrication techniques used to build them. Modern metal gates are no longer a simple polysilicon layer, but rather consist of a stack of several different materials, often requiring multiple processing steps each, to obtain the characteristics needed for stable operation. In order to better understand the underlying mechanics and predict the potential of new methods and materials, technology computer aided design has become increasingly important. This review will discuss the fundamental methods, used to describe expected topology changes, and their respective benefits and limitations. In particular, common techniques used for effective modeling of the transport of molecular entities using numerical particle ray tracing in the feature scale region will be reviewed, taking into account the limitations they impose on chemical modeling. The modeling of surface chemistries and recent advances therein, which have enabled the identification of dominant etch mechanisms and the development of sophisticated chemical models, is further presented. Finally, recent advances in the modeling of gate stack pattering using advanced geometries in the feature scale are discussed, taking note of the underlying methods and their limitations, which still need to be overcome and are actively investigated. View Full-Text
Keywords: technology computer-aided design (TCAD); metal oxide semiconductor field effect transistor (MOSFET); topography simulation; metal gate stack; level set; high-k; fin field effect transistor (FinFET) technology computer-aided design (TCAD); metal oxide semiconductor field effect transistor (MOSFET); topography simulation; metal gate stack; level set; high-k; fin field effect transistor (FinFET)
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This is an open access article distributed under the Creative Commons Attribution License which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited (CC BY 4.0).
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Klemenschits, X.; Selberherr, S.; Filipovic, L. Modeling of Gate Stack Patterning for Advanced Technology Nodes: A Review. Micromachines 2018, 9, 631.

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