Development and Performance Analysis of High-K Spacer-Induced Strained Si/SiGe Channel-Based Gate All Around FET for Thermal Effects

Yugender, Potaraju; Singh, Sneha; Kumar, Kuleen; Dhar, Rudra Sankar; Seteikin, Alexey Y.; Banerjee, Amit; Samusev, Ilia G.

doi:10.3390/nano15231810

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Development and Performance Analysis of High-K Spacer-Induced Strained Si/SiGe Channel-Based Gate All Around FET for Thermal Effects

by

Potaraju Yugender

^1,2,

Sneha Singh

¹,

Kuleen Kumar

³,

Rudra Sankar Dhar

^1,*

,

Alexey Y. Seteikin

⁴

,

Amit Banerjee

^5,*

and

Ilia G. Samusev

^4,*

¹

Department of Electronics and Communication Engineering, National Institute of Technology Mizoram, Chaltlang, Aizawl 796012, Mizoram, India

²

Department of Electronics and Communication Engineering, Malla Reddy (MR) (Deemed to be University), Hyderabad 500100, Telangana, India

³

Department of Electronics and Communication Engineering, National Institute of Technology Puducherry, Thiruvettakudy, Karaikal 609609, Puducherry, India

⁴

Research and Education Center for Fundamental and Applied Photonics & Nanophotonics, Immanuel Kant Baltic Federal University, 236000 Kaliningrad, Russia

⁵

Microsystem Design Integration, Laboratory of Physics Department, Bidhan Chandra College, Asansol 713303, West Bengal, India

^*

Authors to whom correspondence should be addressed.

Nanomaterials 2025, 15(23), 1810; https://doi.org/10.3390/nano15231810 (registering DOI)

Submission received: 25 October 2025 / Revised: 13 November 2025 / Accepted: 25 November 2025 / Published: 29 November 2025

(This article belongs to the Section Nanophotonics Materials and Devices)

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Abstract

A Gate Stack GAA FET using SiGe with a 2 nm gate underlap encapsulating a high-k spacer has been created, explored, and evaluated for improved performance in radio frequency applications. The chip shows significant improvements in electrical and radio frequency analog performance because of the use of wrapped underlaps of high-k, which suppress parasitic capacitance and fringing field effects, to achieve a 192.52% boost in drain current and 98% reduction in I_OFF current, translating into better performance. This new device, as proposed, has demonstrated improved switching behavior with the ability to reduce subthreshold swing by about 11.24% and results in a better Ion/Ioff ratio over existing devices, while also maintaining efficient control over other SCEs, with it being well-suited for the implementation of high-performance and low-power CMOS circuits. In addition, linearity parameters like VIP2, VIP3, and IIP3 reflect improvements, with the device having lesser harmonic distortions (IMD3 and THD), therefore making it more appropriate for RF and analog circuit uses. These results point to the prospect of SiGe-based Gate Stack GAA FETs with a 2 nm gate underlap encircling a high-k spacer for low-power, high-speed applications in IoT and 5G/6G technologies toward building environmentally friendly and sustainable electronic solutions.

Keywords: gate stack; Si/SiGe channel; GAA FET; linearity and harmonics analysis

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MDPI and ACS Style

Yugender, P.; Singh, S.; Kumar, K.; Dhar, R.S.; Seteikin, A.Y.; Banerjee, A.; Samusev, I.G. Development and Performance Analysis of High-K Spacer-Induced Strained Si/SiGe Channel-Based Gate All Around FET for Thermal Effects. Nanomaterials 2025, 15, 1810. https://doi.org/10.3390/nano15231810

AMA Style

Yugender P, Singh S, Kumar K, Dhar RS, Seteikin AY, Banerjee A, Samusev IG. Development and Performance Analysis of High-K Spacer-Induced Strained Si/SiGe Channel-Based Gate All Around FET for Thermal Effects. Nanomaterials. 2025; 15(23):1810. https://doi.org/10.3390/nano15231810

Chicago/Turabian Style

Yugender, Potaraju, Sneha Singh, Kuleen Kumar, Rudra Sankar Dhar, Alexey Y. Seteikin, Amit Banerjee, and Ilia G. Samusev. 2025. "Development and Performance Analysis of High-K Spacer-Induced Strained Si/SiGe Channel-Based Gate All Around FET for Thermal Effects" Nanomaterials 15, no. 23: 1810. https://doi.org/10.3390/nano15231810

APA Style

Yugender, P., Singh, S., Kumar, K., Dhar, R. S., Seteikin, A. Y., Banerjee, A., & Samusev, I. G. (2025). Development and Performance Analysis of High-K Spacer-Induced Strained Si/SiGe Channel-Based Gate All Around FET for Thermal Effects. Nanomaterials, 15(23), 1810. https://doi.org/10.3390/nano15231810

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Development and Performance Analysis of High-K Spacer-Induced Strained Si/SiGe Channel-Based Gate All Around FET for Thermal Effects

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