Instability in In_0.7Ga_0.3As Quantum-Well MOSFETs with Single-Layer Al₂O₃ and Bi-Layer Al₂O₃/HfO₂ Gate Stacks Caused by Charge Trapping under Positive Bias Temperature (PBT) Stress

Abstract

The instability of transistor characteristics caused by charge trapping under positive bias temperature (PBT) stress in In_0.7Ga_0.3As metal oxide semiconductor field-effect transistors (MOSFETs) with single-layer Al₂O₃ and bi-layer Al₂O₃/HfO₂ gate stacks was investigated. The equivalent field across the multi-gate stacks was compared with a single layer used to compare the instability of electrical characteristics. The observed threshold voltage degradation (ΔV_T) was consistent with the phenomenon of fast transient trapping of injected electrons at pre-existing shallow defects in the high-κ dielectric of HfO₂, in which this charging was recovered by applying a relaxation voltage. Excluding the fast-transient charging components, the power law exponent (n), with respect to the time-dependent threshold voltage degradation, ranged from 0.3 to 0.35 for both single-layer Al₂O₃ and bi-layer Al₂O₃/HfO₂ gate stacks. This long-term (slow) V_T shift, which was strongly correlated with transconductance (G_m) degradation, was attributed to significant charge trapping in the border trap or/and defect sites within the high-κ dielectric.

1. Introduction

III-V n-channel metal oxide semiconductor field-effect transistors (MOSFETs) have demonstrated much better electron mobility and injection velocity than transistors with a silicon (Si) channel, making them attractive for future high-speed, low-power logic applications [1,2,3]. Among the various channel materials (GaAs, InP, GaN, and InGaAs) in III-V MOSFETs [1,2,3,4,5], interest in indium-rich In_xGa_1-xAs channel materials, x > 0.53, have recently been considered the most promising replacement of conventional Si-based n-channel materials because of their high electron mobility, high drive current capability, and mature technology for defense applications [3,4,5]. The small electron effective mass of indium-rich In_xGa_1−xAs quantum-well (QW) channels has led to a significant increase of importance of a ballistic transport in the overall electron transport because of the carrier confinement to a deep quantum well [4,5]. The QW structures compared with the n-MOSFET provide better electrostatic control of the channel from the top gate as the devices are aggressively scaled down [4,5]. However, the unstable native oxides on III-V channel materials, such as As₂O₃, As₂O₅, and InO_x, lead to poor electrical properties [6,7]. To fully benefit from intrinsic properties, it is important to minimize the interfacial defect sites in the interfacial self-cleaning reaction process via atomic layer deposition (ALD) using trimethylaluminum (TMA) as the precursor for the Al₂O₃ layer [6,7,8]. An Al₂O₃ layer is insufficient for providing a low equivalent oxide thickness (EOT) and low gate leakage current [4,5]. Therefore, several researchers have deposited high-κ dielectrics, such as HfO₂ (~25) and ZrO₂ (~30), on ultrathin Al₂O₃ layers, improving the electrical properties [4,5,9,10]. The defect sites associated with interfacial traps and high-κ dielectric layers deteriorate the subthreshold-swing (SS) and mobility in the channel, and therefore degrade the on current (I_ON)/off current (I_OFF) ratio [4]. Electron trapping phenomena for InGaAs QW MOSFETs with a high-κ dielectric during device operation can cause a frequency dispersion and shift in ΔV_T, which would cause a severe reliability concern [9,10]. Use of the InGaAs QW MOSFETs to realize the next n-MOSFET application has faced major reliability issues [9,10]. In particular, the electrical parameters under the positive bias temperature (PBT) stress condition may change over operation time, including the on current, threshold voltage degradation, SS, and transconductance (G_m) degradation [9,10]. The degradation of InGaAs QW MOSFETs under the PBT stress condition might be more important than that of the Si-based MOSFETs due to higher interfacial trap density (D_it) and border and bulk traps with high-κ dielectric. There have been only a few reports regarding the relevant instability of electrical characteristics issues in In_0.7Ga_0.3As QW MOSFETs with high-κ dielectrics.

In this paper, we report a study on the instability of electrical characteristics for In_0.7Ga_0.3As QW MOSFETs with single-layer Al₂O₃ and bi-layer Al₂O₃/HfO₂. To verify the degradation mechanism of In_0.7Ga_0.3As QW MOSFETs with the high-κ dielectric under PBT stress condition, the electrical field across single-layer Al₂O₃ and bi-layer Al₂O₃/HfO₂ gate stacks were observed. Finally, we investigated the relationship between ΔV_T degradation, injected charge, and G_m.Max degradation under different PBT stress conditions in In_0.7Ga_0.3As QW MOSFETs with single-layer Al₂O₃ and bi-layer Al₂O₃/HfO₂ gate stacks.

2. Experimental Details

The epitaxial layer in the In_0.7Ga_0.3As QW MOSFETs consists of a heavily doped n⁺ InGaAs capping layer, an In_0.7Ga_0.3As channel, an inverted Si δ-doping layer, and an In_0.48Al_0.52As back buffer or barrier on an InP substrate [3,4,5]. Mesa etching was performed by wet chemical etching to isolate the devices. Source and drain ohmic contacts to the n⁺ InGaAs were formed using e-beam evaporation and subsequent lift-off of the Mo/Ti/Au metal stack. SiO₂ was deposited at the temperatures <150 °C by plasma-enhanced chemical vapor deposition (PECVD), and the gate pattern was defined by electron beam lithography (EBL). SiO₂ on the heavily doped n⁺ InGaAs capping layer was etched using CF₄ reactive ion etching (RIE). Gate recess process of the heavily doped n⁺ InGaAs capping layer was etched to expose the InP layer using an H₃PO₄ based solution. Then, either Al₂O₃ (2.0 nm) or Al₂O₃ (0.7 nm)/HfO₂ (1.6 nm) stacked dielectrics were grown sequentially on the In_0.7Ga_0.3As channel using ALD. Deposition temperatures used for the Al₂O₃ and HfO₂ were 250 °C and 150 °C, respectively. After deposition of the high-κ gate stack on the In_0.7Ga_0.3As channel, a 5-nm TiN metal-gate (MG) was deposited in-situ by ALD. Finally, a Ti/Au gate metal pad was deposited by beam evaporation. The electrical characteristics were evaluated using an Agilent 4156C semiconductor parameter analyzer. The PBT stress condition (V_GS − V_T = V_stress), which was normalized to V_T, was applied at the gate with the other terminals grounded. The instability of electrical characteristics under PBT stress condition was performed by a Summit 11K Cascade probe station with an integrated Temptronic thermochuck able to heat the wafer till temperatures to 200 °C. The injected electron on each stress time was being monitored by the gate current under the PBT stress condition. The injected charge (Q_inj) was obtained from the monitored gate current integral of each stress time.

3. Results and Discussion

3.1. Distribution of the Electrical Field Across Gate Stacks on the Applied Stress Voltage

To compare the instability of electrical characteristics of single layer and multi-gate stacks, it is imperative to consider the equivalent field across the multi-gate stacks compared with a single layer because it is further complicated by the interaction between different materials [11,12]. The In_0.7Ga_0.3As QW MOSFETs structure with a high-κ dielectric usually consists of multi-gate stacks, including the interfacial layer and the high-κ dielectric layer. Hence, the electrical field across multi-gate stacks can be determined easily base on simple electrostatics rules as reported in References [11,12]. The electrical field in bi-layer Al₂O₃/HfO₂ gate stacks in the In_0.7Ga_0.3As QW MOSFETs is given by Equation (1) [11]

$$\begin{array}{l}{E}_{A{l}_2{O}_3}=\frac{V_A}{\left(\frac{{\epsilon }_{A{l}_2{O}_3}}{{\epsilon }_{Hf{O}_2}}\right)t_{Hf{O}_2}+t_{A{l}_2{O}_3}}\\ E_{Hf{O}_2}=\frac{V_A}{\left(\frac{{\epsilon }_{Hf{O}_2}}{{\epsilon }_{A{l}_2{O}_3}}\right)t_{A{l}_2{O}_3}+t_{Hf{O}_2}}\end{array}$$

(1)

where E_HfO2 and E_Al2o3 are the electrical fields across the high-κ dielectric and interfacial layers, respectively. t_HfO2 and t_Al2O3 are the physical thicknesses. κ_HfO2 and κ_Al2O3 are the dielectric constants. V_A is the applied voltage or the applied stress voltage across gate stack.

To understand the role of the interfacial layer and high-κ dielectric layer, the calculated electrical field and the energy-band diagram for single-layer Al₂O₃ and bi-layer Al₂O₃/HfO₂ is plotted with respect to the applied stress voltage as shown in Figure 1. If the electrical field in the ultra-thin interfacial layer is sufficiently high, most carriers of InGaAs channel easily tunnel across the interfacial layer to border traps or/and defect sites within the high-κ dielectric layers [11,13,14]. It is important to verify the degradation of the main high-κ dielectric layer caused by the applied stress voltage.

The electric field in the main high-κ layers, which are HfO₂ for bi-layer Al₂O₃/HfO₂ gate stacks and Al₂O₃ for single-layer Al₂O₃, is similar according to the calculated effective thickness. Generally, the electrical stress fields in the silicon dioxide layer in Si-based high-κ dielectric and silicon germanium (SiGe) MOSFETs have been reported to be on the order of 5–6 MV/cm, which is a dominant region in the Fowler–Nordheim (F-N) tunneling mechanism [11,12]. Although the time zero dielectric breakdown (TZDB) voltage of the high-κ dielectrics in III-V MOSFETs is similar to the values previously reported for high-κ dielectrics [11,12], the smaller band gap of the InGaAs channel and higher D_it between the InGaAs channel and interfacial layer in III-V MOSFETs may seriously degrade the dielectric/substrate interface and high-κ region because of the high vertical field [11,12]. Because these phenomena are related to the properties (effective mass, band gap, etc.) of the channel materials themselves, these stress conditions for the QW III-V MOSFETs, which are 5–6 M/cm, may be inadequate. Therefore, the appropriate PBT stress voltage should be chosen considering the properties of the channel materials and the higher D_it between the InGaAs channel and high-κ dielectric.

3.2. Impact of Charge Trapping in Defect Sites under Positive Bias Temperature (PBT) Stress Condition

Figure 2 presents the trapping and relaxation characteristics during two stress/recovery cycles for single-layer Al₂O₃ and bi-layer Al₂O₃/HfO₂ In_0.7Ga_0.3As QW MOSFETs under different PBT stress conditions. The observed threshold voltage degradation (ΔV_T) is consistent with the phenomenon of electron trapping at defect sites within the high-κ dielectric layer. These charges can be detrapped by applying a relaxation voltage at V_GS = 0 V, as shown in Figure 2. The ΔV_T degradation may be related to two types of traps: The fast-transient trap over short durations (<1 msec) and the slow trap over long durations [13,14,15,16,17,18]. The initial V_T shift for single-layer Al₂O₃ and bi-layer Al₂O₃/HfO₂ In_0.7Ga_0.3As QW MOSFETs during the first 1 s of DC stress shows a substantial change because of the fast transient charging at defect sites in the HfO₂ dielectric, while the initial ΔV_T shift is much less in the Al₂O₃ In_0.7Ga_0.3As QW MOSFETs [15,16,17,18]. The fast-transient charging is from electron tunneling from the InGaAs surface directly into the pre-existing shallow traps within the high-κ dielectric layer, which should be subtracted from the initial 1 s stress for a more accurate evaluation [13,14]. The time dependence of the ΔV_T degradation was investigated to quantitatively studying the charge trapping phenomenon. After subtracting the fast-transient charge trapping component, which is reported to fully saturate within <1 s of stress, the time dependency of the V_T shift (ΔV_T − ΔV_T.initial (1 s)) can be described by a power law expression ΔV_T~tⁿ [13,14,15,16,17,18,19]. The exponent n of this dependency is in the range of 0.3 to 0.35 for single-layer Al₂O₃ and bi-layer Al₂O₃/HfO₂ gate stacks, as shown in Figure 3. Note that ΔV_T values for bi-layer Al₂O₃/HfO₂ gate stacks are greater than that for single-layer Al₂O₃ while the exponent n values are similar, which are likely associated with the higher trap density in the HfO₂.

To further investigate the charge trapping characteristics, ΔV_T was plotted as a function of the injected charge under different PBT stress conditions as shown in Figure 4a. The similar slopes of Q_trapped/Q_inj for single-layer Al₂O₃ and bi-layer Al₂O₃/HfO₂ gate stacks (Figure 4b) indicate that these stacks exhibited similar charge trapping efficiencies [11,15,16,20,21,22]. The injected charges from the InGaAs channel are mostly trapped in defect sites within the high-κ dielectric. The long-term V_T shift, ΔV_T – ΔV_T.initial (1 s), correlates well with the percentage of transconductance (%G_m.Max) degradation for single-layer Al₂O₃ and bi-layer Al₂O₃/HfO₂ gate stacks, as shown in Figure 5. Generally, G_m.Max degradation is related to the generation of interfacial state traps and Coulomb centers in the near-interface dielectric region [21,22]. However, G_m.Max degradation increases as the amount of trapped electrons increases, as shown in Figure 5, which means that remote scattering is a sensitive factor in high-κ dielectric [11,15,16,20,21,22]. Therefore, the correlation seen between the G_m.Max and ΔV_T − ΔV_T.initial (1 s) implies that significant charge trapping occurred in the border trap or/and defect sites within the high-κ dielectric, which is in the main high-κ dielectric layers for single-layer Al₂O₃ and bi-layer Al₂O₃/HfO₂ gate stacks.

Although the bi-layer Al₂O₃/HfO₂ gate stack in In_0.7Ga_0.3As QW MOSFETs demonstrated superior electrical performance (compared with the Al₂O₃) because of its lower EOT [3,4,5], a large density of oxygen vacancies within high-κ dielectrics still caused V_T instability [11,15,16,17,18,20,21,22,23]. Since the defects in the HfO₂-based dielectrics are related to oxygen vacancies in different charge states, from V²⁺ to V²⁻ levels as shown in Figure 1c [11,17,21,22,23], which can reversibly trap the injected electrons, improving the reliability characteristics of high-κ dielectric devices requires oxygen vacancies to be passivated. One of the methods is a high-pressure hydrogen or deuterium annealing.

4. Conclusions

We investigated the instability of electrical characteristics of III-V MOSFETs with single-layer Al₂O₃ and bi-layer Al₂O₃/HfO₂ gate stacks under PBT stress. The initial (within the first stress second) ΔV_T shift in the bi-layer Al₂O₃/HfO₂ III-V MOSFETs was consistent with the phenomenon of fast transient trapping/detrapping of injected electrons at pre-existing shallow defects in the high-κ dielectric film. Long-term V_T degradation with single-layer Al₂O₃ and bi-layer Al₂O₃/HfO₂ gate stacks in III-V QW MOSFETs exhibited slow charging responsible for the ΔV_T power law time dependency. The observed correlation between the %G_m.Max and ΔV_T − ΔV_T.initial (1 s) degradations indicated that this slow charge trapping occurred in border trap or/and defect sites within the high-κ dielectric, which was in the main high-κ dielectric layers of the single-layer Al₂O₃ and bi-layer Al₂O₃/HfO₂ gate stacks. These results indicate that the defect density must be reduced in the high-κ dielectric to improve the stability of In_0.7Ga_0.3As QW MOSFETs with single-layer Al₂O₃ and bi-layer Al₂O₃/HfO₂ gate stacks.