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2,358 Results Found

  • Article
  • Open Access
8 Citations
5,171 Views
23 Pages

A SHA-256 Hybrid-Redundancy Hardware Architecture for Detecting and Correcting Errors

  • Ignacio Algredo-Badillo,
  • Miguel Morales-Sandoval,
  • Alejandro Medina-Santiago,
  • Carlos Arturo Hernández-Gracidas,
  • Mariana Lobato-Baez and
  • Luis Alberto Morales-Rosales

3 July 2022

In emergent technologies, data integrity is critical for message-passing communications, where security measures and validations must be considered to prevent the entrance of invalid data, detect errors in transmissions, and prevent data loss. The SH...

  • Feature Paper
  • Article
  • Open Access
1 Citations
1,838 Views
20 Pages

Hardware Architecture for Asynchronous Cellular Self-Organizing Maps

  • Quentin Berthet,
  • Joachim Schmidt and
  • Andres Upegui

Nowadays, one of the main challenges in computer architectures is scalability; indeed, novel processor architectures can include thousands of processing elements on a single chip and using them efficiently remains a big issue. An interesting source o...

  • Article
  • Open Access
10 Citations
5,591 Views
17 Pages

Modular Hardware Architecture for the Development of Underwater Vehicles Based on Systems Engineering

  • Luis M. Aristizábal,
  • Carlos A. Zuluaga,
  • Santiago Rúa and
  • Rafael E. Vásquez

This paper addresses the development of a modular hardware architecture for the design/construction/operation of a remotely operated vehicle (ROV), based on systems engineering. The Vee model is first presented as a sequential process that emphasizes...

  • Article
  • Open Access
5 Citations
5,756 Views
14 Pages

RT Engine: An Efficient Hardware Architecture for Ray Tracing

  • Run Yan,
  • Libo Huang,
  • Hui Guo,
  • Yashuai Lü,
  • Ling Yang,
  • Nong Xiao,
  • Yongwen Wang,
  • Li Shen and
  • Mengqiao Lan

24 September 2022

The reality of the ray tracing technology that leads to its rendering effect is becoming increasingly apparent in computer vision and industrial applications. However, designing efficient ray tracing hardware is challenging due to memory access issue...

  • Article
  • Open Access
128 Citations
66,806 Views
27 Pages

Nanorobot Hardware Architecture for Medical Defense

  • Adriano Cavalcanti,
  • Bijan Shirinzadeh,
  • Mingjun Zhang and
  • Luiz C. Kretly

6 May 2008

This work presents a new approach with details on the integrated platform and hardware architecture for nanorobots application in epidemic control, which should enable real time in vivo prognosis of biohazard infection. The recent developments in the...

  • Article
  • Open Access
4 Citations
3,855 Views
17 Pages

Since the lightweight convolutional neural network EfficientNet was proposed by Google in 2019, the series of models have quickly become very popular due to their superior performance with a small number of parameters. However, the existing convoluti...

  • Article
  • Open Access
6 Citations
3,311 Views
16 Pages

An Analysis on the Architecture and the Size of Quantized Hardware Neural Networks Based on Memristors

  • Rocio Romero-Zaliz,
  • Antonio Cantudo,
  • Eduardo Perez,
  • Francisco Jimenez-Molinos,
  • Christian Wenger and
  • Juan Bautista Roldan

17 December 2021

We have performed different simulation experiments in relation to hardware neural networks (NN) to analyze the role of the number of synapses for different NN architectures in the network accuracy, considering different datasets. A technology that st...

  • Article
  • Open Access
10 Citations
7,828 Views
29 Pages

27 May 2022

Safety-critical intelligent automotive systems require stringent dependability while the systems are in operation. Therefore, safety and reliability issues must be addressed in the development of such safety-critical systems. Nevertheless, the incorp...

  • Article
  • Open Access
416 Views
19 Pages

A Reconfigurable CNN-2D Hardware Architecture for Real-Time Brain Cancer Multi-Classification on FPGA

  • Ayoub Mhaouch,
  • Wafa Gtifa,
  • Ibtihel Nouira,
  • Abdessalem Ben Abdelali and
  • Mohsen Machhout

1 February 2026

Brain cancer classification using deep learning has gained significant attention due to its potential to improve early diagnosis and treatment planning. In this work, we propose a reconfigurable and hardware-optimized CNN-2D architecture implemented...

  • Article
  • Open Access
47 Citations
9,112 Views
29 Pages

13 October 2019

Object detection in remote sensing images on a satellite or aircraft has important economic and military significance and is full of challenges. This task requires not only accurate and efficient algorithms, but also high-performance and low power ha...

  • Article
  • Open Access
3 Citations
3,682 Views
19 Pages

Analysis and Hardware Architecture on FPGA of a Robust Audio Fingerprinting Method Using SSM

  • Ignacio Algredo-Badillo,
  • Brenda Sánchez-Juárez,
  • Kelsey A. Ramírez-Gutiérrez,
  • Claudia Feregrino-Uribe,
  • Francisco López-Huerta and
  • Johan J. Estrada-López

The significant volume of sharing of digital media has recently increased due to the pandemic, raising the number of unauthorized uses of these media, such as emerging unauthorized copies, forgery, the lack of copyright, and electronic fraud, among o...

  • Article
  • Open Access
464 Views
14 Pages

A Flexible Multi-Core Hardware Architecture for Stereo-Based Depth Estimation CNNs

  • Steven Colleman,
  • Andrea Nardi-Dei,
  • Marc C. W. Geilen,
  • Sander Stuijk and
  • Toon Goedemé

13 November 2025

Stereo-based depth estimation is becoming more and more important in many applications like self-driving vehicles, earth observation, cartography, robotics and so on. Modern approaches to depth estimation employ artificial intelligence techniques, pa...

  • Article
  • Open Access
23 Citations
3,883 Views
23 Pages

ESC-NAS: Environment Sound Classification Using Hardware-Aware Neural Architecture Search for the Edge

  • Dakshina Ranmal,
  • Piumini Ranasinghe,
  • Thivindu Paranayapa,
  • Dulani Meedeniya and
  • Charith Perera

9 June 2024

The combination of deep-learning and IoT plays a significant role in modern smart solutions, providing the capability of handling task-specific real-time offline operations with improved accuracy and minimised resource consumption. This study provide...

  • Article
  • Open Access
4 Citations
4,254 Views
19 Pages

The widespread use of the internet of things (IoT) is due to the value of the data collected by IoT devices. These IoT devices generate, process, and exchange large amounts of safety-critical or privacy-sensitive data. Before transmission, the data s...

  • Article
  • Open Access
1 Citations
1,494 Views
28 Pages

Hardware-Aware Neural Architecture Search for Real-Time Video Processing in FPGA-Accelerated Endoscopic Imaging

  • Cunguang Zhang,
  • Rui Cui,
  • Gang Wang,
  • Tong Gao,
  • Jielu Yan,
  • Weizhi Xian,
  • Xuekai Wei and
  • Yi Qin

19 October 2025

Medical endoscopic video processing requires real-time execution of color component acquisition, color filter array (CFA) demosaicing, and high dynamic range (HDR) compression under low-light conditions, while adhering to strict thermal constraints w...

  • Article
  • Open Access
2 Citations
2,373 Views
19 Pages

Field-Programmable Gate Array Architecture for the Discrete Orthonormal Stockwell Transform (DOST) Hardware Implementation

  • Martin Valtierra-Rodriguez,
  • Jose-Luis Contreras-Hernandez,
  • David Granados-Lieberman,
  • Jesus Rooney Rivera-Guillen,
  • Juan Pablo Amezquita-Sanchez and
  • David Camarena-Martinez

Time–frequency analysis is critical in studying linear and non-linear signals that exhibit variations across both time and frequency domains. Such analysis not only facilitates the identification of transient events and extraction of key featur...

  • Article
  • Open Access
9 Citations
3,152 Views
16 Pages

27 January 2021

In this paper, a real-time implementation of a sliding-mode control (SMC) in a hardware-in-loop architecture is presented for a robot with two degrees of freedom (2DOF). It is based on a discrete-time recurrent neural identification method, as well a...

  • Article
  • Open Access
13 Citations
3,435 Views
17 Pages

With the limitedness of the sub-6 GHz bandwidth, the world is exploring a thrilling wireless technology known as massive MIMO. This wireless access technology is swiftly becoming key for 5G, B5G, and 6G network deployment. The massive MIMO system bri...

  • Article
  • Open Access
2 Citations
10,199 Views
39 Pages

CASPER: Embedding Power Estimation and Hardware-Controlled Power Management in a Cycle-Accurate Micro-Architecture Simulation Platform for Many-Core Multi-Threading Heterogeneous Processors

  • Kushal Datta,
  • Arindam Mukherjee,
  • Guangyi Cao,
  • Rohith Tenneti,
  • Vinay Vijendra Kumar Lakshmi,
  • Arun Ravindran and
  • Bharat S. Joshi

Despite the promising performance improvement observed in emerging many-core architectures in high performance processors, high power consumption prohibitively affects their use and marketability in the low-energy sectors, such as embedded processors...

  • Review
  • Open Access
38 Citations
15,867 Views
34 Pages

Hardware Architectures for Real-Time Medical Imaging

  • Eduardo Alcaín,
  • Pedro R. Fernández,
  • Rubén Nieto,
  • Antonio S. Montemayor,
  • Jaime Vilas,
  • Adrian Galiana-Bordera,
  • Pedro Miguel Martinez-Girones,
  • Carmen Prieto-de-la-Lastra,
  • Borja Rodriguez-Vila and
  • Angel Torrado-Carvajal
  • + 6 authors

15 December 2021

Medical imaging is considered one of the most important advances in the history of medicine and has become an essential part of the diagnosis and treatment of patients. Earlier prediction and treatment have been driving the acquisition of higher imag...

  • Review
  • Open Access
170 Citations
17,948 Views
22 Pages

An Updated Survey of Efficient Hardware Architectures for Accelerating Deep Convolutional Neural Networks

  • Maurizio Capra,
  • Beatrice Bussolino,
  • Alberto Marchisio,
  • Muhammad Shafique,
  • Guido Masera and
  • Maurizio Martina

Deep Neural Networks (DNNs) are nowadays a common practice in most of the Artificial Intelligence (AI) applications. Their ability to go beyond human precision has made these networks a milestone in the history of AI. However, while on the one hand t...

  • Article
  • Open Access
15 Citations
6,746 Views
28 Pages

Efficient Architecture for Spike Sorting in Reconfigurable Hardware

  • Wen-Jyi Hwang,
  • Wei-Hao Lee,
  • Shiow-Jyu Lin and
  • Sheng-Ying Lai

1 November 2013

This paper presents a novel hardware architecture for fast spike sorting. The architecture is able to perform both the feature extraction and clustering in hardware. The generalized Hebbian algorithm (GHA) and fuzzy C-means (FCM) algorithm are used f...

  • Article
  • Open Access
1,354 Views
30 Pages

25 December 2025

With the increasing computational demands of large language models (LLMs), there is a pressing need for more specialized hardware architectures capable of supporting their dynamic and memory-intensive workloads. This paper examines recent studies on...

  • Article
  • Open Access
4 Citations
3,163 Views
16 Pages

Transcendental functions are an important part of algorithms in many fields. However, the hardware accelerators available today for transcendental functions typically only support one such function. Hardware accelerators that can support miscellaneou...

  • Article
  • Open Access
4 Citations
3,938 Views
27 Pages

Hardware-Based Architecture for DNN Wireless Communication Models

  • Van Duy Tran,
  • Duc Khai Lam and
  • Thi Hong Tran

23 January 2023

Multiple Input Multiple Output Orthogonal Frequency Division Multiplexing (MIMO OFDM) is a key technology for wireless communication systems. However, because of the problem of a high peak-to-average power ratio (PAPR), OFDM symbols can be distorted...

  • Article
  • Open Access
19 Citations
8,634 Views
10 Pages

Area-Time Efficient Hardware Architecture for CRYSTALS-Kyber

  • Tuy Tan Nguyen,
  • Sungjae Kim,
  • Yongjun Eom and
  • Hanho Lee

24 May 2022

This paper presents a novel area-time efficient hardware architecture of the lattice-based CRYSTALS-Kyber, which has entered the third round of the post-quantum cryptography standardization competition hosted by the National Institute of Standards an...

  • Article
  • Open Access
8 Citations
5,730 Views
26 Pages

Hybrid Pipeline Hardware Architecture Based on Error Detection and Correction for AES

  • Ignacio Algredo-Badillo,
  • Kelsey A. Ramírez-Gutiérrez,
  • Luis Alberto Morales-Rosales,
  • Daniel Pacheco Bautista and
  • Claudia Feregrino-Uribe

22 August 2021

Currently, cryptographic algorithms are widely applied to communications systems to guarantee data security. For instance, in an emerging automotive environment where connectivity is a core part of autonomous and connected cars, it is essential to gu...

  • Article
  • Open Access
5 Citations
2,422 Views
14 Pages

11 October 2022

Symmetric convolutions can be utilized for potential hardware resource reduction. However, they have not been realized in state-of-the-art transposed block FIR designs. Therefore, we explore the feasibility of symmetric convolution in transposed para...

  • Article
  • Open Access
2 Citations
6,158 Views
23 Pages

27 August 2012

A novel k-winners-take-all (k-WTA) competitive learning (CL) hardware architecture is presented for on-chip learning in this paper. The architecture is based on an efficient pipeline allowing k-WTA competition processes associated with different trai...

  • Article
  • Open Access
10 Citations
5,647 Views
20 Pages

Depth from a Motion Algorithm and a Hardware Architecture for Smart Cameras

  • Abiel Aguilar-González,
  • Miguel Arias-Estrada and
  • François Berry

23 December 2018

Applications such as autonomous navigation, robot vision, and autonomous flying require depth map information of a scene. Depth can be estimated by using a single moving camera (depth from motion). However, the traditional depth from motion algorithm...

  • Article
  • Open Access
1 Citations
3,736 Views
17 Pages

Hardware Architecture for Realtime HEVC Intra Prediction

  • Duc Khai Lam,
  • Pham The Anh Nguyen and
  • Tuan Anh Tran

Researchers have, in recent times, achieved excellent compression efficiency by implementing a more complicated compression algorithm due to the rapid development of video compression. As a result, the next model of video compression, High-Efficiency...

  • Article
  • Open Access
12 Citations
6,268 Views
12 Pages

High Throughput PRESENT Cipher Hardware Architecture for the Medical IoT Applications

  • Jamunarani Damodharan,
  • Emalda Roslin Susai Michael and
  • Nasir Shaikh-Husin

The Internet of Things (IoT) is an intelligent technology applied to various fields like agriculture, healthcare, automation, and defence. Modern medical electronics is also one such field that relies on IoT. Execution time, data security, power, and...

  • Article
  • Open Access
15 Citations
5,399 Views
15 Pages

28 August 2023

Hash functions are an essential mechanism in today’s world of information security. It is common practice to utilize them for storing and verifying passwords, developing pseudo-random sequences, and deriving keys for various applications, inclu...

  • Feature Paper
  • Article
  • Open Access
4 Citations
12,779 Views
36 Pages

A Dynamically Reconfigurable BbNN Architecture for Scalable Neuroevolution in Hardware

  • Alberto García,
  • Rafael Zamacola,
  • Andrés Otero and
  • Eduardo de la Torre

In this paper, a novel hardware architecture for neuroevolution is presented, aiming to enable the continuous adaptation of systems working in dynamic environments, by including the training stage intrinsically in the computing edge. It is based on t...

  • Article
  • Open Access
13 Citations
7,809 Views
17 Pages

Distributed and Modular CAN-Based Architecture for Hardware Control and Sensor Data Integration

  • Diego P. Losada,
  • Joaquín L. Fernández,
  • Enrique Paz and
  • Rafael Sanz

3 May 2017

In this article, we present a CAN-based (Controller Area Network) distributed system to integrate sensors, actuators and hardware controllers in a mobile robot platform. With this work, we provide a robust, simple, flexible and open system to make ha...

  • Article
  • Open Access
13 Citations
4,521 Views
16 Pages

11 February 2023

Convolutional neural network (CNN) is widely deployed on edge devices, performing tasks such as objective detection, image recognition and acoustic recognition. However, the limited resources and strict power constraints of edge devices pose a great...

  • Article
  • Open Access
2 Citations
1,603 Views
18 Pages

3 November 2023

Self-organizing map (SOM) is a type of artificial neural network that provides a nonlinear mapping from a given high-dimensional input space to a low-dimensional map of neurons for clustering. The clustering of high-dimensional vectors is too slow fo...

  • Article
  • Open Access
9 Citations
9,436 Views
29 Pages

A JND-Based Pixel-Domain Algorithm and Hardware Architecture for Perceptual Image Coding

  • Zhe Wang,
  • Trung-Hieu Tran,
  • Ponnanna Kelettira Muthappa and
  • Sven Simon

This paper presents a hardware efficient pixel-domain just-noticeable difference (JND) model and its hardware architecture implemented on an FPGA. This JND model architecture is further proposed to be part of a low complexity pixel-domain perceptual...

  • Article
  • Open Access
3 Citations
2,970 Views
19 Pages

6 November 2022

Deep neural networks have been deployed in various hardware accelerators, such as graph process units (GPUs), field-program gate arrays (FPGAs), and application specific integrated circuit (ASIC) chips. Normally, a huge amount of computation is requi...

  • Article
  • Open Access
7 Citations
4,024 Views
29 Pages

An SHA-3 Hardware Architecture against Failures Based on Hamming Codes and Triple Modular Redundancy

  • Alan Torres-Alvarado,
  • Luis Alberto Morales-Rosales,
  • Ignacio Algredo-Badillo,
  • Francisco López-Huerta,
  • Mariana Lobato-Báez and
  • Juan Carlos López-Pimentel

13 April 2022

Cryptography has become one of the vital disciplines for information technology such as IoT (Internet Of Things), IIoT (Industrial Internet Of Things), I4.0 (Industry 4.0), and automotive applications. Some fundamental characteristics required for th...

  • Article
  • Open Access
15 Citations
3,184 Views
40 Pages

28 December 2022

In this paper, the conceptualization of a control hardware architecture aimed to the implementation of integer- and fractional-order identification and control algorithms is presented. The proposed hardware architecture combines the capability of imp...

  • Article
  • Open Access
13 Citations
2,868 Views
15 Pages

27 May 2023

The hash function KECCAK integrity algorithm is implemented in cryptographic systems to provide high security for any circuit requiring integrity and protect the transmitted data. Fault attacks, which can extricate confidential data, are one of the m...

  • Article
  • Open Access
24 Citations
10,659 Views
59 Pages

4 August 2016

Wireless Sensor and Actuators Networks (WSANs) constitute one of the most challenging technologies with tremendous socio-economic impact for the next decade. Functionally and energy optimized hardware systems and development tools maybe is the most c...

  • Article
  • Open Access
82 Views
29 Pages

This paper proposes a SIM-compatible hardware coordination architecture for secure radio-frequency (RF)-triggered activation in mobile devices. The proposed concept functions as a passive coordination layer rather than as an additional wireless trans...

  • Article
  • Open Access
40 Citations
4,900 Views
13 Pages

A Low Hardware Consumption Elliptic Curve Cryptographic Architecture over GF(p) in Embedded Application

  • Xianghong Hu,
  • Xin Zheng,
  • Shengshi Zhang,
  • Shuting Cai and
  • Xiaoming Xiong

In this paper, a low hardware consumption design of elliptic curve cryptography (ECC) over GF(p) in embedded applications is proposed. The adder-based architecture is explored to reduce the hardware consumption of performing scalar multiplication (SM...

  • Article
  • Open Access
8 Citations
2,978 Views
10 Pages

31 October 2019

In this paper, a novel internal folded hardware-efficient architecture of multi-level 2-D 9/7 discrete wavelet transform (DWT) is proposed. For multi-level DWT, the unfolded structure is more extensively used compared with the folded structure, becau...

  • Article
  • Open Access
1,889 Views
11 Pages

25 August 2024

Sync word-based frame synchronization is an established method of frame synchronization that is employed in many low-resource applications because of its simplicity, and it involves the attachment of sync words (digital binary sequences) to the frame...

  • Article
  • Open Access
5 Citations
4,864 Views
17 Pages

27 July 2022

The current trend in real-time operating systems involves executing many tasks using a limited hardware platform. Thus, a single processor system has to execute multiple tasks with different priorities in different real-time system (RTS) work modes....

  • Article
  • Open Access
38 Citations
6,933 Views
27 Pages

Implementation and Experimental Application of Industrial IoT Architecture Using Automation and IoT Hardware/Software

  • David Calderón,
  • Francisco Javier Folgado,
  • Isaías González and
  • Antonio José Calderón

18 December 2024

The paradigms of Industry 4.0 and Industrial Internet of Things (IIoT) require functional architectures to deploy and organize hardware and software taking advantage of modern digital technologies in industrial systems. In this sense, a lot of the li...

  • Article
  • Open Access
3 Citations
3,422 Views
20 Pages

4 November 2022

In embedded electronic system applications being developed today, complex datasets are required to be obtained, processed, and communicated. These can be from various sources such as environmental sensors, still image cameras, and video cameras. Once...

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