Microelectronics

We present a generalized electrostatic SWAP gate realized in a chain of two double quantum dots operated in the single-electron regime. Using a minimalist tight-binding model, we derive analytical results and corroborate them with numerical simulations. We exploit the charge anticorrelation arising from Coulomb repulsion and quantify the resulting entanglement generation. We contrast classical and quantum descriptions and show how device geometry and coupling strengths govern entanglement dynamics and gate performance. The results are relevant to cryogenic, CMOS-compatible quantum technologies and suggest a route toward large-scale semiconductor implementations of quantum logic. Finally, we outline a systematic procedure for translating classical electrostatic logic gates into single-electron quantum gates.

The increasing bandwidth demand of artificial-intelligence computing and data-center interconnects has driven silicon photonic optical engines toward higher capacity, compact packaging, and improved scalability. This work presents the packaging design and characterization of a completed 16-channel silicon photonic transmitter module for a 1.6 Tb/s-class optical engine. The module integrates an IMEC-fabricated silicon photonic chip, fiber-array edge-coupling interfaces, wire-bond submounts, PAM4 driver circuits, per-channel MZM heaters, and module-level thermoelectric cooling. A custom submount reduced the highly nonuniform wire-bond distance of 255.98–1788.48 μm to approximately 275.26 μm and provided a simulated packaged-path −3 dB bandwidth of approximately 32 GHz. Fiber-array monitor-port scans showed transverse alignment tolerances of approximately 4–6 μm; after accounting for the nominal 1% monitoring tap and a separately calibrated 4 dB grating-coupler-to-MMF path, the effective packaged input-coupling estimate at 1310 nm was approximately 3.77 dB. All 16 channels were independently verified at 53.125 GBaud PAM4, corresponding to 106.25 Gb/s per lane, and the completed module supports concurrent activation of all lanes. Because the Keysight N1000A optical sampling oscilloscope (Keysight Technologies, Inc., Santa Rosa, CA, USA) accepts one optical input at a time, the eye diagrams and metrics were acquired by sequentially selecting the observed channel and do not constitute a simultaneous 16-channel crosstalk measurement. Across the 16 channels, the measured optical power, OMA, ER, TDECQ, and RLM ranged from −0.09 to 0.30 dBm, 1.141 to 1.267 dBm, 3.037 to 3.055 dB, 3.09 to 3.18 dB, and 0.956 to 0.981, respectively. The measured module-level TEC power was 1.2 W. Using the same nominal 1.6 Tb/s data-rate denominator, the estimated energy consumption is 3.95 pJ/bit for the transmitter electronics excluding the external lasers and TEC and 7.83 pJ/bit when the external laser operating power and measured module-level TEC power are included. These results demonstrate a practical package-level proof of concept for scalable 1.6 Tb/s-class silicon photonic transmitters.

Optical through silicon vias (OTSVs) have been regarded as a promising alternative to conventional (electrical) through silicon vias (TSVs) for the next-generation electro-optic heterogeneous integration. This study systematically examines the influence of fabrication imperfections on the transmission performance in terms of incident light misalignment, via geometry variation, and sidewall roughness. The results demonstrate that over a finite range of beam widths, the insertion loss can be maintained at a relatively low level of less than −0.16 dBm, and this low-loss window broadens with increasing via diameter. Moreover, an increased diameter exhibits greater tolerance to the lateral offset, as for 10 μm, 20 μm, and 30 μm vias, the insertion loss rises to 3 dB at axis misalignments of 5 μm, 10 μm, and 15 μm, respectively. Additionally, smaller-diameter OTSVs are considerably more sensitive to sidewall slope angles than their larger-diameter counterparts. Additionally, minimizing the sidewall roughness is critical for maximizing the coupling efficiency, which suggests that the etch-passivation shift needs to be as quick as possible during the deep reactive ion etch (DRIE) process. With the proposed fabrication approach and comprehensive analysis of fabrication imperfection factors, this study provides essential insights for the development of high-performance OTSVs in advanced 3D optoelectronic integration.