Microelectronics

In MOSFETs, mobility enhancement is a key factor for improving the electrical performance and enabling their use in new applications, such as low-power, digital, and medical applications. This mobility improvement can be technically achieved by using different techniques that exploit the complex behavior of mobility (Coulomb, phonon, and surface roughness mobilities). Previous reviews have primarily focused on two main technologies: the introduction of mechanical stress and crystallographic orientation. Therefore, this review summarizes all key techniques that can enhance mobility, and each of these techniques is linked to a physical origin. Mechanical stress notably affects phonon mobility, whereas silicon thickness and channel impurities mainly affect the Coulomb mobility. Moreover, the dielectric oxide type, heat treatments, surface cleaning, ionic implantation in the oxide, and oxynitrides affect surface roughness mobility. In addition, the crystallographic orientation affects Coulomb, phonon, and surface roughness mobilities. Furthermore, the study of the series resistance engineering also affects the performance. Therefore, the simultaneous use of multiple of these techniques leads to an enhancement of the effective mobility at low, medium, and high effective electric fields, and the combined effect results in a more significant mobility increase. Full article

This paper presents a time-domain closed-loop resistive temperature sensor architecture. The design employs a frequency-locked loop (FLL)-based oscillator as the sensing element, generating a monotonic frequency response to temperature variations. The output frequency is digitized on-chip and converted into a temperature code. Within the oscillator core, a switched-capacitor technique converts frequency to voltage for closed-loop control, reducing charging/discharging voltage swings and significantly lowering dynamic power consumption. The FLL topology enhances frequency stability, minimizes distortion, and suppresses power supply sensitivity. Fabricated in a 180 nm CMOS process with a core area of 0.12 mm², the sensor achieves a peak-to-peak inaccuracy of +1.2 °C/−0.9 °C from −40 °C to 125 °C. Operating at 1 V, the circuit consumes only 10 μW with a resolution of 51 mK within 12 ms. Full article

Multifrequency operation in micromachined ultrasonic transducers, enabled by targeted excitation of specific vibrational modes, has emerged as an attractive approach for achieving tunable performance and configurability, well-suited for advanced ultrasound imaging and therapeutic applications. This paper presents a dual-electrode rectangular piezoelectric micromachined ultrasonic transducer (PMUT) designed for efficient dual-frequency operation through mode-selective actuation. The proposed architecture employs segmented electrodes that are spatially aligned with the strain distributions of two distinct flexural modes, enabling selective excitation of Mode 1 (fundamental) and Mode 3 (higher order) through appropriate electrode actuation. Finite element simulations and impedance analysis were used to guide the electrode configuration and validate the mode-selective behavior. The dual-mode PMUT was fabricated alongside a conventional single-electrode PMUT using identical membrane dimensions and material stack for direct comparison. Comprehensive electrical and underwater acoustic characterization confirmed that the conventional PMUT is limited to single-frequency operation at the fundamental resonance. In contrast, the proposed design achieved a substantial improvement in higher-order performance, with a threefold increase in acoustic pressure at Mode 3 compared to the conventional device. These results demonstrate that mode-aligned electrode segmentation enables efficient dual-mode operation without added fabrication complexity, making the design highly suitable for multifrequency ultrasonic applications such as biomedical imaging and sensing. Full article

Accurate modeling of RF capacitors and inductors is critical for predicting circuit behavior and ensuring operational robustness in high-frequency electronic systems. However, SPICE models are often unavailable from manufacturers, and there is still a lack of reliable methodologies for accurate modeling of such passive components over a wide frequency range. This paper presents a systematic and practical equivalent-circuit modeling methodology for capacitors and inductors based on measured impedance data. The proposed approach partitions the entire frequency range into multiple sub-bands and models each using a combination of a core series RLC network and frequency-dependent parallel RC, RL, and RLC sub-networks. This piecewise construction enables the dominant resistive, inductive, and capacitive behaviors to be independently identified and accurately captured in their respective frequency regions, resulting in an accurate broadband equivalent circuit. The resulting models exhibit excellent agreement with target data, demonstrating the reliability of the method. This work provides a practical and systematic procedure for developing accurate broadband models of RF passive components, with validation demonstrated for capacitors up to 6 GHz and inductors up to 20 GHz. Full article

This work presents a systematic design flow for the fundamental building blocks (namely, the low-noise amplifier and the down-conversion mixer) of an analog receiver for 5G backhauling systems implemented in SiGe BiCMOS technology. The proposed methodology enables the sizing and optimization of receiver blocks up to post-layout simulations, starting from the specified performance requirements. It accounts for both the parasitic effects of active devices and the distributed effects of interconnects. The design flow was applied using STMicroelectronics BiCMOS55X technology to develop low-noise amplifiers and D-band to E-band downconverters capable of covering the 130–150 GHz and 150–165 GHz sub-bands. Preliminary measurement results obtained from both the standalone LNA blocks and the complete receivers are presented and discussed. Full article

Fine-pitch redistribution layers (RDLs) are key enabling technologies for fan-out wafer-level packaging (FOWLP)-based interposers used in chiplet and high-bandwidth memory (HBM) integration. In this study, a CAR-based photolithography process optimized for fine-pitch RDL fabrication was evaluated to realize 2 μm/2 μm line/space (L/S) RDL structures in an FOWLP environment. Key lithographic parameters, including exposure energy, focus offset, and thermal processing conditions, were systematically optimized to establish a stable and reproducible process window. Cross-sectional analysis confirmed the structural integrity of the electroplated RDL features formed under the optimized conditions. To assess functional feasibility, channel-level electrical simulations were performed using JEDEC-defined HBM3 signal assignments. Simulated eye diagrams indicate that the fabricated fine-pitch RDL interconnects are capable of supporting HBM3-class signal transmission with a moderate level of signal integrity. The presence of jitter and noise suggests that further optimization of RDL transmission line impedance is required. Rather than presenting a fully optimized interposer solution, this work provides an engineering-level assessment of lithographic and process constraints associated with implementing 2 μm class RDLs in FOWLP-based interposers, offering practical insight into fine-pitch RDL process window definition for advanced packaging applications. This work uniquely combines systematic CAR-based lithography optimization with cross-sectional structural validation and HBM3-class channel-level simulations to define a practical process window for 2 μm/2 μm RDLs in an FOWLP environment. Full article

The growing dependence on third-party foundries for integrated circuit (IC) fabrication has created major security concerns because of hardware Trojan (HT) insertion risks. Traditional detection methods, including side-channel analysis and golden reference models, face limitations such as sensitivity to noise, high cost, and impracticality for large-scale deployment. This work introduces a machine learning framework for HT detection that eliminates the need for golden references. The framework automatically extracts statistical features from chip data, groups chips into clusters, and uses an internal filtering process to identify the most reliable patterns. These patterns are then used to guide a learning model that can accurately separate Trojan-infected chips from clean ones. Experimental evaluation demonstrates that the proposed method achieves high detection accuracy with zero false negatives, while remaining resilient against adversarial perturbations. These findings indicate that cluster-filtered pseudo-labeling provides a practical and scalable solution for enhancing hardware security in modern IC supply chains. Full article

We demonstrate the fabrication of air gaps in a PECVD SiN interlayer through lateral recess by employing two consecutive plasma etch steps on an AlN/SiN/Al₂O₃ stack. This approach enables the preservation of sub-100 nm openings in Al₂O₃, offering a potential optimization for the GaN-HEMT gate stack in RF applications while retaining low gate foot dimensions. A low-power, SF₆-based plasma etch is introduced, and time-dependent etch profiles reveal the formation of a skirt-like profile. The process exhibits excellent selectivity between SiN and Al₂O₃ etch rates. Furthermore, low-power SF₆ plasma produces a small self-bias voltage, and surface fluorine contamination which can subsequently be eliminated by annealing. Full article

4H-SiC has been studied and applied in power semiconductor devices due to its wider band gap and higher thermal conductivity than those of Si and hence has great potential for power devices operating at high powers and high temperatures. The introduction of the superjunction (SJ) structure for the power MOSFETs enables further reduction in the ON resistance while maintaining the breakdown voltage. In this work, we examined the dc and ac performance of the 1.2 kV 4H-SiC SJ double-implanted MOSFET (DMOSFET) with different configurations of pillars by the Atlas device simulator. The simulation results suggest the step-shape SJ DMOSFET can further reduce the specific ON resistance and the gate-drain capacitance while maintaining the breakdown voltage compared with the optimized conventional SJ DMOSFET. In addition, that the multi-pillar SJ DMOSFET demonstrates better performance than that of the optimized conventional SJ DMOSFET was also verified in this work. Full article

Synthesizable field-programmable gate arrays (FPGAs) have recently gained significant traction due to their low development costs and their ability to adapt to new process technologies. The successful adoption of synthesizable FPGAs requires robust methodologies for estimating the area characteristics of the FPGA tiles in the synthesizable FPGA fabrics. FPGA tile area is used to determine the physical lengths of an FPGA’s routing segments and is therefore crucial to ensuring the accurate benchmarking of newly proposed FPGA architectures. In this work, we present a methodology to estimate the area of synthesizable FPGA tiles across various semiconductor process technologies. The methodology leverages scaling trends in the area of synthesizable FPGA tiles and selected hierarchical blocks to derive scaling factors that can be used to scale the area of synthesizable FPGA tiles across process nodes. The results demonstrate that this methodology achieves a maximum absolute percentage error of less than 10% when scaling the area of synthesizable FPGA tiles across open-sourced 130 nm, 45 nm, 15 nm and 7 nm process nodes. Full article

Quantum biosensors offer a promising route to overcome the sensitivity and specificity limitations of conventional biosensing technologies. Their ability to detect biochemical signals at extremely low concentrations makes them strong candidates for next-generation sensing systems. This paper reviews the current state of quantum biosensors and discusses their future implementation in chip-scale platforms that combine microelectronic and photonic technologies. It covers key quantum biosensing approaches including quantum dots (QDs), and nitrogen-vacancy (NV) centers. This paper also considers their potential compatibility with electronic integrated circuits (EICs), photonic integrated circuits (PICs) and integrated quantum photonic (IQP) systems for future biosensing applications. To our knowledge, this is the first review to systematically connect quantum biosensing technologies with the development of microelectronic and photonic chip-based devices. The goal is to clarify the technological trajectory toward compact, scalable, and high-performance quantum biosensing systems. Full article

This paper presents a new compact and efficient first-order all-pass filter in voltage mode based on a second-generation voltage conveyor, along with two resistors, and a capacitor. This circuit delivers an all-pass response from the low-impedance node and eliminates the need for a voltage buffer in cascading configurations. A thorough non-ideal analysis, accounting for parasitic impedances and the non-ideal gains of the active module, shows negligible effects on the filter performance. Furthermore, a sensitivity analysis with respect to both active and passive components further validates the robustness of the design. The proposed all-pass filter is validated by Cadence PSPICE simulations, utilizing 0.18 µm TSMC CMOS process parameter and ±0.9 V power supply, including Monte Carlo analysis and temperature variations. Additionally, experimental validation is carried out using commercially available IC AD844, showing great consistency between theoretical and experimental results. Resistor-less realization of the proposed filter provides tunability feature. A quadrature sinusoidal oscillator is presented to validate the proposed structure. The introduced circuit provides a simple and effective solution for low-power and compact analog signal processing applications. Full article

The influence of back-gate (BG) bias on the breakdown voltage (BV) of lateral SOI power devices is investigated using TCAD simulations. A reference SOI-LDMOS structure with BVREF = 73.7 V, optimized based on RESURF and charge-sharing principles, is selected as the baseline for analysis. The BV response to BG bias is shown to fall into three distinct regimes: (i) a linear decrease with increasing magnitude of negative BG bias (−65 V ≤ VG2 ≤ −5 V), (ii) an invariant region where the BV reaches its maximum value (−5 V ≤ VG2 ≤ +10 V), and (iii) a sharp reduction under increasing magnitude of positive BG bias (+10 V ≤ VG2 ≤ +65 V). Qualitative analysis of impact ionization and charge distribution confirms that inversion, depletion, and accumulation conditions in the drift region govern these behaviors. Furthermore, parametric variations in drift doping, drift thickness, and buried oxide thickness reveal significant shifts in the optimum design window, with the buried oxide thickness emerging as a critical factor for ensuring robustness of BV under BG bias. These results provide valuable design guidelines for achieving stable high-voltage performance in practical SOI-LDMOS power devices. Full article

Automatic techniques for analog integrated circuit layout design have been proposed in the literature for over four decades. However, as analog design moves into deep nanometer integration nodes, the increasing number of design rules, the influence of layout-dependent effects, congestion, and the impact of parasitic structures constantly challenges existing automatic layout generation techniques and keeps the pressure on for further improvement. At the time of writing, no automatic tool or flow has been established in the industrial environment, resulting in a time-consuming and difficult-to-reuse design process. However, very recently, machine and deep learning techniques started to offer solutions for problems not dealt with in the previous generation of automatic layout tools and are reshaping analog design automation. Therefore, this paper conducts a review of the most recent analog integrated circuit automatic layout techniques powered by machine and deep learning methods, covering placement, routing, and trends on post-layout performance estimation, as well as providing an actual, complete, and comprehensive guide for circuit designers and design automation developers. Full article