Chips, Volume 4, Issue 3 (September 2025) – 10 articles

Memristor crossbar-based neural network systems offer high throughput with low energy consumption. A key advantage of on-chip training in these systems is their ability to mitigate the effects of device variability and faults. This paper presents an efficient on-chip training circuit for memristor crossbar-based multi-layer neural networks. We propose a novel method for storing the product of two analog signals directly in a memristor device, eliminating the need for ADC and DAC converters. Experimental results show that the proposed system is approximately twice as energy efficient and 1.5 times faster than existing memristor-based systems for training multi-layer neural networks. Full article

Artificial intelligence is redefining the computing landscape. Chiplets and heterogeneous integration have become the key strategies for current and next-generation processors. In the wake of Moore’s law slowing down, system integration through advanced packaging has emerged as the leading approach to achieve the highest performance per cost. Overall, the system is converging around substrate which is the main component of packaging. Glass stands out as the superior integration platform for chiplet-based systems. Glass substrates provide unmatched electrical and mechanical properties leading to unprecedented design and integration flexibility at a lower cost than competitive technologies. Three key advantages make glass the platform of choice: the ability to tune material properties, the ability to structure glass, and the feasibility of processing on a large panel scale. This review details the fundamentals of glass processing and manufacturing, innovative integration techniques, and cutting-edge research that collectively position glass substrate as a superior option for the next-generation systems for AI and beyond. Finally, we outline how technology must be shaped in the coming years to drive system scaling. Full article

Bias Temperature Instability (BTI)-induced aging of transistors is a serious concern in modern electronic circuits, yet its effects on the operation of mixed-signal circuits have not been extensively studied. In this work, initially we analyze how BTI-induced aging degradation influences the analog front end of Flash analog-to-digital converters (ADCs). BTI-induced aging leads to substantial increments in the offset voltage of the ADC comparators, which in turn affect their trip point voltage, leading to the alteration of the ADC’s performance characteristics, such as gain, full-scale error and integral nonlinearity. Thus, erroneous responses are generated. Next, we propose a low-cost BTI-induced aging mitigation technique based on a circuit reconfiguration method which periodically alters the average voltage stress on the ADC comparators’ transistors. The proposed method limits the comparators’ offset voltage development, restricting the shift in their trip point voltage. Consequently, the impact of aging on the performance characteristics of the ADC is drastically reduced, and its reliability is improved. According to our simulations, after two years of operation, the gain error is reduced by 95.43%, the full-scale error is reduced by 63.31% and the integral nonlinearity is reduced by 63.00%, with respect to operation without applying the proposed aging mitigation technique. Full article

In recent years, many electronic device industries have shown interest in using artificial intelligence (AI) to quickly estimate package warpage. Machine learning is one of the AI techniques which will give an express prediction on package warpage with the help of several attributes of the data and different algorithms. This study uses a deep learning (DL) model which combines with a deep neural network (DNN) technique and finite element analysis (FEA) to estimate the package warpage of a mobile universal flash storage (UFS) package. Developing a DL model requires a training database from finite element simulation results and a DNN algorithm. The developed DL model accuracy for package warpage is calculated by validating FEA simulation results and experiment data. The error between the DL model prediction and FEA simulation result is less than 7%. This proposed approach can help effectively and efficiently assess package warpage for new product introduction (NPI) with less FEA simulation work and less test vehicle of a real package for warpage measurement and assessment. Full article

Drawing inspiration from biological brains’ energy-efficient information-processing mechanisms, photonic integrated circuits (PICs) have facilitated the development of ultrafast artificial neural networks. This in turn is envisaged to offer potential solutions to the growing demand for artificial intelligence employing machine learning in various domains, from nonlinear optimization and telecommunication to medical diagnosis. In the meantime, silicon photonics has emerged as a mainstream technology for integrated chip-based applications. However, challenges still need to be addressed in scaling it further for broader applications due to the requirement of co-integration of electronic circuitry for control and calibration. Leveraging physics in algorithms and nanoscale materials holds promise for achieving low-power miniaturized chips capable of real-time inference and learning. Against this backdrop, we present the State of the Art in neuromorphic photonic computing, focusing primarily on architecture, weighting mechanisms, photonic neurons, and training, while giving an overall view of recent advancements, challenges, and prospects. We also emphasize and highlight the need for revolutionary hardware innovations to scale up neuromorphic systems while enhancing energy efficiency and performance. Full article

Nowadays, Graphical Processor Units (GPUs) are a great technology to implement Artificial Intelligence (AI) processes; however, a challenge arises when the inclusion of a GPU is not feasible due to the cost, power consumption, or the size of the hardware. This issue is particularly relevant for portable devices, such as laptops or smartphones, where the inclusion of a dedicated GPU is not the best option. One possible solution to that problem is the use of a CPU with AI capabilities, i.e., parallelism and high performance. In particular, RISC-V architecture is considered a good open-source candidate to support such tasks. These capabilities are based on vector operations that, by definition, operate over many elements at the same time, allowing for the execution of SIMD instructions that can be used to implement typical AI routines and procedures. In this context, the main purpose of this proposal is to develop an ASIC Vector Engine RISC-V architecture compliant that implements a minimum set of the Vector Extension capable of the parallel processing of multiple data elements with a single instruction. These instructions operate on vectors and involve addition, multiplication, logical, comparison, and permutation operations. Especially, the multiplication was implemented using the Vedic multiplication algorithm. Contributions include the description of the design, synthesis, and validation processes to develop the ASIC, and a performance comparison between the FPGA implementation and the ASIC using different nanometric technologies, where the best performance of 110 MHz, and the best implementation in terms of silicon area, was achieved by 7 nm technology. Full article

The fast-maturing photonic integration technology is calling for a versatile platform that supports both active and passive functions as well as high scalability through component miniaturization. Indium phosphide (InP) has long been recognized for its ability to deliver a comprehensive suite of photonic components. InP membrane technology has emerged as a next-generation solution that could unite the functional completeness with high scalability. This paper describes recent advancements in the InP-membrane-on-Si (IMOS) platform, which supports high-performance passives, polarization and mode handling, native light sources, amplifiers, modulators and detectors, and novel material integration. Full article

This paper deals with a standard cell-based analog-in-concept pW-power building block as a comparator and a wake-up oscillator. Both topologies, traditionally conceived as an analog building block made by a custom process and supply voltage-dependent design flow, are designed only by using digital gates, enabling them to be automated and fully synthesizable. This further results in supply voltage scalability and regulator-less operation, allowing direct powering by an energy harvester without additional ancillary circuit blocks (such as current and voltage sources). In particular, the circuit similarities in implementing a rail-to-rail dynamic voltage comparator and a relaxation oscillator using only digital gates are discussed. The building blocks previously reported in the literature by the author will be described, and the common root of their design will be highlighted. Full article

A multifunctional circuit with high-pass and low-pass negative group delays can be achieved by simply changing the values of the components in the circuit, without changing the circuit structure. While achieving negative group delay, the circuit also has flat broadband characteristics and lower losses. Theoretical calculations and equation derivation are provided. The experimental circuit was simulated, and the simulation results were essentially consistent with the theoretical results, indicating the feasibility of the experiment. Full article

A new control system implemented with a single-stage DC-DC controller to power an LED headlamp for automotive applications is presented in this work. Daytime running light (DRL), low beam (LB), high beam (HB) and adaptive driving beam (ADB) are typical functions requiring a dedicated LED driver solution to fulfill car maker requirements for front-light applications. Single-stage drivers often exhibit a significant overshoot in LED current during transitions from driving a higher number of LEDs to a lower number. To maintain LED reliability, this current overshoot must remain below the maximum current rating of the LEDs. If the overshoot overcomes this limit, it can cause permanent damage to the LEDs or reduce their lifespan. To preserve LED reliability, a comprehensive system has been proposed to minimize the peak of LED current overshoots, especially during transitions between different operating modes or LED string configurations. A key feature of the proposed system is the implementation of a parallel discharging path to be activated only when the current flowing in the LEDs is higher than a predefined threshold. A prototype incorporating an integrated test chip has been developed to validate this approach. Measurement results and comparison with state-of-the-art solutions available in the market are shown. Furthermore, a critical aspect to be considered is the proper dimensioning of the discharging path. It requires careful considerations about the gate driver capabilities, the discharging resistor values, and the thermal management of the dumping element. For this purpose, an extensive study on how to size the relative components is also presented. Full article