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Chips, Volume 4, Issue 3 (September 2025) – 4 articles

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26 pages, 21618 KiB  
Review
Highly Versatile Photonic Integration Platform on an Indium Phosphide Membrane
by Sander Reniers, Yi Wang, Salim Abdi, Jasper de Graaf, Aleksandr Zozulia, Kevin Williams and Yuqing Jiao
Chips 2025, 4(3), 32; https://doi.org/10.3390/chips4030032 (registering DOI) - 31 Jul 2025
Abstract
The fast-maturing photonic integration technology is calling for a versatile platform that supports both active and passive functions as well as high scalability through component miniaturization. Indium phosphide (InP) has long been recognized for its ability to deliver a comprehensive suite of photonic [...] Read more.
The fast-maturing photonic integration technology is calling for a versatile platform that supports both active and passive functions as well as high scalability through component miniaturization. Indium phosphide (InP) has long been recognized for its ability to deliver a comprehensive suite of photonic components. InP membrane technology has emerged as a next-generation solution that could unite the functional completeness with high scalability. This paper describes recent advancements in the InP-membrane-on-Si (IMOS) platform, which supports high-performance passives, polarization and mode handling, native light sources, amplifiers, modulators and detectors, and novel material integration. Full article
(This article belongs to the Special Issue Silicon Photonic Integrated Circuits: Advancements and Challenges)
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12 pages, 1365 KiB  
Article
On Standard Cell-Based Design for Dynamic Voltage Comparators and Relaxation Oscillators
by Orazio Aiello
Chips 2025, 4(3), 31; https://doi.org/10.3390/chips4030031 - 30 Jul 2025
Viewed by 55
Abstract
This paper deals with a standard cell-based analog-in-concept pW-power building block as a comparator and a wake-up oscillator. Both topologies, traditionally conceived as an analog building block made by a custom process and supply voltage-dependent design flow, are designed only by using digital [...] Read more.
This paper deals with a standard cell-based analog-in-concept pW-power building block as a comparator and a wake-up oscillator. Both topologies, traditionally conceived as an analog building block made by a custom process and supply voltage-dependent design flow, are designed only by using digital gates, enabling them to be automated and fully synthesizable. This further results in supply voltage scalability and regulator-less operation, allowing direct powering by an energy harvester without additional ancillary circuit blocks (such as current and voltage sources). In particular, the circuit similarities in implementing a rail-to-rail dynamic voltage comparator and a relaxation oscillator using only digital gates are discussed. The building blocks previously reported in the literature by the author will be described, and the common root of their design will be highlighted. Full article
(This article belongs to the Special Issue IC Design Techniques for Power/Energy-Constrained Applications)
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16 pages, 1503 KiB  
Article
A Low-Loss Circuit with High-Pass Low-Pass Broadband Flat Negative Group Delay Characteristics
by Enze Shi, Aixia Yuan, Junzheng Liu, Niannan Chang and Xinqi Guo
Chips 2025, 4(3), 30; https://doi.org/10.3390/chips4030030 - 7 Jul 2025
Viewed by 202
Abstract
A multifunctional circuit with high-pass and low-pass negative group delays can be achieved by simply changing the values of the components in the circuit, without changing the circuit structure. While achieving negative group delay, the circuit also has flat broadband characteristics and lower [...] Read more.
A multifunctional circuit with high-pass and low-pass negative group delays can be achieved by simply changing the values of the components in the circuit, without changing the circuit structure. While achieving negative group delay, the circuit also has flat broadband characteristics and lower losses. Theoretical calculations and equation derivation are provided. The experimental circuit was simulated, and the simulation results were essentially consistent with the theoretical results, indicating the feasibility of the experiment. Full article
(This article belongs to the Special Issue Advances in Power Management Integrated Circuits (PMICs))
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14 pages, 4544 KiB  
Article
Intelligent DC-DC Controller for Glare-Free Front-Light LED Headlamp
by Paolo Lorenzi, Roberto Penzo, Enrico Tonazzo, Edoardo Bezzati, Maurizio Galvano and Fausto Borghetti
Chips 2025, 4(3), 29; https://doi.org/10.3390/chips4030029 - 27 Jun 2025
Viewed by 259
Abstract
A new control system implemented with a single-stage DC-DC controller to power an LED headlamp for automotive applications is presented in this work. Daytime running light (DRL), low beam (LB), high beam (HB) and adaptive driving beam (ADB) are typical functions requiring a [...] Read more.
A new control system implemented with a single-stage DC-DC controller to power an LED headlamp for automotive applications is presented in this work. Daytime running light (DRL), low beam (LB), high beam (HB) and adaptive driving beam (ADB) are typical functions requiring a dedicated LED driver solution to fulfill car maker requirements for front-light applications. Single-stage drivers often exhibit a significant overshoot in LED current during transitions from driving a higher number of LEDs to a lower number. To maintain LED reliability, this current overshoot must remain below the maximum current rating of the LEDs. If the overshoot overcomes this limit, it can cause permanent damage to the LEDs or reduce their lifespan. To preserve LED reliability, a comprehensive system has been proposed to minimize the peak of LED current overshoots, especially during transitions between different operating modes or LED string configurations. A key feature of the proposed system is the implementation of a parallel discharging path to be activated only when the current flowing in the LEDs is higher than a predefined threshold. A prototype incorporating an integrated test chip has been developed to validate this approach. Measurement results and comparison with state-of-the-art solutions available in the market are shown. Furthermore, a critical aspect to be considered is the proper dimensioning of the discharging path. It requires careful considerations about the gate driver capabilities, the discharging resistor values, and the thermal management of the dumping element. For this purpose, an extensive study on how to size the relative components is also presented. Full article
(This article belongs to the Special Issue New Research in Microelectronics and Electronics)
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