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Chips, Volume 4, Issue 2 (June 2025) – 9 articles

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14 pages, 6551 KiB  
Article
Design Analysis of a Modified Current-Reuse Low-Power Wideband Single-Ended CMOS LNA
by Farshad Shirani Bidabadi, Mahalingam Nagarajan, Thangarasu Bharatha Kumar and Yeo Kiat Seng
Chips 2025, 4(2), 21; https://doi.org/10.3390/chips4020021 (registering DOI) - 6 May 2025
Abstract
This paper presents the design analysis of a low-power wideband single-ended CMOS low-noise amplifier (LNA). The proposed topology is based on a modified current- reuse circuit, in which two-stage common-source (CS) amplifiers consume the same DC current and are isolated from each other [...] Read more.
This paper presents the design analysis of a low-power wideband single-ended CMOS low-noise amplifier (LNA). The proposed topology is based on a modified current- reuse circuit, in which two-stage common-source (CS) amplifiers consume the same DC current and are isolated from each other by large MIMCAPs, which results in good performance with low power consumption. The proposed circuit achieves a bandwidth of 2.5 GHz, suitable for several wireless communication standards such as GSM, WLAN, and Bluetooth. In the first stage, a current-reuse circuit with shunt feedback is used to satisfy input impedance matching and signal amplification with minimal noise injection. A common source (CS) with a source follower circuit forms the second stage to improve the noise figure (NF), harmonic distortion, and output impedance matching. The proposed LNA is designed in 65 nm CMOS technology and covers a frequency range of 0.17–2.68 GHz. The proposed LNA achieves a maximum gain of 17.24 dB, a minimum NF of 2.67 dB, a maximum IIP3 of −14.9 dBm, and input and output return losses of less than −10 dB. The power consumption of the proposed LNA is 3.52 mW from a 1 V power supply, and the core area is 0.3 mm2. Full article
(This article belongs to the Special Issue IC Design Techniques for Power/Energy-Constrained Applications)
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15 pages, 12762 KiB  
Review
Advanced Doherty Power Amplifier Architectures for 5G Handset Applications: A Comprehensive Review of Linearity, Back-Off Efficiency, Bandwidth, and Thermal Management
by Shihai He and Huan Chen
Chips 2025, 4(2), 20; https://doi.org/10.3390/chips4020020 - 6 May 2025
Abstract
This paper presents a comprehensive review of GaAs HBT-based Doherty power amplifiers (DPAs) targeting 5G New Radio (NR) handset applications. Focusing on the critical challenges of linearity enhancement, back-off efficiency improvement, bandwidth extension under low-voltage (3.4 V) operation, and chip thermal management, the [...] Read more.
This paper presents a comprehensive review of GaAs HBT-based Doherty power amplifiers (DPAs) targeting 5G New Radio (NR) handset applications. Focusing on the critical challenges of linearity enhancement, back-off efficiency improvement, bandwidth extension under low-voltage (3.4 V) operation, and chip thermal management, the authors analyze state-of-the-art DPAs published in recent years. Key innovations including dynamic power division technique, third order intermodulation (IM3) cancellation technology, and compact output combiners are comparatively studied. Using 5G NR signals, the critical performance of the latest reported PA such as maximum linear power, back-off efficiency, bandwidth, and operating voltage are quantitatively investigated. The measurement results demonstrated that the best performance in recent DPAs achieved high linear power of 31 dBm with 34% PAE and 30 dBm with 31% PAE at the N78 and N77 bands, respectively. The corresponding adjacent channel leakage ratios (ACLRs) were lower than −36.5 dBc without digital pre-distortion (DPD). This review provides a comprehensive understanding of the latest advancements and future directions in highly efficient and linear DPA designs for 5G handset front-end modules. Full article
(This article belongs to the Special Issue IC Design Techniques for Power/Energy-Constrained Applications)
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30 pages, 2809 KiB  
Review
A Survey on Computing-in-Memory (CiM) and Emerging Nonvolatile Memory (NVM) Simulators
by John Taylor Maurer, Ahmed Mamdouh Mohamed Ahmed, Parsa Khorrami, Sabrina Hassan Moon and Dayane Alfenas Reis
Chips 2025, 4(2), 19; https://doi.org/10.3390/chips4020019 - 3 May 2025
Viewed by 90
Abstract
Modern computer applications have become highly data-intensive, giving rise to an increase in data traffic between the processor and memory units. Computing-in-Memory (CiM) has shown great promise as a solution to this aptly named von Neumann bottleneck problem by enabling computation within the [...] Read more.
Modern computer applications have become highly data-intensive, giving rise to an increase in data traffic between the processor and memory units. Computing-in-Memory (CiM) has shown great promise as a solution to this aptly named von Neumann bottleneck problem by enabling computation within the memory unit and thus reducing data traffic. Many simulation tools in the literature have been proposed to enable the design space exploration (DSE) of these novel computer architectures as researchers are in need of these tools to test their designs prior to fabrication. This paper presents a collection of classical nonvolatile memory (NVM) and CiM simulation tools to showcase their capabilities, as presented in their respective analyses. We provide an in-depth overview of DSE, emerging NVM device technologies, and popular CiM architectures. We organize the simulation tools by design-level scopes with respect to their focus on the devices, circuits, architectures, systems/algorithms, and applications they support. We conclude this work by identifying the gaps within the simulation space. Full article
(This article belongs to the Special Issue Magnetoresistive Random-Access Memory (MRAM): Present and Future)
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30 pages, 8304 KiB  
Article
Design of a Linear Floating Active Resistor with Low Temperature Coefficient
by Yu Liu and Pak Kwong Chan
Chips 2025, 4(2), 18; https://doi.org/10.3390/chips4020018 - 14 Apr 2025
Viewed by 184
Abstract
This paper presents the design and implementation of a linear, stable, low-power and PVT insensitive floating active resistor, which is realized using TSMC 40 nm CMOS process technology. By incorporating the automatic tuning circuit, this work has achieved improved performance metrics, which include [...] Read more.
This paper presents the design and implementation of a linear, stable, low-power and PVT insensitive floating active resistor, which is realized using TSMC 40 nm CMOS process technology. By incorporating the automatic tuning circuit, this work has achieved improved performance metrics, which include low process sensitivity, reduced temperature coefficient, and good linearity. Monte Carlo (MC) simulations are conducted to evaluate the active resistor’s performance under variations in temperature, process, and supply voltage. The proposed design has demonstrated an average resistance process sensitivity of 0.64%, a temperature coefficient (T.C.) of 57 ppm/°C across −25 °C to 85 °C, and a linearity figure of merit (FOM) of 2.4 × 10−2 V−1 with a resistance close to MΩ level. It can achieve a linear resistance tuning range of 430.5 kΩ to 1.714 MΩ. The typical power consumption of a single active resistor is 0.25 µW at 2.1 V bootstrapped supply voltage through a Dickson charge pump (DCP) circuit using a DC input of 1 V. These results have confirmed that the proposed active resistor can function as a robust and efficient resistor for low-voltage integrated circuits and systems. Full article
(This article belongs to the Special Issue IC Design Techniques for Power/Energy-Constrained Applications)
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22 pages, 3837 KiB  
Article
TDM Test Scheduler and TAM Optimization Toolkit: An Integrated Framework for Test Processes of DVFS-Based SoCs with Multiple Voltage Islands
by Fotios Vartziotis
Chips 2025, 4(2), 17; https://doi.org/10.3390/chips4020017 - 11 Apr 2025
Viewed by 136
Abstract
The TDM Test Scheduler and TAM Optimization Toolkit is a novel, integrated, and user-friendly solution designed for engineers, researchers, and instructors working in the field of manufacturing tests. It effectively supports test planning for multicore, DVFS-based SoCs with multiple voltage islands, offering optimized [...] Read more.
The TDM Test Scheduler and TAM Optimization Toolkit is a novel, integrated, and user-friendly solution designed for engineers, researchers, and instructors working in the field of manufacturing tests. It effectively supports test planning for multicore, DVFS-based SoCs with multiple voltage islands, offering optimized solutions that minimize test costs while ensuring compliance with power and thermal constraints. The toolkit provides (a) a high-level language (HLL) for the intuitive representation of test processes, along with a smart syntax and logic checker for verification; (b) an advanced compilation and execution environment featuring two computationally efficient Time-Division Multiplexing (TDM)-specialized solvers; (c) a sophisticated Test Access Mechanism (TAM) optimization framework; (d) a customized visualization environment capable of depicting and animating power- and thermal-annotated test schedules; (e) a versatile testbed for educational and research activities. Full article
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11 pages, 2173 KiB  
Article
Optical Frequency Comb-Based 256-QAM WDM Coherent System with Digital Signal Processing Algorithm
by Babar Ali, Ghulam Murtaza, Hafiz Muhammad Bilal, Tariq Mahmood, Muhammad Rashid and Zaib Ullah
Chips 2025, 4(2), 16; https://doi.org/10.3390/chips4020016 - 10 Apr 2025
Viewed by 235
Abstract
This work presents a cost-effective optical frequency comb generator (CEOFCG) solution for generating multiple, equally spaced carriers in wavelength-division-multiplexing coherent optical fiber communication systems (WDM-COFCS). It enables the replacement of multiple laser sources with a single continuous-wave laser, eliminating the need for additional [...] Read more.
This work presents a cost-effective optical frequency comb generator (CEOFCG) solution for generating multiple, equally spaced carriers in wavelength-division-multiplexing coherent optical fiber communication systems (WDM-COFCS). It enables the replacement of multiple laser sources with a single continuous-wave laser, eliminating the need for additional amplification and filtering setups. The CEOFCG provides stable multicarrier spacing, broad phase coherence, and compatibility with advanced modulation formats, enhancing the performance of WDM-COFCS. Digital signal processing (DSP) techniques, including digital filtering, detection, and impairment compensation, contribute to high transmission and spectral efficiency (SE). The results demonstrate the potential of CEOFCG in achieving cost reduction, complexity reduction, high SE, and optimal utilization of optical fiber bandwidth, particularly in higher-order QAM-based COFCS. Full article
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29 pages, 3607 KiB  
Article
The Quest for Efficient ASCON Implementations: A Comprehensive Review of Implementation Strategies and Challenges
by Mattia Mirigaldi, Valeria Piscopo, Maurizio Martina and Guido Masera
Chips 2025, 4(2), 15; https://doi.org/10.3390/chips4020015 - 7 Apr 2025
Viewed by 344
Abstract
The rapid growth of the Internet of Things (IoT) has significantly expanded the deployment of resource-constrained devices, introducing new security and privacy challenges. To address these concerns, the National Institute of Standards and Technology (NIST) concluded a multi-year effort by announcing ASCON as [...] Read more.
The rapid growth of the Internet of Things (IoT) has significantly expanded the deployment of resource-constrained devices, introducing new security and privacy challenges. To address these concerns, the National Institute of Standards and Technology (NIST) concluded a multi-year effort by announcing ASCON as the new lightweight cryptography standard in 2023. ASCON’s cipher suite includes both Authenticated Encryption with Associated Data (AEAD) and hashing functions, ensuring authenticity, confidentiality, and broad applicability. Since its standardization, there has been a significant research effort focused on enhancing ASCON’s performance under diverse application constraints as well as assessing its vulnerability to advanced side-channel attacks. This study offers a comprehensive overview of current ASCON hardware implementations on FPGA and ASIC platforms, examining key design trade-offs. Additionally, it examines the latest side-channel attacks on ASCON were examined. These attacks exploited weaknesses in the hardware implementations rather than in the algorithm itself. Being highly efficient, they could breach both unprotected and protected implementations. This survey also reviews the proposed countermeasures against these powerful attacks and analyzes how their associated overhead conflicts with the performance demands of real-world ASCON applications. The synthesis of these findings offers clear guidelines for designers seeking to implement ASCON. At the same time, areas requiring further investigation are identified. As ASCON sees ever more widespread deployment, this review serves as a reference for understanding the current state of research and guiding future developments toward efficient and secure implementations. Full article
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18 pages, 481 KiB  
Article
Adaptive and Passage-Based Fault-Tolerant Routing Methods for Three-Dimensional Mesh NoCs
by Yota Kurokawa and Masaru Fukushi
Chips 2025, 4(2), 14; https://doi.org/10.3390/chips4020014 - 6 Apr 2025
Viewed by 165
Abstract
This paper proposes novel two fault-tolerant routing methods for a 3D mesh network-on-chip (NoC). The existing method proposed by Boppana et al. combines two routing methods, minimal fully adaptive routing and fault-tolerant routing, for faulty region detouring. However, in the latter fault-tolerant routing, [...] Read more.
This paper proposes novel two fault-tolerant routing methods for a 3D mesh network-on-chip (NoC). The existing method proposed by Boppana et al. combines two routing methods, minimal fully adaptive routing and fault-tolerant routing, for faulty region detouring. However, in the latter fault-tolerant routing, a detour direction is statically defined for each faulty region. Due to the long detour path and the use of eight virtual channels, this method has the problems of high communication latency and a large hardware overhead. To solve these problems, the first proposed method allows adaptive detours for faulty regions, and the second proposed method allows the passage of them. The simulation results show that, compared with the existing method, the second proposed method enables us to reduce the latency by about 30% and improve the throughput by about 3.1% with half of the virtual channels. Full article
(This article belongs to the Topic Theory and Applications of High Performance Computing)
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16 pages, 1318 KiB  
Article
Optimised Extension of an Ultra-Low-Power RISC-V Processor to Support Lightweight Neural Network Models
by Qiankun Liu and Sam Amiri
Chips 2025, 4(2), 13; https://doi.org/10.3390/chips4020013 - 3 Apr 2025
Viewed by 361
Abstract
With the increasing demand for efficient deep learning models in resource-constrained environments, Binary Neural Networks (BNNs) have emerged as a promising solution due to their ability to significantly reduce computational complexity while maintaining accuracy. Their integration into embedded and edge computing systems is [...] Read more.
With the increasing demand for efficient deep learning models in resource-constrained environments, Binary Neural Networks (BNNs) have emerged as a promising solution due to their ability to significantly reduce computational complexity while maintaining accuracy. Their integration into embedded and edge computing systems is essential for enabling real-time AI applications in areas such as autonomous systems, industrial automation, and intelligent security. Deploying BNN on FPGA using RISC-V, rather than directly deploying the model on FPGA, sacrifices detection speed but, in general, reduces power consumption and on-chip resource usage. The AI-extended RISC-V core is capable of handling tasks beyond BNN inference, providing greater flexibility. This work utilises the lightweight Zero-Riscy core to deploy a BNN on FPGA. Three custom instructions are proposed for convolution, pooling, and fully connected layers, integrating XNOR, POPCOUNT, and threshold operations. This reduces the number of instructions required per task, thereby decreasing the frequency of interactions between Zero-Riscy and the instruction memory. The proposed solution is evaluated on two case studies: MNIST dataset classification and an intrusion detection system (IDS) for in-vehicle networks. The results show that for MNIST inference, the hardware resources required are only 9% of those used by state-of-the-art solutions, though with a slight reduction in speed. For IDS-based inference, power consumption is reduced to just 13% of the original, while resource usage is only 20% of the original. Although some speed is sacrificed, the system still meets real-time monitoring requirements. Full article
(This article belongs to the Special Issue IC Design Techniques for Power/Energy-Constrained Applications)
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