On Standard Cell-Based Design for Dynamic Voltage Comparators and Relaxation Oscillators

Abstract

This paper deals with a standard cell-based analog-in-concept pW-power building block as a comparator and a wake-up oscillator. Both topologies, traditionally conceived as an analog building block made by a custom process and supply voltage-dependent design flow, are designed only by using digital gates, enabling them to be automated and fully synthesizable. This further results in supply voltage scalability and regulator-less operation, allowing direct powering by an energy harvester without additional ancillary circuit blocks (such as current and voltage sources). In particular, the circuit similarities in implementing a rail-to-rail dynamic voltage comparator and a relaxation oscillator using only digital gates are discussed. The building blocks previously reported in the literature by the author will be described, and the common root of their design will be highlighted.

1. Introduction

To meet the strict power and cost restrictions of sensor nodes for the Internet of Things (IoT), Integrated Circuit (ICs) approaches that facilitate dependable operation over a wide variety of supply voltages are essential [1,2,3,4,5,6,7]. Most analog building blocks are unsuitable for ultra-low-power systems, such as sensor nodes and energy-harvested systems, as their supply voltage is typically 0.6 V or higher. In this framework, the need to increase design automation, reduce human design effort, and thereby reduce costs has increased the relevance of highly digital, fully synthesizable building blocks that perform analog functions. On this basis, circuit solutions based on digital standard cells that exploit design/technology portability and operate under aggressively scaled supply voltage conditions have been explored [8,9].

Among the several digital-based circuit solutions of traditionally analog building blocks already explored in the literature, the present paper will focus on rail-to-rail dynamic voltage comparators (RRDVCs) and relaxation oscillators. The first ones, the comparators, are essential building blocks for the functions, speed, and power consumption of basic circuits such as analog-to-digital converters and linear voltage regulators (i.e., LDOs) used in smart systems to control power, utilize sensors, or communicate with the environment [10,11,12,13,14,15,16,17,18]. The latter, relaxation oscillators, are generally nonlinear oscillator circuits used to generate a repeating, non-sinusoidal output signal, such as a square or triangle wave. The Hz-range oscillation frequencies of such oscillators can lead to Hz-range duty-cycled operation mode in sensor nodes, which is the main method for saving power [19,20,21,22,23,24,25,26,27,28,29,30,31]. The paper shows how, from the understanding of fully synthesizable RR-DVC (FS-RRDVCs), it is possible to conceive fully synthesizable relaxation oscillators (FS-RelOsc) that can work with a supply voltage as low as 0.3 V, enabling the creation of an unregulated and reference-less IC building block highly suitable for any IoT sensor node and any electronic system with tight energy constraints.

The paper is structured as follows: firstly, different versions of fully synthesizable DVCs are presented in Section 2, where their working principle is briefly described, and a few basic versions are shown. Then, on this basis, how to move from an FS RRDVC to a fully synthesizable relaxation oscillator (FS-RelOsc) by adding a timing capacitor and a minimum gates refinement is discussed in Section 3. Section 4 discusses how dynamic leakage suppression logic offers a straightforward possibility to make a relaxation oscillator suitable as a wake-up oscillator with negligible supply voltage dependence. The conclusions are drawn in Section 4.

2. Fully Synthesizable Rail-to-Rail Dynamic Voltage Comparator

Dynamic voltage comparators (DVCs) are key parts of analog-to-digital converters (ADCs), sensor interfaces for gathering physical data and event monitoring, and sensor nodes. Despite the effort put into implementing DVCs, they often request manual or custom layouts and designs that are kept separate from the digital standard cell-based modules, which makes block design and system integration more challenging. In this context, the first fully synthesizable DVC circuit example was reported in Figure 1a, first introduced in [10,11,12,13,14], and further refined in [15,16,17,18]. This meant that for the first time, the RRDVC shown in Figure 1c was used as a rail-to-rail solution. This latter merges the prior NAND-based topology (Figure 1a) with its dual, NOR-based one (Figure 1b) to obtain a rail-to-rail solution. The RRDVC is incredibly tiny and has an entirely synthesizable design flow. The place and route (PnR) of the layout can be automated by starting with a structural Verilog description, as it is wholly based on CMOS digital standard cells.

To describe how the fully synthesizable RRDVC operates, only the bottom portion of the circuit, which is based on NAND3 input gates, is shown in Figure 2. Specifically, the first DVC [10] is shown in Figure 2a, which includes an input stage with two NAND3 gates and an SR latch. Figure 2b (dotted frames) reports the NAND3 input gate design. The top inputs A1 and A2 of the NAND3 are linked to the gates of the top nMOS devices (MN1_1 and MN1_2), and these are connected to the non-inverting ($v_{INp}$) and inverting ($v_{INm}$) analog inputs of the DVC. The center input B1 (B2), which is cross-fed from the OUT2 (OUT1) output, drives the NMOS transistor MN2_1 (MN2_2). The sample clock is connected to the bottom inputs C1 and C2, as shown in Figure 1b,c. The SR latch’s set (S) and reset (R) inputs are also connected to the outputs OUT1 and OUT2 via inverter gates. The latter keeps the prior comparator’s output when the sampling clock is low, or the comparator is not used. In this example, the cross-coupled feedback connection activates transistors MN2_1, MN2_2, and MP3_1 and MP3_2 after pre-charging OUT1 and OUT2 to $V_{DD}$. When transistors MN3_1 and MN3_2 are turned on during the low-to-high clock transition, the pull-down networks of the two NAND gates are enabled because MN2_1 and MN2_2 are still on immediately after the rising clock edge, as OUT1 and OUT2 are still at $V_{DD}$. At the same time, transistors MP3_1 and MP3_2 are turned off, which prevents the precharge of OUT1 and OUT2. If the input differential voltage $v_{diff}=v_{INp}-v_{INm}$ is positive, transistor MN1_1 would sequentially pull down the output OUT1 faster than transistor OUT2 because its gate voltage is lower than that of transistor MN1_2. As a result, OUT1 achieves the threshold voltage $V_{THn}$ for NMOS transistors before OUT2. In this way, MN2_2 is turned off, and a positive feedback loop is initiated, driving the OUT1 and OUT2 latches to be low and high, respectively. The reverse considerations apply if the input $v_{diff}$ is negative. In both cases, the polarity of the analog input differential voltage around the rising clock edge sets the digital output, which latches via the SR latch, as one might anticipate from a DVC. The DVC mentioned above causes the drain currents of MP1_1 and MP1_2, which are also controlled by the analog inputs, to resist the drawing down of OUT1 and OUT2.

The OUT1 and OUT2 falling transients, which are naturally determined by MN1_1 and MN1_2 (see above), are explicitly opposed to these currents. This behavior is negligible when the common-mode input voltage is close to $V_{DD}$ because MP1_1 and MP1_2 are not functioning, which results in a very low current. However, as the common-mode input voltage decreases, the source–gate voltage of MP1_1 and MP1_2 increases, along with their corresponding currents. The currents buried by MN1_1 and MN1_2 drop as the common-mode voltage drops, and the latter subtracts from these currents to pull down OUT1 and OUT2 (see the details of currents involved in the switching of the OUT1 node in Figure 2b). OUT1 and OUT2 must remain at $V_{DD}$ regardless of inputs when common-mode voltages are too low because MP1_1 and MP1_2 currents outweigh MN1_1 and MN1_2 currents (i.e., the comparator stops operating correctly). According to simulations, a value $V_N$, roughly equivalent to $V_{DD}$/2, constrains the common-mode range (CMR) to a lesser extent.

On this basis, the complementary NOR3 version in Figure 1b is combined with the NAND3 input stage in Figure 1a. Double CMR limitations are present throughout the circuit. The NOR3 gates only function as a comparator properly when the common-mode input voltage $V_P$ is close enough to the ground, as shown when the preceding study is repeated using NOR gates rather than NAND gates. The comparator stops working correctly when it surpasses a maximum Image value, which is again found to be around $V_{DD}$/2. The corresponding NOR3-based DVC fails when $V_P$ is exceeded because OUT1 and OUT2 cannot be addressed appropriately. The whole circuit produces a DVC with rail-to-rail CMR while retaining full synthesizability if the condition $V_P>V_N$ is satisfied.

Therefore, a DVC that uses rail-to-rail CMR while retaining full synthesizability may be produced by combining the input stages of a NAND3-based DVC (Figure 1a and Figure 2a) with its complementary form, a NOR3-based DVC (Figure 1b). A dual-input SR latch is driven by the cross-coupled NAND3 and NOR3 outputs, as seen in the truth table in Figure 1c. ORing is used to combine the two “set” inputs (S1 and S2) and the two “reset” inputs (R1 and R2). Therefore, the appropriate operation of the other input stage (NOR or NAND) is sufficient to operate the SR latch correctly if the signals originating from that stage are stuck at their pre-charge level, signifying that it cannot generate acceptable outputs. As previously mentioned, the dual-input SR latch stores the value the functioning input stage provides while remaining indifferent to the other’s output. According to the CMR, this ensures appropriate functioning toward $V_{DD}$. Opposing concerns come into play when the common-mode input is nearer the ground than $V_{DD}$. In this case, even if the outputs of the NAND3 gates are stalled at $V_{DD}$, the SR latch still generates the correct output. The intended outputs, S2 and R2, are produced by the NOR3 gates operating as expected.

3. Digital-Gate Design: From Dynamic Voltage Comparators to Relaxation Oscillators

The DVC clock enables a pre-charge phase that allows a new valuation phase starting with a balanced current flowing into the two input branches. This is needed to detect differential-mode input voltage. Assuming the voltages of the two inputs at the opposite side of the input dynamic range (i.e., VDD and 0), the precharge/restart phase is no longer necessary. Under this condition, (i) the complementary outputs of the comparator can be shortened directly to the input nodes (see green line in Figure 3a), creating an oscillator due to the propagation of a commutating signal across the parasitic between input and output; (ii) the clock terminal is redundant so that the 3-input NANDs can be replaced with 2-input NANDs.

In Figure 3a, in addition to the above-mentioned circuit modifications, an additional timing capacitor (in red between nodes OUT_1 and OUT_2) is placed among the former output nodes of the DVC. This allows for a modicum of control over the oscillation frequency, which is otherwise only related to parasitics. In fact, the presence of the timing capacitor defines a relaxation oscillator whose frequency is linearly dependent on such a timing capacitor. Moreover, the outputs of two 2-input NANDs (see red NANDs in Figure 3a) have been tied to the terminal of such a timing capacitor. Such NANDs have two roles: (a) they define the common mode of the two terminals; (b) the respective terminal ENABLE allows the oscillation activity to be stopped (whenever it is tied to the ground).

In brief, a fully synthesizable relaxation oscillator (FS-RelOsc) has been implemented by connecting the outputs of a fully synthesizable DVC to their respective inputs, removing redundant clock inputs, and adding a timing capacitor and two NAND gates. These changes are shown in Figure 3a. In Figure 3b, the gates of Figure 3a are spatially rearranged, but the circuit is the same as that in Figure 3a. To facilitate the understanding of how Figure 3a,b are the same, the feedback loop in the first figure is reported in the latter one highlighted in green.

It is worth mentioning that the digital gates considered so far do not have special requirements. Thus, they can be implemented using the standard cells available in any process design kit for the digital design flow. In other words, building digital gates does not require any customization to allow the DVC and the relaxation oscillator to work.

The sizing of the gates is possible by choosing a different strength among the available cells of a given process design kit. For instance, increasing the strength of the input gate of the DVC (both NANDs, NORs, and rail-to-rail versions) implies an offset reduction, according to Pelgrom’s law [31]. On the contrary, a minimum strength is suitable for the relaxation oscillator.

Starting from the DVC mentioned above, other solutions have been proposed, mainly with the target of reducing the delay [20,21,22,23,24,25,26,27]. These solutions have been used as the building blocks of analog-to-digital converters [32,33,34,35,36]. Regarding the relaxation oscillator, few solutions have been proposed [28,29,30]. Notice that the digital nature of both circuits enables them to operate even without a supply voltage regulator, over a wide supply voltage range, and under aggressively scaled supply voltage conditions. The supply voltage scaling worsens the offset in RRDVC and increases the delay, respectively, lowering the frequency oscillation of the relaxation oscillator.

The standard cell implementation of the oscillator with conventional CMOS is affected by jitter, just as a ring oscillator is. To exploit, at best, the proposed relaxation oscillator’s simplicity and supply voltage scalability, it needs to rely on another logic implementation (i.e., the DLS described in the following Section) that makes it suitable as a wake-up (Hz-range) oscillator.

4. A Wake-Up Relaxation Oscillator Made with DLS Gates

An alternative and more effective way to slow the oscillation frequency is to use the dynamic leakage suppression (DLS) logic [37] that is highly suited to wake-up oscillator design. The DLS (first known as ultra-low-power [38]) logic style significantly reduces the standby power of digital standard cells at the expense of reduced speed [39,40,41,42,43,44,45,46,47,48,49]. The standby power is usually two to three orders of magnitude lower than the normal transistor leakage (i.e., at zero gate–source voltage), and the gate delay is usually in the millisecond range. The DLS pull-up (MPU) and pull-down (MPD) transistors are identical to those found in a typical CMOS inverter (the same observations apply to any other standard cell) in the DLS inverter gate, which is shown in Figure 4. Furthermore, DLS gates consist of a PMOS footer MP and an NMOS header transistor MN, both of which have a feedback loop created by driving their gate terminals with the cell output. As will be covered later, this loop causes a notable decrease in standby current and hysteretic behavior.

Figure 4 illustrates how a low input disables MPD, causing the output to be high, which in turn disables the PMOS footer MP, thereby reducing the standby current drawn by the DLS logic gates. The voltage $V_x$ of their common node $X$ settles to a value that is around $V_{DD}/2$ since the drain currents of MPD and MP are equal [37,38]. This results in super-cutoff operation and a negative gate–source (source–gate) voltage in MPD (MP) of about $-V_{DD}/2$ [37,38]. Dual considerations apply to a large input, resulting in super-cutoff operation in MN and MPU. The standby current of DLS logic gates is two to three orders of magnitude lower than the normal leakage current because it is located in the super-cutoff area. The inverter gate standby current in 180 nm CMOS is 10 fA/gate [37,38], which is several hundred times lower than the normal leakage. It is even lower for other logic gates that use stacked transistors.

Thus, DLS logic is highly suitable for wake-up oscillators. In fact, Hz-range functioning with small on-chip capacitors and, hence, little area is made possible by the very modest current (pA range) that DLS gates give to the load. The DLS logic characteristics can be exploited to implement an Hz-range FS-RelOsc. In particular, the relaxation oscillator in Figure 3b is further reported in Figure 5 by DLS logic implementation and an additional inverter for the output.

Notice that the equations that define the oscillation period for the relaxation oscillator, just using standard CMOS technology instead of DLS, are the same. What differs is the way DLS affects such an equation across different supply voltages and temperatures (as shown in Figure 6). Regarding the temperature, as the transistors of the DLS operate in deep subthreshold, a stronger exponential temperature dependence can be observed (Figure 6b,c). Nevertheless, what makes the use of the DLS for the proposed oscillator remarkable, unlike the standard CMOS, is its slight supply voltage independence (Figure 6a). This is because, in DLS, the current varies slightly linearly with the supply voltage (unlike in standard CMOS). Since the hysteresis window still exhibits slight linear variance, a 10%/V frequency variation occurs over the supply voltage scaling from 1.8 V down to 0.3 V.

Conventional on-chip and traditionally analog-based wake-up oscillators require ancillary circuitry such as current and voltage references and regulation. As the quiescent power of current state-of-the-art references/voltage regulators is in the order of nWs or higher [50,51,52], the intrinsic power consumption of the oscillator is easily exceeded. Accordingly, the dismissal of voltage regulation and references is essential for taking advantage of deep sub-nW oscillators [53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72]. On the contrary, the DLS wake-oscillator (Figure 5) conceived starting from the DVC implemented in CMOS (Figure 1a), according to the steps mentioned above, can operate in the wide voltage range from deep sub-threshold to nominal voltage and achieve the lowest power reported to date (1.4–1.6 pW), outperforming the previous best in class by 2.5X [28,29,30].

Notice that the oscillator implementation with a pseudo-CMOS implementation [73,74] (also named dual-mode logic [75,76,77,78]) allows the use of the relaxation oscillator in other circuit solutions as seen in digital-based sensors, where the switching activity can be hastened, resulting in a conversion time that makes the practical implementation of fully synthesizable and supply voltage-based highly independent fully synthesizable sensors possible for capacitive [76,77] and temperature sensors [78].

5. Conclusions

In this paper, two digital-gate-based circuit solutions have been explored. In particular, the steps involved in transitioning from a fully synthesizable dynamic voltage comparator (DVC) to a relaxation oscillator have been discussed. The relaxation oscillator has been utilized as a wake-up oscillator, reducing both its power consumption and speed by employing DLS logic. This defines a perfect match between a novel digital-gate-based solution and the practical use of an IC building block. Moreover, although they are composed of only a few gates, they can be easily described by a Verilog structural code and incorporated into a digital design flow. Then, both the DVC and the relaxation oscillator show low supply voltage sensitivity across a broad supply voltage range, from nominal voltage to the deep sub-threshold region (i.e., 0.3 V). This eliminates the need for voltage regulation, allowing for direct powering from energy harvesters or batteries throughout their entire discharge cycle. Thus, the DVCs and the relaxation oscillator are well-suited for millimeter-sized energy-harvested sensor nodes.