A Low-Loss Circuit with High-Pass Low-Pass Broadband Flat Negative Group Delay Characteristics

Abstract

A multifunctional circuit with high-pass and low-pass negative group delays can be achieved by simply changing the values of the components in the circuit, without changing the circuit structure. While achieving negative group delay, the circuit also has flat broadband characteristics and lower losses. Theoretical calculations and equation derivation are provided. The experimental circuit was simulated, and the simulation results were essentially consistent with the theoretical results, indicating the feasibility of the experiment.

1. Introduction

Group delay is an important technical indicator in identifying whether a communication system is in good condition, and distortion of group delay can cause some problems, such as increased system error rates. The negative group delay circuit, as a method of balancing group delay, has received a lot of attention.

Since the discovery of the theory of negative group delay, scholars have conducted extensive research on negative group delay circuits and proposed different circuit structures with negative group delay to meet different needs, such as the crab shape, Li type, etc. [1,2,3,4]. This includes lumped parameter circuits and microstrip line circuits. After proposing different circuit structures, scholars conducted theoretical analyses on negative group delay circuits [5,6,7]. At the same time, scholars have attempted to apply different negative group delay circuits in different fields, such as filters [8,9], non-Foster capacitors [10], cables [11], and improving array antenna performance [12,13,14] to eliminate the positive group delay generated by signals passing through communication systems.

Over time, scholars have found that there are usually significant fluctuations in circuit performance when negative group delay occurs. Therefore, the question of how to obtain a flat negative group delay to achieve ultra-low bit error rates in communication has become an important direction of negative group delay research [15]. In Ref. [16], a negative group delay circuit composed of microstrip lines is proposed. With a negative group delay of −1.11 ns and an insertion loss of 9.75 dB, the flat NGD bandwidth is 6.1% and the group delay fluctuation is 11.5%. In the study of flat negative group delay circuits, many scholars use a fluctuation of 8% as the standard [17,18], with a negative group delay of about −0.5 ns and insertion loss of over 15 dB under this standard. Similarly, many scholars use a fluctuation of 20% as the standard, which, as shown in [19], has a negative group delay of −0.2 ns and an insertion loss of 14 dB.

These flat circuit structures can usually only achieve one function. In Ref. [9], a circuit structure with three functions—low pass, high pass, and band pass—is proposed. However, the negative group delay that it achieves is not smooth, and, in research on flatness, it has significant insertion losses. Therefore, it is necessary to develop a multifunctional and low-loss flat negative group delay circuit.

This study proposes a flat negative group delay low-loss circuit that can achieve both high-pass and low-pass functions by changing the circuit component parameters. This article consists of four sections. The second section mainly describes the circuit structure and theoretically analyzes the circuit transfer function and group delay. It explores the impact of delay component parameters on the circuit when implementing a high-pass or low-pass negative group. The third section presents the circuit theory and simulation results and compares them with other research results to demonstrate that the circuit has the advantages of high-pass and low-pass flat negative group delay. The final section presents the conclusions of the study.

2. Circuit Design and Analysis with High-Pass and Low-Pass Negative Group Delay

As shown in Figure 1, the circuit that can achieve high-pass and low-pass negative group delays is composed of a branch connected in series with a capacitor C₁ and in parallel with an inductor L₁, resistor R₁, and inductor L₂, and then connected in series with a branch connected in parallel with a resistor R₂ and inductor L₃. The topology retains the structural characteristics of both the high-pass prototype and the low-pass prototype, and the circuit can be switched between low pass and high pass by adjusting the parameters of the components in the circuit. By changing the values of capacitors C₁, inductors L₃, L₂, and resistors R₁, R₂, the circuit can have the function of a high-pass or low-pass flat negative group delay circuit. Compared with previously designed negative group delay circuits, the negative group delay circuit designed in this work can achieve high-pass negative group delay while maintaining fairly high flatness.

Figure 1. Negative group delay circuit structure diagram.

The impedance value of the circuit is given in Equation (1), and the equivalent [ABCD] matrix model is shown in Figure 2. The [ABCD] matrix value of the circuit is also given in Equation (2). Moreover, the partial admittance of the circuit is given in Equations (3) and (4). By synthesizing Equations (2)–(4), the transfer function of the circuit can be obtained, as given in Equations (5) and (6), and the group delay is given in Equation (7). The results of achieving high-pass and low-pass negative group delays in the circuit are shown in Figure 3 and Figure 4.

$$Z=R_1+j\omega L_2-{\displaystyle \frac{1}{\frac{j}{L_3\omega }-\frac{1}{R_2}}}+{\displaystyle \frac{1}{j\omega C_1-\frac{j}{L_1\omega }}}$$

(1)

$$\left[\begin{array}{cc}A& B\\ C& D\end{array}\right]=\left[\begin{array}{cc}1& {\displaystyle \frac{1}{Y_2}}\\ Y_1& 1+{\displaystyle \frac{Y_1}{Y_2}}\end{array}\right]$$

(2)

$$Y_1={\displaystyle \frac{1}{R_1+j\omega L_2+\frac{1}{j\omega C_1-\frac{j}{\omega L_1}}}}$$

(3)

$$Y_2={\displaystyle \frac{1}{R_2}}-{\displaystyle \frac{j}{\omega L_3}}$$

(4)

$$S_{21}={\displaystyle \frac{2}{A+\frac{B}{Z_0}+C{Z}_0+D}}$$

(5)

$$S_{21}={\displaystyle \frac{-2}{E+F-G-2}}$$

(6)

$$\left\{\begin{array}{c}E={\displaystyle \frac{Z_0\left(C_1{L}_1{\omega }^2-1\right)}{R_1-C_1{L}_1{R}_1{\omega }^2+L_{1}j\omega +L_{2}j\omega -C_1{L}_1{L}_2{\omega }^{3}j}}\hfill \\ F={\displaystyle \frac{L_3{R}_2\omega }{Z_0\left(-L_3\omega +R_{2}j\right)}}\hfill \\ G={\displaystyle \frac{L_3{R}_2\omega \left(C_1{L}_1{\omega }^2-1\right)}{\left(-L_3\omega +R_{2}j\right)\left(R_1-C_1{L}_1{R}_1{\omega }^2+L_1\omega j+L_2\omega j-C_1{L}_1{L}_2{\omega }^{3}j\right)}}\hfill \end{array}\right.$$

(7)

$$\tau \left(\omega \right)=-{\displaystyle \frac{\partial \angle S_{21}}{\partial \omega }}$$

(8)

Figure 2. Equivalent [ABCD] matrix model.

Figure 3. The group delay result generated by the circuit shown in Figure 1.

Figure 4. The S₂₁ result generated by the circuit shown in Figure 1.

2.1. High-Pass Flat Negative Group Delay Circuit

The circuit structure is shown in Figure 1. When the values of the components in the circuit are as shown in Table 1, the circuit is a circuit with a high-pass negative group delay function. The results are shown by the red lines in Figure 3 and Figure 4.

Table 1. Component values for high-pass flat negative group delay low-loss circuit.

C1(pF)	L1 (nH)	R1 (Ω)	L2 (nH)	R2 (Ω)	L3 (nH)
15	3.9	50	3.9	50	50

2.1.1. High-Pass Negative Group Delay Circuits with Different C₁ Values

When the values of $\mathit{L}$₁, R₁, $\mathit{L}$₂, $\mathit{R}$₂, and $\mathit{L}$₃ in the circuit remain unchanged, as shown in Table 1, we change the values of $\mathit{C}$₁ to 5 pF, 15 pF, and 25 pF in sequence and observe the changes in the circuit transfer function and group delay. The circuit results in these three cases are shown in Table 2 and Figure 5 and Figure 6. Through observation, it is found that changing the value of capacitor $\mathit{C}$₁ does not change the group delay of the high-pass circuit at 0 MHz. However, as the frequency increases, the larger the value of capacitor $\mathit{C}$₁, the greater the negative group delay value. The change in capacitor $\mathit{C}$₁ also affects the flat negative group delay bandwidth. If the capacitance is too large or too small, the negative group delay will not have a relatively flat characteristic, and the circuit insertion loss will also decrease with the increase in capacitor $\mathit{C}$₁. $\mathit{C}$₁ is the key capacitive element of a high-pass negative group delay circuit, and changes in its value modify the circuit’s impedance characteristics and energy transfer efficiency. When $\mathit{C}$₁ is increased, the impedance matching and resonance characteristics of the branch in the circuit formed by the participation are changed, resulting in a reduction in the energy attenuation of the signal as it is transmitted through the circuit, which in turn manifests itself as a reduction in the loss of insertion (IL).

Table 2. Circuit results with different $\mathit{C}$₁ values.

C1 (pF)	τ (ns)	FBW (MHz)	IL (dB)
5	−0.141	102.5	−7.178
15	−0.147	302	−7.098
25	−0.154	140	−7.012

Note: FBW is the relative negative group delay bandwidth, which is defined by the equation FBW = $f_c$/bandwidth.

Figure 5. Group delay results for different $\mathit{C}$₁ values.

Figure 6. $\mathit{S}$₂₁ results for different $\mathit{C}$₁ values.

2.1.2. High-Pass Negative Group Delay Circuits with Different L₁ Values

When the values of $\mathit{C}$₁, $\mathit{R}$₁, $\mathit{L}$₂, $\mathit{R}$₂, and $\mathit{L}$₃ in the circuit remain unchanged, as shown in Table 1, we change the values of $\mathit{L}$₁ to 0.9 nH, 3.9 nH, and 5.9 nH in sequence and observe the changes in the circuit transfer function and group delay. The circuit results in these three scenarios are shown in Table 3 and Figure 7 and Figure 8. Through observation, it is found that, as the value of inductance $\mathit{L}$₁ increases, the group delay of the high-pass circuit at 0 MHz decreases. As the frequency increases, the larger the value of capacitance $\mathit{L}$₁, the smaller the negative group delay value. The change in inductance $\mathit{C}$₁ also affects the flat negative group delay bandwidth, and the insertion loss of the circuit also decreases with the increase in inductance $\mathit{L}$₁.

Table 3. Circuit results with different $\mathit{L}$₁ values.

L1 (nH)	$\mathit{\tau }$ (ns)	FBW (MHz)	IL (dB)
0.9	−0.117	134.5	−7.463
3.9	−0.147	302	−7.098
5.9	−0.172	201	−6.852

Figure 7. Group delay results for different $\mathit{L}$₁ values.

Figure 8. $\mathit{S}$₂₁ results for different $\mathit{L}$₁ values.

2.1.3. High-Pass Negative Group Delay Circuits with Different R₁ Values

When the values of $\mathit{C}$₁, $\mathit{L}$₁, $\mathit{L}$₂, $\mathit{R}$₂, and $\mathit{L}$₃ in the circuit remain unchanged from Table 1, we change the values of R₁ to 10 Ω, 50 Ω, and 100 Ω in sequence and observe the changes in the circuit transfer function and group delay. The circuit results in these three cases are shown in Table 4 and Figure 9 and Figure 10. Through observation, it is found that, as the value of resistance $\mathit{R}$₁ decreases, the negative group delay value of the circuit is no longer flat. However, as $\mathit{R}$₁ decreases, the minimum negative group delay of the high-pass circuit decreases, and the circuit insertion loss also decreases with the increase in resistance $\mathit{R}$₁.

Table 4. Circuit results with different $\mathit{R}$₁ values.

R1 (Ω)	$\mathit{\tau }$ (ns)	FBW (MHz)	IL (dB)
10	−0.443	28.5	−4.59
50	−0.147	302	−7.098
100	−0.079	293	−12.565

Figure 9. Group delay results for different $\mathit{R}$₁ values.

Figure 10. $\mathit{S}$₂₁ results for different $\mathit{R}$₁ values.

2.1.4. High-Pass Negative Group Delay Circuits with Different L₂ Values

When the values of C₁, R₁, L₁, R₂, and L₃ in the circuit remain unchanged, as shown in Table 1, and the L₂ values are sequentially changed to 0.9 nH, 3.9 nH, and 5.9 nH, we observe the changes in the circuit transfer function and group delay. The circuit results in these three scenarios are shown in Table 5 and Figure 11 and Figure 12. Through observation, it is found that, as the value of inductance L₂ increases, the group delay of the high-pass circuit at 0 MHz decreases, but the difference is small. Changing the value of inductance L₂ also has a small impact on the bandwidth of the flat negative group delay. At the same time, the insertion loss of the circuit also decreases with the increase in inductance L₂.

Table 5. Circuit results with different $\mathit{L}$₂ values.

L2 (nH)	$\mathit{\tau }$ (ns)	FBW (MHz)	IL (dB)
0.9	−0.126	225	−7.729
3.9	−0.147	302	−7.098
5.9	−0.160	127.5	−6.958

Figure 11. Group delay results for different $\mathit{L}$₂ values.

Figure 12. $\mathit{S}$₂₁ results for different $\mathit{L}$₂ values.

2.1.5. High-Pass Negative Group Delay Circuits with Different $\mathit{R}$₂ Values

When the values of $\mathit{C}$₁, $\mathit{L}$₁, $\mathit{L}$₂, $\mathit{R}$₁, and $\mathit{L}$₃ in the circuit remain unchanged, as shown in Table 1, and the $\mathit{R}$₂ values are sequentially changed to 10 Ω, 50 Ω, and 100 Ω, we observe the changes in the circuit transfer function and group delay. The circuit results in these three cases are shown in Table 6 and Figure 13 and Figure 14. Through observation, it is found that the group delay of the high-pass circuit remains unchanged at 0 MHz as the resistance $\mathit{R}$₂ value changes. However, increasing or decreasing $\mathit{R}$₂ will lead to poorer flatness of the high-pass circuit. The negative group delay value will also decrease as $\mathit{R}$₂ decreases, and the insertion loss of the circuit will also increase with the increase in resistance $\mathit{R}$₂.

Table 6. Circuit results with different $\mathit{R}$₂ values.

R2 (Ω)	τ (ns)	FBW (MHz)	IL (dB)
10	−0.170	191.5	−4.516
50	−0.147	302	−7.098
100	−0.139	25	−8.734

Figure 13. Group delay results for different $\mathit{R}$₂ values.

Figure 14. $\mathit{S}$₂₁ results for different $\mathit{R}$₂ values.

2.1.6. High-Pass Negative Group Delay Circuits with Different $\mathit{L}$₃ Values

When the values of $\mathit{C}$₁, $\mathit{R}$₁, $\mathit{L}$₁, $\mathit{R}$₂, and $\mathit{L}$₂ in the circuit remain unchanged from Table 1, we change the values of $\mathit{L}$₃ to 5 nH, 50 nH, and 100 nH in sequence and observe the changes in the circuit transfer function and group delay. The circuit results in these three cases are shown in Table 7 and Figure 15 and Figure 16. Through observation, it is found that, as the value of inductance $\mathit{L}$₃ increases, the group delay of the high-pass circuit at 0 MHz increases. As the value of inductance $\mathit{L}$₃ increases, the negative group delay value decreases, and the circuit insertion loss increases with the increase in inductance $\mathit{L}$₃.

Table 7. Circuit results with different $\mathit{L}$₃ values.

L3 (nH)	τ (ns)	FBW (MHz)	IL (dB)
5	+0.134	/	−3.577
50	−0.147	302	−7.098
100	−0.224	35.5	−7.536

Figure 15. Group delay results for different $\mathit{L}$₃ values.

Figure 16. $\mathit{S}$₂₁ results for different $\mathit{L}$₃ values.

2.2. Low-Pass Flat Negative Group Delay Circuit

The circuit structure is shown in Figure 1. When the values of the components in the circuit are as shown in Table 8, the circuit has a low-pass negative group delay function, as shown by the blue lines in Figure 3 and Figure 4.

Table 8. Component values for low-pass flat negative group delay low-loss circuit.

C1 (pF)	L1 (nH)	R1 (Ω)	L2 (nH)	R2 (Ω)	L3 (nH)
10	82	100	3.9	100	0.3

2.2.1. Low-Pass Negative Group Delay Circuits with Different C₁ Values

When the values of L₁, R₁, L₂, R₂, and L₃ in the circuit remain unchanged, as shown in Table 8, and the values of C₁ are sequentially changed to 5 pF, 10 pF, and 15 pF, we observe the changes in the circuit transfer function and group delay. The circuit results in these three cases are shown in Table 9 and Figure 17 and Figure 18. Through observation, it is found that changing the value of capacitor C₁ does not change the group delay of the low-pass circuit at 0 MHz. However, as the frequency increases, the larger the value of capacitor C₁, the smaller the negative group delay value. The change in capacitor C₁ also affects the flat negative group delay bandwidth. If the capacitance is too large or too small, the negative group delay will not have a relatively flat characteristic, and the change in C₁ does not affect the maximum insertion loss value of the circuit.

Table 9. Circuit results with different $\mathit{C}$₁ values.

C1 (pF)	τ (ns)	FBW (MHz)	IL (dB)
5	−0.149	61	−1.938
10	−0.168	85.5	−1.938
15	−0.199	43.5	−1.938

Figure 17. Group delay results for different $\mathit{C}$₁ values.

Figure 18. $\mathit{S}$₂₁ results for different $\mathit{C}$₁ values.

2.2.2. Low-Pass Negative Group Delay Circuits with Different $\mathit{L}$₁ Values

When the values of C₁, R₁, L₂, R₂, and L₃ in the circuit remain unchanged, as shown in Table 8, and the L₁ values are sequentially changed to 20 nH, 82 nH, and 160 nH, we observe the changes in the circuit transfer function and group delay. The circuit results in the three scenarios are shown in Table 10 and Figure 19 and Figure 20. Through observation, it is found that, as the value of inductance L₁ increases, the group delay of the low-pass circuit at 0 MHz decreases, while the bandwidth of the flat negative group delay decreases. The circuit insertion loss does not change with the change in inductance L₁.

Table 10. Circuit results with different $\mathit{L}$₁ values.

L1 (nH)	τ (ns)	FBW (MHz)	IL (dB)
20	−0.044	158.5	−1.938
82	−0.168	85.5	−1.938
160	−0.324	26	−1.938

Figure 19. Group delay results for different $\mathit{L}$₁ values.

Figure 20. $\mathit{S}$₂₁ results for different $\mathit{L}$₁ values.

2.2.3. Low-Pass Negative Group Delay Circuits with Different R₁ Values

When the values of C₁, L₁, L₂, R₂, and L₃ in the circuit remain unchanged, as shown in Table 8, we change the values of R₁ to 50 Ω, 100 Ω, and 200 Ω in sequence and observe the changes in the circuit transfer function and group delay. The circuit results in these three cases are shown in Table 11 and Figure 21 and Figure 22. Through observation, it is found that, as the value of resistance R₁ decreases, the negative group delay value of the circuit is no longer flat. However, as R₁ decreases, the minimum negative group delay of the high-pass circuit decreases, and the circuit insertion loss also decreases with the increase in resistance R₁.

Table 11. Circuit results with different $\mathit{R}$₁ values.

R1 (Ω)	τ (ns)	FBW (MHz)	IL (dB)
50	−0.569	16	−3.522
100	−0.168	85.5	−1.938
200	−0.044	71	−1.023

Figure 21. Group delay results for different $\mathit{R}$₁ values.

Figure 22. $\mathit{S}$₂₁ results for different $\mathit{R}$₁ values.

2.2.4. Low-Pass Negative Group Delay Circuits with Different L₂ Values

When C₁, R₁, L₁, R₂, and L₃ in the circuit remain unchanged from the values in Table 8, and the L₂ values are sequentially changed to 0.9 nH, 3.9 nH, and 5.9 nH, we observe the changes in the circuit transfer function and group delay. The circuit results in the three scenarios are shown in Table 12 and Figure 23 and Figure 24. Through observation, it is found that, as the value of inductance L₂ increases, the group delay of the high-pass circuit at 0 MHz decreases, but the difference is small. Changing the value of inductance L₂ also has a small impact on the bandwidth of the flat negative group delay. At the same time, the insertion loss of the circuit does not change with the value of inductance L₂.

Table 12. Circuit results with different $\mathit{L}$₂ values.

L2 (nH)	τ (ns)	FBW (MHz)	IL (dB)
0.9	−0.162	84	−1.938
3.9	−0.168	85.5	−1.938
5.9	−0.172	86.5	−1.938

Figure 23. Group delay results for different $\mathit{L}$₂ values.

Figure 24. $\mathit{S}$₂₁ results for different $\mathit{L}$₂ values.

2.2.5. Low-Pass Negative Group Delay Circuits with Different $\mathit{R}$₂ Values

When the values of C₁, L₁, L₂, R₁, and L₃ in the circuit remain unchanged, as shown in Table 8, and the R₂ values are sequentially changed to 50 Ω, 100 Ω, and 200 Ω, we observe the changes in the circuit transfer function and group delay. The circuit results are identical in all three cases.

2.2.6. Low-Pass Negative Group Delay Circuits with Different $\mathit{L}$₃ Values

When the values of C₁, R₁, L₁, R₂, and L₂ in the circuit remain unchanged, as shown in Table 8, and L₃ is sequentially changed to 0.3 nH, 1.3 nH, and 2.3 nH, we observe the changes in the circuit transfer function and group delay. The circuit results in these three cases are shown in Table 13 and Figure 25 and Figure 26. Through observation, it is found that, as the value of inductance L₃ increases, the group delay of the high-pass circuit at 0 MHz decreases. As the value of inductance L₃ increases, the negative group delay also decreases. The degree of change in the circuit insertion loss is not significant, but, as the frequency increases, the insertion loss increases with the increase in inductance L₃.

Table 13. Circuit results with different $\mathit{L}$₃ values.

L2 (nH)	τ (ns)	FBW (MHz)	IL (dB)
0.3	−0.168	85.5	−1.938
1.3	−0.156	85.5	−1.938
2.3	−0.144	85.5	−1.938

Figure 25. Group delay results for different $\mathit{L}$₃ values.

Figure 26. $\mathit{S}$₂₁ results for different $\mathit{L}$₃ values.

3. Circuit Simulation with High-Pass and Low-Pass Negative Group Delay

Based on the analysis of the circuit parameters, and considering the factors of the average negative group delay bandwidth and insertion loss, the parameters of the high-pass circuit are determined as in Table 14, and those of the low-pass circuit are as shown in Table 15. The circuit was simulated using the ADS software and Murata simulation library. The simulation results are shown in Table 14 and Table 15 and Figure 27 and Figure 28, and they are consistent with the theoretical results, indicating the feasibility of the experiment. We take inductor L₃ as an example to analyze the effects of component tolerance on the circuit. We select inductors with different tolerances and the same inductance value in the Murata component library for simulation, and the simulation results are shown in Figure 29. The results obtained using inductors with different tolerances are essentially the same, which indicates that the component tolerances have a small effect on the circuit. As shown in Table 16, we achieve the characteristics of a larger negative group delay bandwidth, flatter bandwidth, and lower loss compared to other studies. During the comparison process, the GD ripple is calculated as shown in Equation (7).

$$GDripple={\displaystyle \frac{GDfluctuation/2}{\left|\tau \right|+\left|GDfluctuation/2\right|}}\ast 100\%$$

(9)

Table 14. High-pass circuit theory and simulation results.

	τ (ns)	FBW (MHz)	IL (dB)	GD Ripple
Theory	−0.147	302	−7.098	5.53%
Simulation	−0.131	295.5	−6.851	2.19%

Table 15. Low-pass circuit theory and simulation results.

	τ (ns)	FBW (MHz)	IL (dB)	GD Ripple
Theory	−0.168	85.5	−1.938	1.67%
Simulation	−0.160	43.5	−1.938	3.44%

Figure 27. Theoretical and simulation group delay results.

Figure 28. Theoretical and simulation S₂₁ results.

Figure 29. Cluster delay results for $\mathit{L}$₃ with different tolerances.

Table 16. Comparison with other studies.

Ref.	IL (dB)	τ (ns)	NBW (MHz)	Relatively FBW	GD Ripple
[7]	14	−0.2	310	9.3%	20%
[10]	16.6	−0.49	550	14.7%	8%
[18]	9.75	−1.11	-	6.1%	11.5%
[20]	40	$-1.51\times {10}^9$	$3.18\times {10}^{-7}$	-	0%
This work (high)	6.833	−0.147	469	169%	5.53%
This work (low)	1.76	−0.168	120	133%	1.67%

Note: NBW stands for negative group delay bandwidth. In some cases, this bandwidth is greater than 3 dB and can lead to severe distortion.

4. Conclusions

The proposed negative group delay circuit can achieve high- or low-pass negative group delay circuit functionalities through parameter adjustment, and it has multifunctionality. Moreover, the designed and implemented negative group delay circuit has the characteristics of a larger negative group delay bandwidth, better flatness, and lower transmission loss. Through testing, it has been proven to yield consistent experimental results and demonstrates feasibility. These results lay the foundation for subsequent research and can also be applied to various circuits to eliminate the originally generated positive group delay in the circuit and achieve the goal of reducing signal errors.