Design Analysis of a Modified Current-Reuse Low-Power Wideband Single-Ended CMOS LNA

Abstract

This paper presents the design analysis of a low-power wideband single-ended CMOS low-noise amplifier (LNA). The proposed topology is based on a modified current- reuse circuit, in which two-stage common-source (CS) amplifiers consume the same DC current and are isolated from each other by large MIMCAPs, which results in good performance with low power consumption. The proposed circuit achieves a bandwidth of 2.5 GHz, suitable for several wireless communication standards such as GSM, WLAN, and Bluetooth. In the first stage, a current-reuse circuit with shunt feedback is used to satisfy input impedance matching and signal amplification with minimal noise injection. A common source (CS) with a source follower circuit forms the second stage to improve the noise figure (NF), harmonic distortion, and output impedance matching. The proposed LNA is designed in 65 nm CMOS technology and covers a frequency range of 0.17–2.68 GHz. The proposed LNA achieves a maximum gain of 17.24 dB, a minimum NF of 2.67 dB, a maximum IIP3 of −14.9 dBm, and input and output return losses of less than −10 dB. The power consumption of the proposed LNA is 3.52 mW from a 1 V power supply, and the core area is 0.3 mm².

1. Introduction

Wideband low-noise amplifiers (LNAs) are the main building blocks in a receiver system to cover multiple wireless communication standards. LNAs should amplify the weak signal received by the antenna with a flat response and minimal noise injection. Also, input impedance and linearity over the frequency bandwidth are two important parameters of wideband LNAs, used to prevent signal reflections and harmonic distortion [1]. However, in the design of wideband LNAs, there is a trade-off between the above-mentioned parameters and power consumption [2]. Recently, low-power designs have received a lot of attention, as most of the systems are powered by only a single lithium battery, which must work for several days (mobile phone) or even a year (medical devices). Therefore, designing low-power circuits is a hot topic of research in academia and is a major challenge for RF designers [3]. LNAs can either be single-ended or differential. Although single-ended LNAs have lower gain and linearity, they have good stability and low-noise performance, whereas differential LNAs are excellent at achieving high gain and better linearity [4]. Common-gate (CG) and common-source (CS) circuits are used either individually or in combination for differential and single-ended LNA designs [5]. Although CG topology shows the best performance for wideband LNAs because of its low input impedance independent of frequency, it needs higher power consumption to satisfy input impedance matching and the noise figure (NF). Therefore, CG topology is not often used alone for low-power circuits. A CS with shunt feedback is another choice in designing wideband LNAs and consumes more power to achieve high gain and a low NF, necessitating current-reuse techniques [6].

The noise cancellation technique is another method for reducing thermal noise with low power consumption, as reported in 2004 [7]. Figure 1a shows conventional current-reuse with shunt feedback [2], and 1b shows a noise cancellation LNA [7]. In [8], a differential LNA was reported that shows good linearity. In the reported work, using a combination of CS, CG, and a cross-couple structure between the positive and negative outputs, linearity was improved without a gain reduction over the entire bandwidth. However, the requirement of an external RF choke, an additional buffer, and high power consumption of around 12 mW are its limitations. The authors of [9] reported a differential LNA by combining CG and CS in 65 nm CMOS. Although the gain was high, high power consumption of 19.8 mW made it unsuitable for low-power devices. A low-power differential LNA using CG and CS was reported in [10], which presented a differential LNA with a frequency range of 0.05 to 1.3 GHz. However, an external RF choke was used, similar to [9,10]. In [11], a differential LNA for sub-GHz applications with a low power of 3 mW was presented, but the minimum NF of 3.6 dB was not suitable for noise-sensitive applications. In [12], an inductor-less wideband LNA that covered 0.18 to 2 GHz was reported. The presented circuit used a combination of CG and CS topology with transconductance (gm) and was boosted by using a cross-couple structure between differential nodes. However, the results were reported under an unmatched output impedance. If the buffer current is calculated, the results become poor. Reference [13] reported a noise and distortion cancellation LNA with single-ended output that achieved reasonable results with an ultra-low power (under 1 mW) by handling shunt feedback and the feedforward technique. Although the reported circuit consumes ultra-low amounts of power, it needs a buffer network to measure, and the minimum NF of 4.45 dB is high. Yunyou Pu and Wei Li reported a differential wideband LNA from 0.2 to 3.2 GHz by using CS and CG and a noise cancellation technique [14]. Although they achieved a high gain and a minimum NF of 1.4 dB, the power dissipation was 17.4 mW, which is very high for low-power applications. In [15], a single-ended LNA with CG, current-reuse and noise cancellation circuits for low-voltage and low-power applications was presented. Though the results were acceptable, the area and power of buffer circuit was not calculated. In [16], a differential wideband LNA using noise and distortion cancellation techniques with a 1.6 GHz bandwidth was presented. A minimum NF of 1.1 dB was reported; however, its power consumption of 9.1 mW is high for low-power systems.

This paper presents a single-ended wideband LNA for low-power applications which covers the frequency range from 0.17 to 2.68 GHz. The proposed circuit consists of two stages. The first stage employs a current-reuse topology incorporating both shunt feedback and series inductive peaking techniques to achieve flat gain with low NF while satisfying input impedance matching requirements. The second stage implements a combined CG and CS configuration that functions as a buffer network while simultaneously improving NF and linearity performance. Both stages share the same DC bias current and are isolated through a large metal–insulator–metal capacitor (MIMCAP). Due to the current-reuse technique, the proposed LNA achieves significant power consumption reduction. Furthermore, the output impedance is matched to a 50 Ω load without requiring an additional buffer network for measurement. The paper is organized as follows. Section 2 analyzes the proposed LNA structure in detail. Section 3 presents the post-layout simulation results, and finally Section 4 provides the conclusion.

2. Analysis of the Proposed LNA

Figure 2 shows the schematic of the proposed wideband LNA with its component values. The proposed LNA consists of two stages. Transistors M₁ and M₂ form the first stage as a current-reuse circuit. The length of transistors M₁ and M₂ is chosen to be slightly longer than the minimum length of the used technology (65 nm) to increase the intrinsic impedance between source and drain (1/gds), which slightly increases the voltage gain at node A [17]. M₁ and M₂ also play the role of a gm-boosting for M₅; therefore, the signal at node A is amplified by M₅ and appears at node B. M₅ and M₆ are an auxiliary stage in the proposed LNA. M₈ acts as shunt-series feedback to meet wideband input impedance matching and linearity improvement. M₈ is biased in the sub-threshold region to decrease power. Also, since the gain at node B is high, input impedance matching is satisfied very well without increasing the feedback network coefficient (gm₈). Transistors M₃ and M₄ form the second stage of the proposed LNA, which consumes the same DC current as the first stage and is decoupled from the first stage by capacitor C_B1. The second stage also acts as a buffer stage, which is used to match the output impedance. The gate terminal of the M₄ is also connected to the input (node C) and acts as a noise and distortion cancellation technique to improve the gain, NF, and linearity. This means that the noise and harmonic distortion returned by the feedback network are amplified by this transistor with a 180° phase difference and summed with the output, which reduces distortion and noise. Inductor Lg is used to achieve a flat gain, input impedance matching, and improved bandwidth. The Lg is a standard spiral-on-chip inductor which acts as a series inductive peaking element to compensate for parasitic capacitors (node D). The quality factor (Q-factor) of the Lg has a significant effect on the S₂₁ and NF for frequencies above 1.5 GHz. Therefore, when the Q-factor decreases, S₂₁ drops and the NF increases, resulting in the bandwidth reducing by −3 dB. The Q-factor of spiral inductors is influenced by the metal width and inner radius. Increasing the metal width reduces the series resistance, which enhances the Q-factor. However, it also increases parasitic capacitances, ultimately limiting the Q-factor at higher frequencies. On the other hand, a larger inner radius reduces both conductor losses and parasitic capacitance, leading to an improved quality factor [18]. To achieve optimal performance, the inductor geometry is carefully optimized for the highest possible Q-factor, as demonstrated in Figure 2. Additionally, temperature variations impact the Q-factor due to changes in metal resistivity and substrate losses. Specifically, as temperature decreases, the Q-factor increases slightly, though this effect is relatively minor [19].

The DC points of nodes A and B are set by a common-mode feedback (CMFB) circuit. Although the combinations of CMFB with transistors M₁ and M₆ form a negative feedback loop, the effect of the CMFB loop on the proposed circuit has been investigated. Figure 3 shows the effect of CMFB1 and CMFB2 on the small signal response. The outputs of CMFB1 and CMFB2 are connected to the gates of M₁ and M₆, respectively, through a large resistor RB (12 KΩ). Since the impedance seen at these nodes (C and D) is approximately Rs (50 Ω), the return signal from the CMFB loop reaches the transistor gates with significant attenuation. Therefore, the CMFB loop does not affect the stability conditions of the proposed circuit. While a bypass capacitor could be used at the CMFB outputs to ensure stability at higher frequencies, it is not required in the proposed design.

The details of the input impedance matching, voltage gain, NF, and linearity of the proposed single-ended wideband LNA are presented in the following section.

2.1. Input Impedance Matching

Figure 4 shows the small-signal model of the first stage for the input impedance calculation. The Lg compensates for the parasitic capacitors (C_P) at node D for frequencies above 1.5 GHz. Using the Lg enables input impedance matching over the entire bandwidth (0.17 to 2.68 GHz).

As shown in Figure 4, the input impedance of the proposed LNA is approximately calculated as follows:

$$Zin\approx {\displaystyle \frac{1}{S{C}_1}}‖\hspace{0.17em}\hspace{0.17em}\left({\displaystyle \frac{S^{2}Lg{C}_P+1}{S{C}_P+g{m}_8{Z}_B\left(S^{2}Lg{C}_P+1\right)\times \left(\frac{g{m}_6}{1+g{m}_{6}r{o}_7}+\frac{g{m}_5}{S^{2}Lg{C}_P+1}-\frac{g{m}_5{Z}_A\left(g{m}_5-\left(g{m}_1+g{m}_2\right)\right)}{\left(1+g{m}_5{Z}_A\right)\left(S^{2}Lg{C}_P+1\right)}+1\right)}}\right)$$

(1)

where $Z_A\approx r{o}_1‖r{o}_2$, $Z_B\approx \left(g{m}_{6}r{o}_{6}r{o}_7\right)‖\left(g{m}_{5}r{o}_5\left(r{o}_1‖r{o}_2\right)\right)$, and C_P represents the parasitic capacitance at node D, which is approximately equal to

$$C_P\approx \left(Cg{s}_1+Cg{s}_2\right)+\left(Cg{d}_1+Cg{d}_2+Cg{s}_5\right)\left(1+\left(g{m}_1+g{m}_2\right)\left(r{o}_1‖r{o}_2\right)\right)$$

(2)

Based on Equation (1), when the Lg and C_P are in resonance, the input impedance decreases significantly, which noticeably affects S₁₁. However, the resonance frequency occurs at approximately 6 GHz, which is well beyond the desired bandwidth (0.17–2.68 GHz).

2.2. Voltage Gain

Figure 5 shows the AC model of the proposed LNA. M₁ and M₂ form the first stage, M₅ and M₆ constitute the auxiliary stage, and M₈ forms the feedback network. Transistors M₃ and M₄ form the second stage.

Considering an output load R_L of 50 Ω, the voltage gain can be approximately calculated as follows:

$${\displaystyle \frac{V_O}{V_S}}\approx {\displaystyle \frac{\left(g{m}_3{Z}_B\left(1+g{m}_{6}r{o}_7\right)\left(-\left(g{m}_1+g{m}_2\right)\left(1+g{m}_{6}r{o}_7\right)-g{m}_6\right)-g{m}_4\left(1+g{m}_{6}r{o}_7\right)\right)R_L}{\left(1+g{m}_3{R}_L\right)\left(1+g{m}_{6}r{o}_7\right)\left(1+g{m}_8{R}_S\left(\left(g{m}_1+g{m}_2\right)Z_B+1\right)\right)+g{m}_8{R}_{S}g{m}_6{Z}_B}}$$

(3)

where $Z_B\approx \left(g{m}_{6}r{o}_{6}r{o}_7\right)‖\left(g{m}_{5}r{o}_5\left(r{o}_1‖r{o}_2\right)\right)$. The Lg and parasitic capacitors are not considered in Equation (3) to simplify calculation and improve understanding; however, the effect of the Lg on the gain is explained below.

The Lg acts as a series inductive peaking element to compensate for the parasitic capacitances at node D. Figure 6 shows −3 dB bandwidth enhancement using the Lg as a series inductive peaking element. As shown, it is clear that before the current-reuse stage, passive gain is created by the Lg at node D, which increases the −3dB bandwidth.

2.3. Noise Analysis

Considering the proposed circuit consists of two stages, according to the Friis equation, it is clear that the first stage has the main effect on NF [2]. In the proposed LNA, the current-reuse circuit (M₁, M₂) dominates the thermal noise contribution. In the auxiliary stage, the thermal noise of M₅ and M₆ can be ignored due to their source-degenerated impedance [2]. In the feedback network, M₈ is biased in sub-threshold region, where shot noise is comparable to thermal noise [20]. Although M₈ injects noise into the circuit before the first stage which could affect the NF of entire receiver due to its equal amplification with the desired signal, this noise can be also ignored, because the impedance at the input node (node C) is sufficiently small. In the second stage, M₄ is connected between the input and output as a CS stage serving as a noise cancellation technique [7]. Therefore, the dominant noise (M₁, M₂) can be cancelled by M₄. The noise of M₁ and M₂ appears at the output, as described by Equation (4).

$$\overline{V_{noise}ou{t}^2}={\left(\begin{array}{l}\left({\displaystyle \frac{g{m}_{3}Zout}{1+g{m}_{3}Zout}}-{\displaystyle \frac{g{m}_{4}g{m}_{8}RsZout}{1+g{m}_{8}Rs}}\right)\times \\ \left({\displaystyle \frac{g{m}_5{Z}_B\left(1+g{m}_{8}Rs\right)\left(1+g{m}_{6}r{o}_7\right)}{g{m}_{8}Rs\left(Z_B\left(g{m}_5\left(1+g{m}_{6}r{o}_7\right)+g{m}_6\right)+g{m}_{6}r{o}_7+1\right)+g{m}_{6}r{o}_7+1}}\right)\end{array}\right)}^2\left(\overline{I{n}_1^2}+\overline{I{n}_2^2}\right)\times Z_A^2$$

(4)

where $Zout\approx {\displaystyle \frac{1}{g{m}_3}}‖r{o}_4‖R_L$, $Z_B\approx \left(g{m}_{6}r{o}_{6}r{o}_7\right)‖\left(g{m}_{5}r{o}_5\left(r{o}_1‖r{o}_2\right)\right)$, $Z_A\approx r{o}_1‖r{o}_2$ and $\overline{I{n}^2}=4KT\gamma gm$.

Therefore, complete noise cancellation is achieved when Equation (5) is satisfied, as derived from Equation (4).

$${\displaystyle \frac{g{m}_3}{1+g{m}_{3}Zout}}={\displaystyle \frac{g{m}_{4}g{m}_{8}Rs}{1+g{m}_{8}Rs}}$$

(5)

In Equation (5), the value of gm₄ is limited by low-power design constraints, preventing complete cancellation conditions from being met. Consequently, the NF is slightly improved. The resulting NF of the proposed circuit is calculated as follows:

$$NF=1+{\displaystyle \frac{{\left(r{o}_1‖r{o}_2\right)}^2{\left(1+{gm}_{8}Rs\right)}^2\gamma \left(g{m}_1+g{m}_2\right)}{{\left(1+\left(g{m}_1+g{m}_2\right)\left(r{o}_1‖{ro}_2\right)\right)}^{2}Rs}}$$

(6)

where γ is the correction factor that is assumed identical for both the NMOS (M₁) and PMOS (M₂) transistors for simplicity. According to Equation (6), since the value of $\left(g{m}_1+g{m}_2\right)\left(r{o}_1‖{ro}_2\right)$ is significantly greater than 1, Equation (6) can be simplified to Equation (7).

$$NF\approx 1+{\displaystyle \frac{{\left(1+{gm}_{8}Rs\right)}^2\gamma }{\left(g{m}_1+g{m}_2\right)Rs}}$$

(7)

As Equation (7) demonstrates, a stronger feedback network of M₈ $\left(g{m}_8{R}_S\right)$ results in poorer NF performance. Furthermore, Equation (1) indicates that input impedance depends on feedback of M₈, establishing a fundamental trade-off between S₁₁ and NF.

2.4. Linearity Analysis

Typically, both single-ended and differential LNAs are implemented as single-stage designs to optimize linearity. For non-ideal amplifiers, the signal amplification can be approximated as follows [2]:

$$y\left(t\right)\approx {\alpha }_{1}x\left(t\right)+{\alpha }_2{x}^2\left(t\right)+{\alpha }_3{x}^3\left(t\right)+\dots$$

(8)

where α₁ is the small-signal gain. In differential LNAs, due to the output differential signal, the second term of Equation (8) can be decreased significantly [2], but third-order harmonic is still problematic [8].

Figure 7 illustrates the mechanism of linearity improvement in the proposed circuit. when two interferer signals of ${\omega }_1,\hspace{0.17em}{\omega }_2$ are applied to the input, a third-order harmonic of $2{\omega }_2-{\omega }_1$ and $2{\omega }_1-{\omega }_2$ is generated at the output of the first stage (node A). The harmonic generated at node A appears at node B through M₅ while being returned to the input (node C) via the feedback of M₈. This feedback signal is then amplified by M₄ with a 180° phase difference, thus reducing output distortion and improving linearity [7]. Similar to the noise analysis section, Equation (5) is also valid for canceling the generated harmonic, but as mentioned in the noise analysis, the generated harmonic cannot be cancelled completely. In the other words, the harmonics at node B reach node C with a large attenuation coefficient, which transistor M₄ cannot fully compensate for due to its low-power design and consequently low gm₄; this results in the linearity of the proposed LNA being improved by slightly less than 2 dB.

3. Simulation Results

The proposed low-power single-ended wideband LNA is suitable for low-power multi-standard receivers that cover the frequency range of 0.17–2.68 GHz, including (GSM, WLAN and Bluetooth). The proposed LNA is designed in 65 nm CMOS technology with a 1 V supply voltage and is simulated using Cadence Spectre-RF. An external reference current (IREF) of 50µA is applied to the proposed circuit for biasing. Figure 8 shows the layout of the proposed wideband LNA with a core area of 0.3 mm². The area of the proposed LNA including pads is 0.45 mm². The post-layout simulation results of input return loss (S₁₁), output return loss (S₂₂), power gain (S₂₁), and NF for the proposed wideband LNA across PVT and corner variations are presented in Figure 9 and Figure 10, respectively. Corner simulations are considered for the worst-case scenario (Fast–Fast (FF) at −40° and Slow–Slow (SS) at 85 °C) [8]. As shown in Figure 9 and Figure 10, both S₁₁ and S₂₂ remain below −10 dB; furthermore, S₂₁ exceeds 15 dB, while the NF remains below 3.24 dB over the desired bandwidth. Based on Figure 9a, in FF mode at −40 °C, S₁₁ shows a significant deviation from other conditions. This is because in CMOS technology, as the temperature decreases, the threshold voltage increases [21]. Therefore, with decreasing temperature, the voltage at node A increases while the current through M₅ decreases significantly, causing a reduction in gm₅. Based on Equation (1), the decreased gm₅ reduces the feedback network loop effect, resulting in increased input impedance and S₁₁.

To validate the simulation results, Monte Carlo simulations were also conducted for S₁₁, S₂₁, and NF at sensitive frequency points, as shown in Figure 11, Figure 12 and Figure 13. Based on Figure 9 and Figure 10, since S₁₁ in FF mode at −40 °C shows deviation in the sub-GHz range and S₂₁ and NF can exhibit significant variations due to the Q-factor of the Lg above 2 GHz, the sensitive frequency points were selected as 500 MHz for S₁₁ and 2.5 GHz for S₂₁ and NF. As shown in Figure 11, Figure 12 and Figure 13, S₂₁ and NF have average values of 15.2 dB and 3.13 dB at 2.5 GHz, respectively, and the mean S₁₁ value at 500 MHz is −15.2 dB.

Figure 14 shows the stability factor (Kf) across process corners and temperature variations from 0.1 to 12 GHz. The stability factor exceeds unity across the entire 0.1–12 GHz range, demonstrating that the proposed circuit is unconditionally stable.

To verify the inductance and Q-factor of the Lg, electromagnetic (EM) simulation was performed using the Advance Design System (ADS) Momentum EM simulator. As depicted in Figure 15, the simulation results at 2 GHz indicate that Lg exhibits an inductance of 5.9 nH and a Q-factor of 13.9. The self-resonant frequency (SRF) occurs at approximately 9 GHz, well beyond the target operation bandwidth (0.17 to 2.68 GHz). Two-tone tests with 10 MHz spacing were performed at 2.4 GHz, and as shown in Figure 16, an intercept point three (IIP3) of −14.9 dBm was obtained. As mentioned in the noise and linearity analysis section, M₄ improves both NF and linearity. To verify this, NF and IIP3 were simulated under two conditions, as illustrated in Figure 17a,b. The first case involves connecting the gate terminal of M₄ to the input, where M₄ operates as a CS amplifier, implementing the noise and distortion cancellation mechanism. The second case considers M₄ functioning solely as a current source for the second stage. Figure 18 compares the NF for both modes. Based on Equations (4) and (5) and simulation results, it is clear that when M₄ is connected to the input, the noise voltage at the first stage output is decreased and the NF improves. The IIP3 across the entire bandwidth was also simulated using two-tone tests with 10 MHz spacing, both with and without M₄. Figure 19 shows the IIP3 versus frequency. Similar to the NF analysis, IIP3 improves when M₄ is included. Equation (5) can be also used for distortion cancellation since the harmonic produced at node A can be cancelled similarly to the noise generated at node A.

Table 1. Corners and temperature simulation results.

Parameter	TT @ 27 °C	SS @ 85 °C	FF @ −40 °C
−3 dB BW (GHz)	0.17–2.68	0.17–2.2	0.17–2.54
S21 (dB)	15–17.24	13.58–15.58	15.2–18.2
NFmin (dB)	2.67	3.35	1.99
IIP3 (dBm)	−14.9	−13	−12.6
Power (mW)	3.52	3.64	2.87

summarizes the performance results of the proposed wideband LNA across different corners and temperatures. Although the proposed LNA shows slight variations under different corner conditions, it demonstrates robust performance against both corner and temperature variations.

Table 2. Performance comparison with several recent similar works.

Reference	CMOS Process	VDD (V)	Frequency (GHz)	S21 (dB)	NF (dB)	S11 (dB)	IIP3 (dBm)	Symmetric Load	Power (mW)	Area (mm2)	FoM (dB)
TCAS-II′22 *,b [8]	65 nm	1.5	0.47–3.3	19.45–22	2.57–3.5	<−10	+2.81	Yes	12.5	0.057	11.02
TCAS-I′19 b [9]	65 nm	2.2	0.05–1	24–30	2.3–3.3	<−12	−4.1	Yes	19.8	0.045	6.84
TCAS-I′20 b [10]	65 nm	1	0.05–1.3	24–27.5	2.3–3	<−12	−2.2	Yes	5.7	0.046	17.73
TCAS-II′21 b [11]	180 nm	1.8	0.13–0.93	16.6–19.6	3.6–5	<−10	−8.5	Yes	3	0.18	6.52
AEUE′19 *,b [12]	180 nm	1.2	0.18–2	15–20.8	2.65–3.8	<−8	−4.91	Yes	4.9	0.04	13.7
TCAS-I′24 b [13]	65 nm	0.78	0.1–4.2	15.6	4.45–6.9	<−10	−14.5	No	0.96	0.011	23.19
MWT′25 [14]	28 nm	1.1	0.2–3.2	24.4–26	1.4–2.18	<−15	−3.6	Yes	17.4	0.018	19.13
TCAS-I′24 b [15]	28 nm	0.6	0.2–2.85	20	2.9–3.6	<−13	−12.3	No	1.74	0.0048	24.19
TCAS-II′25 b [16]	130 nm	1.3	0.01–1.7	21.5	1.1–1.9	<−10	−2.3	Yes	9.1	0.18	17.45
This work *	65 nm	1	0.17–2.68	15–17.24	2.67–3.24	<−10	−14.9	No	3.52	0.3	15.7

* Post-layout simulation results. ^b needs buffer to measure.

presents a comparison with state-of-the-art designs, benchmarking the proposed LNA against similar recent works. The Figure of Merit (FoM) is calculated as follows [15]:

$$FOM=20{\log }_{10}\left({\displaystyle \frac{S_{21}[\mathrm{abs}]\hspace{0.17em}·\hspace{0.17em}B{W}_{-3\mathrm{dB}}[\mathrm{GHz}]}{P_{DC}\hspace{0.17em}[\mathrm{mW}]\hspace{0.17em}·\hspace{0.17em}(F_{\min }-1)}}\right)$$

(9)

Excluding [14], which achieves complete output impedance matching, other cited references have reported only the LNA core power consumption, resulting in higher FoM values than the proposed circuit. Only [11] includes the output buffer power of 9 mW, which would significantly reduce its FoM if properly accounted for. In comparison, the proposed LNA achieves output matching without requiring a buffer. Due to the combined circuits approach used in the proposed low-power design, the occupied die area is larger than other cited references. For example, two stages of the proposed circuit are isolated by large MIMCAPs. Although the proposed circuit occupies a large area, one advantage of the implemented topology is that it performs output impedance matching without requiring high power consumption.

4. Conclusions

In this paper, a low-power wideband single-ended LNA is analyzed. The proposed LNA covers frequency ranges from 0.17 to 2.68 GHz and is suitable for low-power multi-standards wireless applications. Two-stage amplifier implementation shares the same DC current bias and uses large MIMCAPs for isolation. A noise and distortion cancellation technique are employed to improve both NF and linearity. The circuit was simulated using Cadence Spectre-RF in 65 nm CMOS technology. Post-layout simulation results demonstrate acceptable performance with low power consumption, validating the theoretical analysis. Furthermore, the proposed LNA achieves full output matching without requiring an additional buffer, thereby reducing overall power consumption and making it particularly suitable for low-power applications.