Design of a Linear Floating Active Resistor with Low Temperature Coefficient

Abstract

This paper presents the design and implementation of a linear, stable, low-power and PVT insensitive floating active resistor, which is realized using TSMC 40 nm CMOS process technology. By incorporating the automatic tuning circuit, this work has achieved improved performance metrics, which include low process sensitivity, reduced temperature coefficient, and good linearity. Monte Carlo (MC) simulations are conducted to evaluate the active resistor’s performance under variations in temperature, process, and supply voltage. The proposed design has demonstrated an average resistance process sensitivity of 0.64%, a temperature coefficient (T.C.) of 57 ppm/°C across −25 °C to 85 °C, and a linearity figure of merit (FOM) of 2.4 × 10⁻² V⁻¹ with a resistance close to MΩ level. It can achieve a linear resistance tuning range of 430.5 kΩ to 1.714 MΩ. The typical power consumption of a single active resistor is 0.25 µW at 2.1 V bootstrapped supply voltage through a Dickson charge pump (DCP) circuit using a DC input of 1 V. These results have confirmed that the proposed active resistor can function as a robust and efficient resistor for low-voltage integrated circuits and systems.

1. Introduction

In analog CMOS integrated circuit design, high-accuracy components are required to ensure reliable performance across diverse applications. Resistors, as fundamental components, are critical in determining the precision of integrated circuits (ICs) for applications such as such as voltage and current reference circuits, analog filters, oscillators, programmable amplifiers and so forth. However, the use of traditional passive resistors in integrated circuits will display variations in both manufacturing tolerance as well as temperature sensitivity, thus limiting their applicability in precision designs [1,2,3,4,5]. Polysilicon resistors, often used in CMOS processes, have typical sheet resistance deviations of ±20%, making them unsuitable for high-accuracy applications without extensive trimming [1,6]. Moreover, the value of polysilicon resistors is fixed and not tunable [7]. Another critical limitation of passive resistors is the requirement for large chip area to achieve high resistance values, especially in ultra-low-power applications. This is particularly pronounced with a large scale of high-resistance resistors being employed in the design. As a result, such an increase leads to inefficient use of chip area and higher fabrication costs [3,8].

To address these issues, this paper addresses the design of a MOSFET-based active resistor in conjunction with the automatic tuning circuit. This brings the benefits of maintaining good linearity, reducing temperature sensitivity and suppressing wide process variation characteristics through the variation of the transistor’s parameters. As a result, the proposed active resistor can serve as a potential replacement for passive resistors in low-power voltage reference, current reference circuits and other analog circuit building blocks. This offers greater adaptability and improved stability in precision analog applications [6,9,10,11]. Furthermore, active resistors exhibit improved stability with respect to temperature and process variations and can be integrated using standard CMOS processes without the need for additional trimming circuits, which can reduce complexity and cost [8,12].

Regarding previous works, ref. [3] achieves ultra-low power and high resistance but it suffers from relatively lower linearity and larger T.C. due to mismatches in devices. This mismatch prevents the active resistor from fully replicating the resistance in the triode region because the triode transistors are sensitive to transistor parameters in variation. Meanwhile, ref. [6] offers relatively lower process sensitivity and a reduced T.C. but at the expense of increased circuit complexity. Its reliance on a differential difference amplifier (DDA) for control voltage generation introduces high circuit complexity and increased biasing current, resulting in greater power consumption. This raises the motivation for the investigation and the design of a floating active resistor with improved performance. Not only does it have low power consumption through the circuit simplicity in architecture, but it also provides low T.C. whilst offering good stability against PVT variation.

Section 1 presents the introduction. Section 2 presents the review of the representative active resistors. Section 3 details the proposed floating active resistor topology together with the automatic tuning circuit. Section 4 discusses the simulation results. Section 5 gives the conclusion.

2. Review of Representative Active Resistor

2.1. Parallel Compensated Active Resistor

A floating voltage-controlled resistor in CMOS technology with the method of nonlinearity cancellation is shown in Figure 1.

To achieve a floating voltage-controlled resistor, the work in [1] first analyzes the drain current characteristics of a MOS transistor operating in the triode region.

$$\begin{array}{cc}{I}_D=& -\mu C_{ox}{\displaystyle \frac{W}{L}}\left\{\left(V_G-V_B-V_{FB}-2{\Phi }_F\right)\left(V_D-V_S\right)-{\displaystyle \frac{1}{2}}\left[{\left(V_D-V_B\right)}^2-{\left(V_S-V_B\right)}^2\right]\right\}\hfill \\ & +{\displaystyle \frac{2}{3}}\mu C_{ox}{\displaystyle \frac{W}{L}}\gamma \left\{{\left(-V_D+V_B-2{\Phi }_F\right)}^{{\displaystyle \frac{3}{2}}}+{\left(-V_S+V_B-2{\Phi }_F\right)}^{{\displaystyle \frac{3}{2}}}\right\}\hfill \end{array}$$

(1)

where V_G, V_S, V_D, V_B are the gate, source, drain and substrate voltage with respect to ground, W and L are the gate width and length, μ is the effective mobility in the channel, C_ox is oxide capacitance per unit area, V_FB is the flat band voltage, Φ_F is the substrate Fermi potential and γ is the body effect coefficient. If γ is considered to be small enough, the body effect can be neglected.

The primary nonlinearity comes from the quadratic term in the drain current equation. The cubic term in general is much smaller than the quadratic term. To tackle the non-linearity problem, a parallel compensated resistor [1] scheme is proposed. Two identical MOS devices with their channels connected in parallel and their gate voltages are biased by a respective dc voltage V_C and coupled with ac voltages, V_D and V_S, through two source followers. Referring to [1], we have

$$\begin{gathered} V_{GA}=V_C+V_D \\ {V}_{GB}=V_C+V_S \end{gathered}$$

(2)

Assuming body effect is negligible and applying the substrate voltage V_B, the two current expressions are given as follows:

$$I_{1A}=\mu C_{ox}{\displaystyle \frac{W}{L}}\left\{\left(V_C-\left|V_{TH}\right|\right)V_{SD}-{\displaystyle \frac{1}{2}}{V_{SD}}^2\right\}+{\displaystyle \frac{2}{3}}\mu C_{ox}{\displaystyle \frac{W}{L}}\gamma \left\{{\left(-V_D+V_B-2{\Phi }_F\right)}^{{\displaystyle \frac{3}{2}}}+{\left(-V_S+V_B-2{\Phi }_F\right)}^{{\displaystyle \frac{3}{2}}}\right\}$$

(3)

$$I_{1B}=\mu C_{ox}{\displaystyle \frac{W}{L}}\left\{\left(V_C+V_{SD}-\left|V_{TH}\right|\right)V_{SD}-{\displaystyle \frac{1}{2}}{V_{SD}}^2\right\}+{\displaystyle \frac{2}{3}}\mu C_{ox}{\displaystyle \frac{W}{L}}\gamma \left\{{\left(-V_D+V_B-2{\Phi }_F\right)}^{{\displaystyle \frac{3}{2}}}+{\left(-V_S+V_B-2{\Phi }_F\right)}^{{\displaystyle \frac{3}{2}}}\right\}$$

(4)

The summed current ID is obtained as

$$\begin{array}{cc}\hfill I_D& =I_{1A}+I_{1B}\hfill \\ & =\mu C_{ox}{\displaystyle \frac{W}{L}}\left\{2\left(V_C-\left|V_{TH}\right|\right)V_{SD}+{\displaystyle \frac{1}{2}}{V_{SD}}^2-{\displaystyle \frac{1}{2}}{V}_{SD}^2\right\}+{\displaystyle \frac{4}{3}}\mu C_{ox}{\displaystyle \frac{W}{L}}\gamma \left\{{\left(-V_D+V_B-2{\Phi }_F\right)}^{{\displaystyle \frac{3}{2}}}+{\left(-V_S+V_B-2{\Phi }_F\right)}^{{\displaystyle \frac{3}{2}}}\right\}\hfill \\ & =2\mu C_{ox}{\displaystyle \frac{W}{L}}\left(V_C-\left|V_{TH}\right|\right)V_{SD}+{\displaystyle \frac{4}{3}}\mu C_{ox}{\displaystyle \frac{W}{L}}\gamma \left\{{\left(-V_D+V_B-2{\Phi }_F\right)}^{{\displaystyle \frac{3}{2}}}+{\left(-V_S+V_B-2{\Phi }_F\right)}^{{\displaystyle \frac{3}{2}}}\right\}\hfill \end{array}$$

(5)

where $\left|V_{TH}\right|$ represents the absolute threshold voltage of PMOS M_1A and M_1B. Through Taylor expansion of equation, the small-signal conductance between D and S becomes

$$R_{DS}\left(V_C\right)\approx {\displaystyle \frac{L}{2\mu C_{ox}W\left(V_C-\left|V_{TH}\right|\right)}}$$

(6)

This arrangement effectively cancels the dominant even order nonlinearity and the odd order non-linearity is assumed to be small and ignored. As observed from Equation (6), the equivalent resistance is approximately linear. However, the second-order effects such as bulk modulation, mobility degradation and mismatch with transistor pair M_1A–M_1B will degrade the non-linearity.

2.2. Floating Active Resistor with Common-Mode Generator Incorporating Bulk Effect

An alternative floating active resistor [2] is proposed and depicted in Figure 2. For a single triode transistor, the drain current expression is

$$I_D={\mu }_n{C}_{ox}{\displaystyle \frac{W}{L}}\left\{{\alpha }_1\left(V_D-V_S\right)+{\alpha }_2{\left(V_D-V_S\right)}^2+{\alpha }_3{\left(V_D-V_S\right)}^3\right\}$$

(7)

where

$$\begin{array}{c}{\alpha }_1=V_G-V_{th}\hfill \\ {\alpha }_2=-{\displaystyle \frac{1}{2}}\left(1+{\displaystyle \frac{\gamma }{2\sqrt{2{\Phi }_F+V_{SB}}}}\right)\hfill \\ {\alpha }_3={\displaystyle \frac{\gamma }{24\sqrt{{\left(2{\Phi }_F+V_{SB}\right)}^3}}}\hfill \end{array}$$

(8)

with

$$V_{th}=V_{th0}-\gamma \sqrt{2{\Phi }_F}+\gamma \sqrt{2{\Phi }_F+V_{SB}}$$

(9)

where V_D, V_S, V_G, V_B represent the drain, source, gate and bulk potential, respectively. W and L are the gate width and length, μ_n is the effective mobility in the channel, C_ox is oxide capacitance per unit area. Φ_F is the substrate Fermi potential and γ is the body effect coefficient. V_T0 is the threshold voltage at zero bias.

The main nonlinearity is caused by the quadratic term in the drain current equation, whilst the cubic term can be neglected due to the small value in general. To mitigate this, a specific gate voltage, taking into account the induced body effect within the common-mode voltage as the compensation term, is applied to the gate of the active resistor transistor M₆. Hence, we have

$$V_{G6}=V_C+V_{th5}+\left[1+{\displaystyle \frac{\gamma }{2\sqrt{2{\Phi }_F+V_{SB5}}}}\right]V_{CM}$$

(10)

where V_CM is the common-mode voltage generated through M₁–M₄ without any body effect. It is defined as

$$V_{CM}={\displaystyle \frac{V_D+V_S}{2}}$$

(11)

and V_C is the dc bias voltage component generated using the level shifter. This is formed by M₅ with a constant biasing current of 2I in conjunction with the common-mode generator. When M₅ works in the saturation region and is subjected to bulk modulation though arranging V_SB5 ≠ 0, the gate potential becomes

$$V_{G5}=V_{D5}=V_{G6}=\sqrt{{\displaystyle \frac{2\left(2I\right)}{K_5}}}+V_{th5}+\left[1+{\displaystyle \frac{\gamma }{2\sqrt{2{\Phi }_F+V_{SB5}}}}\right]V_{CM}$$

(12)

where

$$V_{th5}=V_{th0}+\gamma \left(\sqrt{2{\Phi }_F+V_{CM}+V_{SS}}-\sqrt{2{\Phi }_F}\right)$$

(13)

The substrate voltage is fixed as −V_SS and the source-bulk voltage of M₅ is

$$V_{SB5}=V_{CM}+V_{SS}$$

(14)

By substituting Equations (12)–(14) into Equation (7) and assuming that the cubic term is negligible, the drain current of the active resistor M₆ is obtained as

$$I_{D6}\approx 2K_6\sqrt{{\displaystyle \frac{4I}{K_5}}}{V}_{DS6}$$

(15)

Through the bulk induced common-mode voltage, the approach further eliminates the residual quadratic distortion term in the drain current, significantly improving linearity. The equivalent resistance of the active resistor M₆ is approximated as

$$R_6\approx {\displaystyle \frac{1}{2K_6\sqrt{\frac{4I}{K_5}}}}$$

(16)

The key achievement of this design is further reduction in nonlinearity arising from bulk modulation of V_th. As a result, the design ensures that the resistance value remains stable and independent of input voltage. This has illustrated its potential as an economic alternative with respect to other schemes used for applications requiring good linearity. Furthermore, the single active transistor eliminates the need of matching two transistors or more in the compensation process. Since it is relatively insensitive to mismatch effect, its technical merit is identified. Despite its strengths, the design also has certain limitations. The resistor’s performance will be degraded by mobility degradation that leads to odd order distortion. The circuit requires high supply voltage (±5 V) to sustain the operation. The common-mode generator also consumes significant power. This is not favorable when a large scale of active resistors is employed in low-power circuits and systems.

2.3. Grounded Active Resistor with Pre-Distortion Compensation

Another active resistor [3], which is aimed for use as a ground resistor, is depicted in Figure 3. The circuit consists of one main triode active transistor, M_R, the replica triode transistors, M₁ and M₃, the saturation-based voltage mirror transistor pair M₂ and M₄, one operational amplifier (op-amp) and the pre-distortion block that comprises weak-inversion-based transistors M₅–M₈ with identical size and an independent current source I_B.

Through the clamping function of op-amp and identical matching design for M₂ with M₄, M_R with M₁ and M₃, the relationship is established as follows:

$$\begin{array}{cc}\hfill V_{DR}& =V_{D1}\Rightarrow V_{DSR}=V_{DS1}\hfill \\ \hfill I_R& =I_{D3}=I_{D1}\hfill \end{array}$$

(17)

As can be observed, $I_{D4}=I_{D8}$ comes from the translinear loop [3] which is established among the transistors M₅–M₆ with a relationship of

$$V_{GS5}+V_{GS7}=V_{GS6}+V_{GS8}$$

(18)

This yields

$$I_{D8}=I_C={\displaystyle \frac{I_R^2}{I_B}}$$

(19)

where I_C is the compensated current coming from the pre-distortion block. This is forced to be equal to that of I_D1 as drawn by the resistor network, which is formed by the nested configuration between the saturation transistor M₂ and the triode transistor M₁. Through the analysis of the network involving M₁ and M₂, we obtain

$$I_{D1}={\mu }_n{C}_{ox}{\left({\displaystyle \frac{W}{L}}\right)}_1\left[\left(V_{GS1}-V_{th1}\right)V_{DS1}-{\displaystyle \frac{1}{2}}{V_{DS1}}^2\right]$$

(20)

$$I_{D2}={\displaystyle \frac{1}{2}}{\mu }_n{C}_{ox}{\left({\displaystyle \frac{W}{L}}\right)}_2{\left(V_{GS2}-V_{th1}\right)}^2$$

(21)

and

$$V_{GS2}=V_{DS2}=V_{D2}-V_{S2}=V_{G1}-V_{D1}=V_{GS1}-V_{DS1}$$

(22)

Combining Equations (20)–(22), we have

$$I_{D1}={\displaystyle \frac{1}{2}}{\mu }_n{C}_{ox}{\left({\displaystyle \frac{W}{L}}\right)}_1{\displaystyle \frac{1}{1+k_{1,2}}}{\left(V_{GS1}-V_{th1}\right)}^2$$

(23)

where k_1,2 is defined as

$$k_{1,2}={\displaystyle \frac{{\left({\displaystyle W/L}\right)}_1}{{\left({\displaystyle W/L}\right)}_2}}$$

(24)

Similarly, we have the relation that

$$I_{D3}=I_{D4}=I_R=I_{D2}=I_{D1}=I_{D8}$$

(25)

By substituting I_D1 of Equation (23) into Equation (20), this gives

$$V_{DS1}^2+\left(2V_{th1}-2V_{GS1}\right)V_{DS1}+{\displaystyle \frac{1}{1+k_{1,2}}}{\left(V_{GS1}-V_{th1}\right)}^2=0$$

(26)

Solving V_DS1 in the quadratic Equation (26), we have

$$V_{DS1}=\left(1\pm \sqrt{{\displaystyle \frac{k_{1,2}}{1+k_{1,2}}}}\right)\left(V_{GS1}-V_{th1}\right)$$

(27)

The root term $\left(1+\sqrt{{\displaystyle \frac{k_{1,2}}{1+k_{1,2}}}}\right)\left(V_{GS1}-V_{th1}\right)$ is discarded because the condition for M₁ to be biased in the triode region is based on the condition that $V_{DS1}<V_{GS1}-V_{th1}$. Hence, the remaining root term for V_DS1 is obtained as

$$V_{DSR}=V_{DS1}=\left(\sqrt{1+k_{1,2}}-\sqrt{k_{1,2}}\right)\sqrt{{\displaystyle \frac{I_{D1}}{{\displaystyle 1/2}{\mu }_n{C}_{ox}{\displaystyle W_1/L_1}}}}$$

(28)

and the effective resistance of the active resistor becomes

$$R_{ActR}\approx R_{M1}={\displaystyle \frac{V_{DS1}}{I_R}}={\displaystyle \frac{\left(\sqrt{1+k_{1,2}}-\sqrt{k_{1,2}}\right)\sqrt{\frac{I_{D1}}{{\displaystyle 1/2}{\mu }_n{C}_{ox}{\displaystyle W_1/L_1}}}}{I_R}}$$

(29)

By substituting I_C from Equation (19) into Equation (29), we obtain

$$R_{ActR}\approx \left(\sqrt{1+k_{1,2}}-\sqrt{k_{1,2}}\right)\sqrt{{\displaystyle \frac{1}{{\displaystyle 1/2}{\mu }_n{C}_{ox}{\displaystyle W_1/L_1{I}_B}}}}$$

(30)

As can be seen, through the independent design of separate bias current source IB, the stability of the resistor is translated to the stability of bias current source. The resistance of the active resistor becomes a stable, predictable value, unaffected by variations in the input current. Nevertheless, the key disadvantages of the resistor are not allowed to support floating resistor applications and the relatively high temperature coefficient (T.C.). This stems from the that fact that the performance of resistor topology relies on the matching among transistor group pairs such as triode transistors, sub-threshold transistors in the translinear loop. Different degrees of mobility degradation effect among the triode devices also contribute to the linearity issue.

3. Proposed Floating Active Resistor

3.1. Core Active Resistor Circuit

The proposed design distinguishes itself through its method of generating the common-mode voltage to ensure the effectiveness of the active resistor and the cancellation of second-order terms. Referring to Figure 4, the floating resistor consists of the common-mode generator formed by the transistors M₃–M₄, a self-cascade composite transistor (SCCT) source follower formed by the transistors M₇–M₈ and the current bias I_bias, and a native cascade transistor M₀ comprising M₁ and M₂. The active resistor’s gate bias voltage is given as follows:

$$\begin{array}{cc}\hfill V_G& =V_C+V_{CM}\hfill \\ \hfill V_{CM}& =m{\displaystyle \frac{V_D+V_S}{2}}\hfill \end{array}$$

(31)

where V_G is the tuned DC gate voltage applied to gate of the cascade transistor M₀. V_CM is the intermediate mid-point AC voltage obtained from the common mode generator. The parameter m [13,14] is given.

$$m=1+{\displaystyle \frac{\gamma }{2\sqrt{2{\Phi }_F+V_S}}}$$

(32)

The proposed design makes use of an NMOS native transistor as the active resistor, and hence, its bulk connection to the substrate will cause the body effect. Nevertheless, the body effect coefficient γ is usually small due to the lightly doped substrate. As a result, $m\approx 1$, and this yields

$$V_{CM}\approx {\displaystyle \frac{V_D+V_S}{2}}$$

(33)

Therefore, it is imperative to evaluate and compare the respective threshold voltage and respective body effect coefficient among the native transistor, LVT transistor and HVT transistor. The characterization involves grounding the bulk terminal and varying the source voltage V_SB to observe the resulting change in threshold voltage V_th. Furthermore, the calculation of γ for a single transistor is given as

$$\gamma ={\displaystyle \frac{V_{th}\left(V_{SB}\right)-V_{th0}}{\sqrt{V_{SB}+2{\Phi }_F}-\sqrt{2{\Phi }_F}}}$$

(34)

where V_th (V_SB) represents the threshold voltage of the MOS transistor under a given source-bulk voltage V_SB and V_th0 is the threshold voltage when V_SB is zero and temperature is absolute zero. For native, LVT, and HVT NMOS transistors, V_th0 is equal to −158.4 mV, 340.1 mV and 397.2 mV, respectively. Φ_F is the Fermi potential of the semiconductor, which is related to the doping concentration and temperature.

Figure 5a illustrates the variation of the threshold voltage V_th with respect to the source-bulk voltage V_SB. As observed, the V_th of the native transistor changes the least as V_SB varies when compared to other transistor types. Similarly, Figure 5b shows the relationship between the body-effect coefficient γ and V_SB. At $V_{SB}=0.3V$, the native transistor shows a γ value of approximately $23m\sqrt{V}$, which is significantly smaller than the values of LVT and HVT transistors, at $186m\sqrt{V}$ and $207m\sqrt{V}$, respectively. These results demonstrate that using native transistors effectively minimizes the impact of the body effect and facilitates the generation of a more precise and simplified common-mode voltage.

In addition, the long channel length L of the native transistor allows the realization of MΩ resistance level. With such a large L, the short-channel length effect can be effectively neglected. However, since the channel length cannot be infinitely increased due to physical and process limitations, a cascaded configuration of two native transistors is employed to further enhance the resistance value. This approach provides a practical and efficient method to achieve higher resistance without compromising performance significantly.

The voltage V_CM is achieved by using diode-connected PMOS transistors in the cutoff region as the pseudo-resistors (PRs) with extremely large resistance, where the drain-source current is negligible [15,16]. As depicted in Figure 6, the PR group, which is arranged in symmetrical topology, is used to generate the common-mode voltage V_CM instead of a single pair of pseudo-resistors.

When V_SG > 0, each PR behaves as a diode-connected PMOS transistor. To ensure that the transistor operates in either the cutoff region or the subthreshold region, the condition V_SG < |V_THP| must be satisfied. Under this condition, the transistor conducts only a few nA or even pA of current, resulting in an extremely high equivalent resistance for the PR. Consequently, the voltage drop across the PR remains negligible. When V_SG < 0, the parasitic drain–n-well–source junction forms an unintentional pnp bipolar junction transistor (BJT), which can become activated. In this scenario, the PR behaves similarly to a diode-connected BJT [17,18]. However, since V_D varies between 0 and 1 V while V_S is fixed at 0.5 V, the maximum potential drop across a single PR is 0.25 V. This voltage is insufficient to forward-bias the parasitic diode, preventing significant conduction. As a result, the current remains extremely low, ensuring that the PR continues to function as a high-resistance element.

The small level drain-source current across each PR and the total leakage current I_leak are illustrated in Figure 7 with the change of the input signal, respectively. As observed, the leakage current is small enough to be negligible. Thus, the voltage drop across the transistors is nearly zero, leading to an intermediate voltage, which is almost half of the drain-source voltage.

The common-mode voltage V_CM is plotted against the change of the input voltage V_D from 0 to 1 V, as depicted in Figure 8. Since V_S is fixed at 0.5 V, the value of V_CM remains approximately equal to ${\displaystyle \frac{V_D+V_S}{2}}$. The simulation results have validated a good common-mode generator using the symmetrical PR network.

V_C is the DC voltage generated by level shifter formed by transistors M₇–M₈ and I_bias, which is also called self-cascade composite transistor. SCCT structure is formed by M₇ operating in the triode region and M₈ operating in the saturation region, to enhance the performance of the source follower through addressing the key limitation on the short-channel effect [19,20]. The SCCT structure operates by utilizing M₇ as a triode degeneration resistor to increase the bias voltage for the active resistor whilst increasing the output resistance of M₈, which works in the saturation region. Thus, we have

$$V_G=V_{CM}+\sqrt{{\displaystyle \frac{2I_{bias}}{K_{M8}}}}+\left|V_{th8}\right|+I_{bias}{R}_{DS7}$$

(35)

$$R_{DS7}\approx {\displaystyle \frac{1}{K_{M7}\left(\left|V_{GS7}\right|-\left|V_{th7}\right|\right)}}$$

(36)

$$V_C=\sqrt{{\displaystyle \frac{2I_{bias}}{K_{M8}}}}+\left|V_{th8}\right|+I_{bias}{R}_{DS7}$$

(37)

As can be seen in Equation (37), by adjusting the bias current I_bias, V_C can be tuned to compensate the active resistor under PVT fluctuation. By applying the automatic tuning circuit, the current source I_bias will be replaced by the tuning current source I_tune from the automatic tuning circuit, which will be discussed in the next section. The gate control bias voltage becomes

$$V_C=\sqrt{{\displaystyle \frac{2I_{tune}}{K_{M8}}}}+\left|V_{th8}\right|+I_{tune}{R}_{DS7}$$

(38)

Based on the triode transistor expression, we have

$$I_D\approx {\mu }_n{C}_{ox}{\displaystyle \frac{W}{L}}\left\{a_1\left(V_D-V_S\right)+a_2{\left(V_D-V_S\right)}^2+a_3{\left(V_D-V_S\right)}^3\right\}$$

(39)

Due to the use of native transistor M₁–M₂, V_B is always equal to zero. This leads to $V_{SB}=V_S$. Thus, this gives

$$\begin{array}{c}{a}_1=V_G-V_{th}\hfill \\ a_2=-{\displaystyle \frac{1}{2}}\left(1+{\displaystyle \frac{\gamma }{2\sqrt{2{\Phi }_F+V_S}}}\right)\hfill \\ a_3={\displaystyle \frac{\gamma }{24\sqrt{{\left(2{\Phi }_F+V_S\right)}^3}}}\hfill \end{array}$$

(40)

$$V_{th}=V_{th0}+\gamma \left(\sqrt{2{\Phi }_F+V_S}-\sqrt{2{\Phi }_F}\right)$$

(41)

With the use of the native transistors M₁–M₂ as the core active resistor, the characterization results have shown that the body-effect coefficient γ is approximately $23m\sqrt{V}$. It indicates that γ is a very small value that can be neglected for approximation. Consequently, the control voltage is obtained as follows:

$$V_G\approx V_C+{\displaystyle \frac{V_D+V_S}{2}}$$

(42)

Hence, the drain current becomes

$$I_D\approx {\mu }_n{C}_{ox}{\displaystyle \frac{W}{L}}\left\{\left(V_G-V_{th}\right)\left(V_D-V_S\right)-{\displaystyle \frac{1}{2}}{\left(V_D-V_S\right)}^2\right\}$$

(43)

where the cubic term is ignored due to its small value. For the triode region, the terminal condition is given as

$$V_G-V_{th}>V_{DS}$$

(44)

With $V_G\approx V_C+{\displaystyle \frac{V_D+V_S}{2}}$, the linearized resistance is obtained as

$$R_{eq}\approx {\displaystyle \frac{L}{{\mu }_n{C}_{ox}W\left(V_C-V_{th}\right)}}$$

(45)

It suggests that the resistance is dependent on the input voltage.

Table 1. Device types and sizes of the proposed active resistor.

Component	Model	Size (W/L)	Multiplier
M1–2	nch_na25_mac	1.5/200 (µm/µm)	1
M3–6	pch_25_mac	120/600 (nm/nm)	5
M7–8	pch_25_mac	0.5/10 (µm/µm)	1
M9	pch_25_mac	2/8 (µm/µm)	1
M10	pch_25_mac	1.8/8 (µm/µm)	1
M11	pch_25_mac	16/4 (µm/µm)	1

lists the sizes and types of components used in the proposed active resistor.

3.2. Proposed Automatic Tuning Circuit

The proposed active resistor topology incorporates a new automatic tuning circuit designed to dynamically stabilize resistance under variations in PVT [9,21,22,23]. As shown in Figure 9, the topology combines a dual operational amplifier configuration with each consuming 500 nA supply current, a reference voltage V_ref, current sources formed by M₉, M₁₀, and M₁₁ and two compensation MOS capacitors [24] C₁ and C₂ used to stabilize the two amplifiers.

These two capacitors not only provide a frequency compensation function, but they also suppress the high-frequency transients in the feedback loops since the disturbances come from the supply line. As a result, they stabilize overall circuit performance in the presence of ripple at the supply line. These capacitors with parallel configuration are shown in Figure 10. The unit capacitor for the compensation capacitor is 25 pF and N is the multiplier of the active capacitor.

The automatic tuning circuit is responsible for generating the tuning current I_tune, which dynamically adjusts the resistance of the active resistor against environmental, process-induced variations [21,22,23,25]. On top of that, two passive resistors with opposite T.C. are connected in series to achieve close to zero T.C. for the combined resistor R. The negative feedback mechanism ensures that the voltage across R is close to V_ref, through dynamically adjusting the output of the amplifier to produce I_tune1 according to the following relationship:

$$I_{tune1}={\displaystyle \frac{V_{ref}}{R}}=I_{ref}$$

(46)

This current is scaled down by the current source transistor M₁₀, with respect to M₉ by M times.

$$I_{tune2}={\displaystyle \frac{1}{M}}{I}_{tune1}$$

(47)

where M is the multiplier. Since both transistors M₉ and M₁₀ operate in the saturation region whilst employing long channel design, it permits I_tune2 to track well with the scaled I_ref. Due to the usual large resistance of MΩ level realized by the active resistor (ActR), the I_tune2 is made sufficiently small to avoid excessive voltage drops across ActR.

The loop₂ in the automatic tuning circuit plays a pivotal role in generating I_tune to provide adaptive current to bias and tune the active resistor against PVT variation. As a result, it provides a separate control whilst correlating with respect to I_tune1 and I_tune2. When the reference current I_tune2 flows into the ActR, a feedback voltage is established at V₋ and is compared with V_ref. The negative feedback adjusts its output to ensure that the tuning current I_tune is dynamically regulated by M₁₁, which works in the subthreshold region. This current serves as a replacement for the intrinsic bias current I_bias within ActR, as shown in Figure 4. Through this action, variation of process parameters, such as transconductance and threshold voltage, etc., in the active resistor, are compensated such that the active resistance of ActR is tracked with the constant value of passive resistor R.

Moreover, I_tune1 (generated by M₉) and I_tune (generated by M₁₁) belong to different feedback loops, and their associated resistances are also different levels. M₉ and M₁₀ operate in the saturation region to provide stable mirror currents with respect to the reference current I_ref. On the other hand, M₁₁ operates in the sub-threshold region. It offers high transconductance g_m, which aims to increase the feedback loop gain for loop control at low current level design in the context of minimizing the power consumption. As shown in Figure 9, the current source transistor M₁₇ further copies the current I_tune from the transistor M₁₁. This is used to bias the ActR. This configuration enables the realization of a fully floating active resistor.

Table 2. Size of components in automatic tuning.

Component	Model	Size (W/L)	Multiplier
M9	pch_25_mac	2 µm/8 µm	10
M10	pch_25_mac	1.86 µm/8 µm	3
M11	pch_25_mac	16 µm/4 µm	10
R1	rnpoly_wo	68 kΩ	-
R2	rppoly_wo	185 kΩ	-
C0	nch_25_dnw_mac	50/45 (µm/µm) 25 pF	1
C1–2	nch_25_dnw_mac	4 × C0 = 100 pF	4

lists the size of components in the automatic tuning circuit.

As illustrated in Figure 11, the op-amp consists of three main parts: the start-up circuit, the bias circuit, and the core circuit. Each sub-circuit plays a critical role in ensuring the proper functioning of the op-amp, which is used in the automatic tuning circuit to clamp the two input voltages (V₊ and V₋) to the same level, a necessary condition for maintaining stable and precise operation.

The start-up circuit, comprising M_P6 and M_P7, and the capacitor C_S, is designed to ensure that the bias circuit initializes correctly during power-up. In many self-biasing circuits, there is a risk of the system entering a metastable state where the current through the circuit is zero, preventing the bias circuit from functioning. This is called the degenerating point. The start-up circuit injects an initial current to avoid this uncertainty and to get rid of the degenerating point. The capacitor C_S ensures that the start-up mechanism is transient, allowing the bias circuit to take over in steady-state operation once the system stabilizes itself. As such, the start-up circuit does not add extra power consumption.

The bias circuit consists of transistors M_P3, M_P4, M_N5, M_N6, and the resistor R₃. This loop generates the bias current I_bias for the op-amp. The transistors M_N5 and M_N6, along with R₃, form a self-regulating feedback loop. The resistor R₃ sets the reference voltage that determines the bias current. The feedback ensures the voltage at the gate of M_P4 in stabilized condition, thereby setting a stable I_bias that is mirrored to the other part of the circuit. As a result, the op-amp operates in its active region, providing the required clamping functionality for V₊ and V₋.

Referring to the op-amp core circuit, it consists of M_P1, M_P2, M_P5, M_N1, M_N2, M_N3, M_N4, serving as one of the parts in the automatic tuning circuit. The op-amp’s primary role in the automatic tuning circuit is to clamp V₊ and V₋ to the same level. This is achieved through its open-loop gain of 47.1 dB, which ensures a small difference between V₊ and V₋ in application. This adjustment allows the op-amp to effectively maintain the stability and precision of the automatic tuning circuit. Additionally, the op-amp exhibits a PSRR of 94.3 dB, ensuring that variation in the supply voltage minimally affects its circuit performance. Furthermore, its CMRR of 62.4 dB enhances its ability to reject common-mode noise or disturbances in the input signal. The op-amp in the automatic tuning circuit has a bandwidth of 4.1 kHz, which is considered sufficient for low-frequency tuning and control applications. The simulation results are shown in Figure 12.

Table 3. Size of components in op-amp.

Component	Model	Size (W/L)	Multiplier
MN1–2	nch_25_mac	8 µm/2 µm	4
MN3–4	nch_25_mac	2 µm/1 µm	1
MP1–2	pch_25_mac	2 µm/4 µm	1
MP3–5	pch_25_mac	8 µm/4 µm	1
MP6–7	pch_25_mac	500 nm/1 µm	1
R3	rnpoly_wo	28 kΩ	-
R4	rppoly_wo	72 kΩ	-

illustrates the size of components in op-amp.

3.3. Dickson Charge Pump (DCP)

The proposed design needs a higher voltage supply required for the automatic tuning circuit to ensure that the native resistor is biased in the triode region and higher voltage supply for the op-amp, but the DC 1 V supply is insufficient. To address this issue, the voltage conversion circuit is essential to boost the supply voltage to meet operational requirements. Among the various DC-DC conversion techniques, DCP is widely used in such applications due to their compactness, ability to generate multiple voltage levels, and absence of bulky components, making them highly suitable for integration in modern CMOS circuits [26,27]. Moreover, by employing the charge pump, the design achieves insensitivity to the variation in the original V_DD supply voltage, ensuring stable performance across different supply conditions. To account for the variations caused by different process corners and temperature-induced degradation, the voltage level boosted by the charge pump can reach a maximum of 2.2 V. The exemplary output voltage of the charge pump is illustrated in Figure 13.

The operation of DCP can be described as a sequential process involving three key phases: charging, boosting, and voltage multiplication, as shown in Figure 14.

During the charging phase, when the first clock signal CLK₁ is active, the charge is transferred from one capacitor C_i to the next through the forward-biased MOS diodes, enabling the storage of charge along the capacitor chain. In the boosting phase, when the second clock signal CLK₂ (the inverted counterpart of CLK₁) is active, the boosted potential generated at the preceding stage is utilized to transfer additional charge to the subsequent stage, thereby incrementally increasing the voltage level [28]. This process is repeated across multiple stages of the charge pump, resulting in a progressive voltage multiplication. The output voltage at the final stage is approximately equal to the input voltage V_DD plus the cumulative contributions from each stage, which are determined by the amplitude of the clock signal minus any voltage drops due to parasitic resistances and threshold voltages of the MOS diodes [29]. This stepwise transfer and boosting process makes use of the capacitor voltage dynamics.

$$Q=C\Delta V$$

(48)

where Q represents the amount of electric charge stored on the capacitor plates and ΔV is the voltage difference across the capacitor’s plates. ΔV across a capacitor cannot change instantaneously due to the fixed Q in each step. This ensures stable and predictable voltage increments at each stage.

In the context of the proposed design, the ring oscillator serves as the clock generation unit, producing the biphasic signals CLK₁ and CLK₂ with a short non-overlapping period, as shown in Figure 15. This is achieved by incorporating a non-overlapping clock generation circuit. The frequency of the clock is 3.08 MHz. The non-overlapping clock generator ensures that two complementary clocks CLK₁ and CLK₂ do not overlap during their transitions. Overlapping between these clocks could result in short-circuit currents within the switches of the charge pump, reducing its efficiency and increasing power dissipation. The non-overlap period is introduced using a delay chain, typically implemented with cascaded inverters and NAND gates. Thus, the non-overlapping design is critical for ensuring the performance of switched-capacitor circuits [30].

However, it is important to note that the charge pump introduces inherent ripple into the boosted power supply, which can affect the performance of the circuit if the ripple is not well suppressed. To mitigate this issue, an integrated second-order RC low-pass filter comprising R₅C₆ and R₆C₇ is implemented, as shown in Figure 16.

This filtering effectively reduces the ripple voltage down to 2.54 mV, corresponding to a ripple coefficient of 0.18%, which is negligibly small enough to cause an impact on the circuit’s performance. The proposed DCP is designed to provide a voltage from a DC 1 V to a typical bootstrapped value of 2.1 V, providing power to the entire circuit. Under all process corners, the charge pump achieves a maximum output voltage of 2.2 V, delivering a maximum load current of 9.5 µA. This translates to drive an effective load of 231 kΩ.

Table 4. Device types and their sizes used in the DCP.

Component	Model	Size (W/L)	Multiplier
M12–16	nch_dnw_mac	50/1 (µm/µm)	10
NAND1–2	pch_mac & nch_mac	120/40, 120/40 (nm/nm)	1
Inv1–3	pch_mac & nch_mac	2.5/1.5, 1/5 (µm/µm)	1
Inv4–6	pch_mac & nch_mac	120/40, 120/40 (nm/nm)	1
Inv7–8	pch_mac & nch_mac	1/40, 1/40 (µm/nm)	1
Inv9–10	pch_mac & nch_mac	4/40, 4/40 (µm/nm)	1
Inv11–12	pch_mac & nch_mac	28/0.04, 28/0.04 (µm/µm)	1
C3–6	nch_25_dnw_mac	4 × C0 = 100 pF	4
C7–8	nch_25_dnw_mac	8 × C0 = 200 pF	8
R5–8	rnpoly_wo	1 kΩ	-
RL	rnpoly_wo	250 kΩ	-
IL	Current Source	9.5 µA	-

shows the component types, sizes and their values in the DCP design.

The resistance of the active resistor after integrating the DCP into the circuit is shown in Figure 17. As observed, the resistance of the active resistor with the charge pump introduced exhibits very minute fluctuations across the TT, SS, FF, SF, and FS process corners, with variations of approximately 2.2 kΩ, 3.7 kΩ, 2.1 kΩ, 2.7 kΩ, and 2.5 kΩ, respectively. To assess the impact of the fluctuation, their magnitudes were normalized based on the corresponding steady-state resistance value, resulting in variations of 0.24%, 0.35%, 0.29%, 0.30%, and 0.28%, respectively. The observed fluctuation is negligibly small. This indicates that the ripple-induced resistance variation in this design is insignificant and does not pose a concern for circuit performance.

4. Results and Discussions

The proposed active resistor, realized using TSMC 40nm CMOS technology, operates at a typical bootstrapped supply voltage of 2.1 V from the DC 1 V input voltage. To compare the variation of resistance with the input voltage, the linearity figure of merit (FOM) is defined as follows:

$$LinearityofFOM={\displaystyle \frac{1}{R_{nor}}}{\displaystyle \frac{R_{max}-R_{min}}{VoltageRange}}$$

(49)

It can be seen that the resistance variation is evaluated at different temperatures, such as −25 °C, 0 °C, 27 °C, and 85 °C. Then, the linearity of the resistance can be assessed. Figure 18 and Figure 19 show the results before and after applying the automatic tuning, respectively. The term ${\displaystyle \frac{R_{max}-R_{min}}{VoltageRange}}$ represents the resistance change with respect to the range of applied voltage. The smaller the value, the better the stability of the resistance. Dividing by R_nor ensures that the linearity measure is independent of the absolute value of resistance through normalization. This makes it suitable for comparing resistors at different nominal values.

In order to compare the linearity FOM numerical value with and without automatic tuning circuit, the calculated results at different temperatures are summarized in

Table 5. Simulated linearity FOM without and with automatic tuning circuit.

Linearity FOM (V−1)	Without Tuning Circuit	With Tuning Circuit
$Temp=-25 °\mathrm{C}$	$2.1\times {10}^{-2}$	$2.8\times {10}^{-2}$
$Temp=0 °\mathrm{C}$	$1.7\times {10}^{-2}$	$2.6\times {10}^{-2}$
$Temp=27 °\mathrm{C}$	$2.5\times {10}^{-2}$	$2.4\times {10}^{-2}$
$Temp=85 °\mathrm{C}$	$2.6\times {10}^{-2}$	$3.1\times {10}^{-2}$

.

The results have revealed that without the tuning circuit, the linearity FOM remains relatively stable across temperatures, ranging from $1.7\times {10}^{-2} {\mathrm{V}}^{-1}$ to $2.6\times {10}^{-2} {\mathrm{V}}^{-1}$, suggesting that the resistance variation with input voltage is within a reasonable range. With the tuning circuit, the variation of linearity FOM suggests that the resistance is dependent on the input voltage across most temperature conditions, but leads to some increase in nonlinearity at extreme temperatures of −25 °C and 85 °C, at $2.8\times {10}^{-2} {\mathrm{V}}^{-1}$ and $3.1\times {10}^{-2} {\mathrm{V}}^{-1}$, respectively. Nevertheless, the increase is within an acceptable range.

Furthermore, the resistance variation with temperature needs to be evaluated. This is achieved by controlling different drain-source voltages (V₁ − V₂), such as ±0.25 V, ±0.5 V, and ±0.75 V, while the resistance change over temperature is recorded. This setup also serves to demonstrate that the floating resistor can accommodate bidirectional signal flow, ensuring stable operation across varying input conditions. The ability to maintain consistent resistance characteristics in both positive and negative voltage scenarios further highlights its adaptability in practical applications. Figure 20 and Figure 21 illustrate the resistance variation without and with the automatic tuning circuit.

In order to compare the TC performance without and with the automatic tuning circuit, the calculated values are summarized in

Table 6. Simulated T.C. performance without and with automatic tuning circuit.

T.C. (ppm/°C)	Without Tuning Circuit	with Tuning Circuit
$V_1-V_2=0.25 \mathrm{V}$	$4.264\times {10}^3$	44.02
$V_1-V_2=-0.25 \mathrm{V}$	$4.262\times {10}^3$	44.17
$V_1-V_2=0.5 \mathrm{V}$	$4.270\times {10}^3$	57.28
$V_1-V_2=-0.5 \mathrm{V}$	$4.266\times {10}^3$	57.45
$V_1-V_2=0.75 \mathrm{V}$	$4.271\times {10}^3$	61.36
$V_1-V_2=-0.75 \mathrm{V}$	$4.271\times {10}^3$	61.23

.

Table 6 presents a comparison of T.C. before and after applying the automatic tuning circuit. Without the tuning circuit, the T.C. remains consistently high at about 4.3 × 10³ ppm/°C. This has confirmed significant high temperature sensitivity. However, with the tuning circuit, the T.C. is dramatically reduced to the worst maximum value of 61.36 ppm/°C, demonstrating an improvement by nearly two orders of magnitude. This significant reduction in T.C. highlights the effectiveness of the automatic tuning circuit in compensating for the variation of transistors’ parameters in the active resistor against temperature change. This permits the active resistor to maintain a stable resistance across different operating conditions.

The Monte Carlo (MC) simulation results of the proposed active resistor will reveal a statistical analysis of its resistance change against the temperature variation at different process corners. Figure 22 shows the MC simulation of the resistance, which is conducted over 800 samples, under TT, SS, FF, SF, and FS process corners at a bootstrapped supply voltage of 2.1 V.

The corresponding statistical data are summarized in

Table 7. ActR values under different process corners with automatic tuning.

	TT	SS	FF	SF	FS
σ (Ω)	5.72 k	6.93 k	4.48 k	5.75 k	5.68 k
μ (Ω)	887.41 k	1.05 M	716.19 k	886.63 k	888.20 k
σ/μ (%)	0.64	0.66	0.62	0.64	0.64

. With the automatic tuning circuit, the average resistance values for the TT, SS, FF, SF, and FS process corners are obtained as 887.41 kΩ, 1.05 MΩ, 716.19 kΩ, 886.63 kΩ, and 888.20 kΩ, respectively. These results have indicated a stable performance, with the resistance variation being well contained within acceptable ranges. The SS corner represents the extreme process conditions with the largest deviation from the nominal resistance. The SS corner corresponds to slower transistors with higher resistances, while the FF corner corresponds to faster transistors with lower resistances. The SF and FS corners with respect to the TT corner display a similar level of process sensitivity.

For the analysis of the active resistor’s T.C. with temperature range from −25 °C to 85 °C in statistical performance, the MC simulation results are shown in Figure 23.

The statistical data values pertaining to the sensitivity of the active resistor at different process corners are summarized in

Table 8. T.C. variation at different process corners with automatic tuning circuit.

	TT	SS	FF	SF	FS
σ (ppm/°C)	10.02	10.64	9.34	10.22	9.83
μ (ppm/°C)	57.08	54.16	61.61	59.02	55.56
σ/μ (%)	17.55	19.64	15.15	17.32	17.69

.

The T.C. values for the TT, SS, FF, SF, and FS corners, under automatic tuning circuit, are obtained as 57.08 ppm/°C, 54.16 ppm/°C, 61.61 ppm/°C, 59.02 ppm/°C, and 55.56 ppm/°C, respectively. These results have demonstrated that the active resistor exhibits a reasonably low T.C. across most corners, except for the FF corner, where the value increases to a certain extent due to faster transistors but still an acceptable value. The calculated sensitivities for TT, SS, FF, SF, and FS corners are 17.55%, 19.64%, 15.15%, 17.32%, and 17.69%, respectively. The low sensitivity reflects the effectiveness of the compensation strategies employed, ensuring robust operation over a wide temperature range. However, the increased T.C. and sensitivity in the SS corner suggest that the process variation can increase the resistor’s temperature dependency to an acceptable extent.

Moreover, the resistance of the active resistor should be tuned for practical applications. A tuning strategy is implemented by the binary-weighted reference resistor array. Specifically, the reference resistor in Figure 9 is replaced by four reference resistors with binary weights (1, 2, 4, and 8) [31] which are configured in a switchable array, enabling adjustment of the tuning current by digital means, as shown in Figure 24. The typical resistor used in the automatic tuning circuit is split into four unit resistors. Each unit resistor comprises two passive resistors with opposite T.C. They are series-connected to achieve close to zero T.C. for the combined resistor R_unit.

Table 9. Device types and sizes of the binary-weighted reference resistor array.

Component	Model	Size (W/L)
RArray1a	rnpoly_wo	16.15 kΩ
RArray1b	rppoly_wo	46.35 kΩ
RArray1/Runit	rnpoly_wo + rppoly_wo	62.5 kΩ
RArray2	rnpoly_wo + rppoly_wo	125 kΩ
RArray4	rnpoly_wo + rppoly_wo	250 kΩ
RArray8	rnpoly_wo + rppoly_wo	500 kΩ
SW1	nch_hvt_dnw	32 µm/1 µm
SW2	nch_hvt_dnw	32 µm/1 µm
SW4	nch_hvt_dnw	48 µm/1 µm
SW8	nch_hvt_dnw	68 µm/1 µm

shows the device types and sizes for the binary-weighted reference resistor array.

As a result, the resistance tuning range is significantly expanded, achieving values from approximately 430.5 kΩ to 1.71 MΩ. This corresponds to a tuning range greater than ±50% around the nominal value, which is denoted as 887.4 kΩ in this design. The resistance of ActR in response to the change of frequency is shown in Figure 25. It can be observed that the ActR resistance remains constant when frequency is up to about 4.6 kHz before dropping in value. This design provides enhanced flexibility and control over the resistor’s value, thus making it suitable for various application requirements.

The performance comparison demonstrates that the proposed active resistor design achieves technical merits such as process sensitivity, temperature stability, wide tuning range of the resistance, very low power consumption and good linearity. The performance results of active resistors are compared with those of the representative reported works in

Table 10. Performance comparison with previously reported works.

	Unit	2008	2012	2018	2020	2023	2025	2025
		[5]	[9]	[32]	[6]	[3]	[33]	This Work #
Process Technology	nm	NA	180	250	180	130	180	40
DC Supply	V	NA	1.8	1.25	1.5	1.2	1.25	1
Typical ActR Value	MΩ	25	0.12	0.001	0.05	20.3	0.052	0.89
Res. Tuning Range	kΩ	NA	1 × 103~ 1 × 106	0.77~ 1.37	NA	NA	35.73~ 71.26	430.5~ 1.714 × 103
Single ActR Transistor Count	NA	23	10	6	6	12	18	8
1 Res. Sen.	(σ/μ) %	NA	1.33	NA	NA	4.9	NA	0.14
2 Res. Sen.	(σ/μ) %	NA	NA	NA	1.6	NA	NA	0.64
Temp. Range	°C	6~46	0~100	−25~75	−20~85	−40~125	−20~40	−25~85
1 T.C.	ppm/°C	NA	4400	NA	NA	3000	5700	4300
1 T.C. Sen.	(σ/μ) %	NA	NA	NA	NA	NA	NA	0.06
2 T.C.	ppm/°C	4000	NA	NA	500	NA	NA	57
2 T.C. Sen.	(σ/μ) %	NA	NA	NA	NA	NA	NA	17.55
1 Linearity FOM	V−1	NA	NA	NA	NA	2.1 × 10−1	NA	2.5 × 10−2
2 Linearity FOM	V−1	NA	NA	NA	3.2 × 10−2	NA	NA	2.4 × 10−2
ActR Bias Control Current	nA	5 × 103	NA	NA	10 × 103	3.5	40 × 103	121
Single ActR Power Consumption	μW	NA	NA	NA	15	4.2 × 10−3	50	* 0.25

¹ without tuning circuit; ² with tuning circuit; ^# with the use of native transistors as ActR; * with 2.1 V typical bootstrapped supply voltage of ActR from DC input of 1 V.

.

Since many ActRs can share the same control unit, the overhead design for the proposed work is significantly reduced when compared to others [3,6,33] in which each active resister relies on an individual control unit. Referring to Table 10, the proposed design achieves a process sensitivity of 0.64% corresponding to the resistance variation, which is lower than that of prior works with sensitivity of 1.33% [9]. With the automatic tuning circuit, the temperature coefficient (T.C.) is reduced to 57 ppm/°C over a wide temperature range of −25 °C to 85 °C with the sensitivity of 17.55%. The T.C. with the tuning circuit is 80 times lower than that without the tuning circuit. It is a significant improvement compared to T.C. of up to 500 ppm/°C in earlier designs [6]. These results have shown the robustness of the proposed design against process and temperature variation through the effective use of automatic tuning and temperature compensation techniques.

In terms of linearity, the reported design has achieved a good result of 2.4 × 10⁻² V⁻¹. Regarding power consumption, the single active resistor only dissipates 0.25 µW under a low bias control current of 121 nA. Additionally, the total power consumption of the active resistor with the automatic tuning circuit is approximately 13 µW. When the charge pump is included, the overall power consumption is 42 µW. These indicate that it is suitable for realization in low-power and compact systems.

As interpreted from Table 10, it can be observed that after applying the tuning circuit, the temperature and process sensitivity increase in value, though not by much. This is primarily because the tuning circuit forces ActR to track the temperature behavior of the passive resistor R, whose resistance value can vary differently across process corners and temperature variation. Another reason is that of the variation of the tuning circuit’s loop gain under different process corners. To verify the issues, the T.C. of the passive resistor R and the loop gain pertaining to loop₂ variation across five standard process corners are evaluated and shown in

Table 11. T.C. of passive resistor and loop gain of loop₂ variation at different process corners with automatic tuning circuit.

	TT	SS	FF	SF	FS
T.C. of Passive R (ppm/°C)	14.76	14.48	15.31	14.76	14.76
Loop Gain of Loop2 (dB)	61.27	64.7	57.9	64.5	57.8
T.C. of ActR (ppm/°C)	57.08	54.16	61.61	59.02	55.56

.

The slight change in the T.C. of the passive resistor across process corners and the moderate loop gain fluctuation in the tuning circuit contribute the imperfections in this circuit implementation. However, as can be observed from the good stability in overall performance, their influences are considered insignificant.

In summary, the proposed active resistor has demonstrated an excellent balance among power, linearity and T.C., while addressing key limitations of earlier reported designs and offering an economical design perspective in which many PRs can share one common control unit.

To demonstrate the practical application of the proposed active resistor, a tunable Sallen–Key low-pass filter (SKLPF) [34] is implemented and illustrated in Figure 26. In this design, the conventional passive resistors R₉ and R₁₀ are replaced with the proposed active resistors, enabling electronic tuning of the cutoff frequency f_c. The f_c and the quality factor Q of an SKLPF are defined as follows:

$$f_c={\displaystyle \frac{1}{2\pi \sqrt{R_9{R}_{10}{C}_9{C}_{10}}}}$$

(50)

$$Q={\displaystyle \frac{\sqrt{R_9{R}_{10}{C}_9{C}_{10}}}{C_2\left(R_9+R_{10}\right)}}$$

(51)

where R₉ and R₁₀ are the tunable active resistors, and C₉ and C₁₀ are the active capacitors realized by the MOS capacitor, as depicted in Figure 10. Considered without peaking effect, the quality factor Q is set to 0.707 (Butterworth response). In this design, R₉ = R₁₀ and C₉ = 2C₁₀ = 200 pF.

To validate the tunable function of ActR, the binary-weighted reference resistor array is applied in the design. Figure 27 shows the plot of different frequency responses of the SKLPF with reference to that of benchmark implementation using an ideal resistor R. Their cut-off frequencies are summarized in

Table 12. Cutoff frequencies of the Sallen–Key low-pass filter with ideal resistors and tunable active resistors.

	Rarray1 = 62.5 kΩ	Rarray1 = 125 kΩ	Rarray1 = 250 kΩ	Rarray1 = 500 kΩ
ActR Resistance (kΩ)	430.5	609.6	887.4	1.714 × 103
fc of Ideal R (kHz)	2.603	1.834	1.266	0.655
fc of ActR (kHz)	2.496	1.766	1.223	0.627
Error (%)	4.1	3.7	3.4	4.3

.

As shown in Table 12, by tuning the resistance values of R₉ and R₁₀ within the range of 430.5 kΩ to 1.714 MΩ, f_c is dynamically tuned from 0.627 kHz to 2.496 kHz. Additionally, the cutoff frequency f_c of the Sallen–Key low-pass filter using the proposed ActR closely matches that of an ideal resistor. Across various tuning configurations, the deviation remains within 5%, with the maximum error being only 4.3%. The slight reduction in f_c can be attributed to the intrinsic parasitic effects of the MOSFET-based ActR, which effectively increase the total capacitance in the circuit and slightly shift the frequency response downward. Despite this minor variation, the ActR maintains reasonable accuracy and reliability, particularly for low-frequency applications. The results have confirmed that the proposed tunable ActR can be a good replacement to a passive resistor in integrated filter design.

Taking routing area into account, the estimated layout area for each circuit block is stated in the following. They are summarized in

Table 13. Cutoff frequency f_c of the Sallen–Key low-pass filter with ideal resistors and tunable active resistors.

Block	Active Resistor Core	Single Op-Amp	Auto-Tuning Circuit	Dickson Charge Pump
Estimated Area (μm × μm)	150 × 5	30 × 20	150 × 35	300 × 255

. As can be seen, the active resistor core occupies approximately 150 × 35 μm². The single op-amp consumes 30 × 20 μm². The automatic tuning circuit with the binary-weighted reference resistor array is 150 × 35 μm², and the DCP occupies 300 × 255 μm². Hence, the overall layout area is approximately 0.096 mm² or 320 μm × 300 μm. Of particular note is that the charge pump and the core tuning circuitry serve as the common resource of the tunable resistor system; the actual active resistor area is small and they can be applied on a large scale without requiring significant silicon area or power consumption.

5. Conclusions

This paper presents the design and implementation of a linear, tunable floating active resistor using the TSMC 40 nm CMOS process technology. The circuit incorporates several key circuits, such as the automatic tuning circuit for resistance stabilization against PVT variation, the active common-mode generator with utmost simplicity and drawing no current, the SCCT for quality level shifting, the triode-based native cascade transistors for reduced DC supply operation, and the DCP for generating the necessary boosted supply voltage.

The design has achieved good linearity performance as well as low power consumption. Due to the significantly low power in a single active resistor, it permits a large scale of active resistors to be implemented in integrated circuits and systems. Furthermore, the effective process sensitivity of the resistance and T.C. performance metrics are low. These technical merits make it attractive for precision analog circuit applications, such as voltage and current reference circuits, tunable sinusoidal oscillator, analog filters, programmable gain amplifiers and so forth. In brief, the proposed active resistor design offers a promising solution for realizing temperature-compensated and tunable resistors for advanced CMOS technology nodes.