Interconnect parasitic capacitance extraction is crucial in analyzing VLSI circuits’ delay and crosstalk. This paper uses the deep neural network (DNN) to predict the parasitic capacitance matrix of a two-dimensional pattern. To save the DNN tr...
With continued transistor scaling and increasing interconnect density in very large-scale integration (VLSI) circuits, the parasitic capacitance of interconnect has become a major contributor to circuit delay and signal integrity degradation. Fast an...
In this study, we designed an MOS varactor for application in the differential voltage-controlled oscillator (VCO). To improve the quality factor of the MOS varactor, we proposed a symmetric layout technique of the MOS varactor with reduced parasitic...
In recent years, on-chip interconnects have been considered as one of the most challenging areas in ultra-large scale integration. In ultra-small feature size, the interconnect delay becomes more pronounced than the gate delay. The continuous scaling...
Field voltage testing after the maintenance of large converter transformers requires high-voltage response verification while preserving the restored equipment boundary. However, conventional direct voltage application on the grid side usually requir...
On-chip electrostatic discharge (ESD) protection is required for all integrated circuits (ICs). Conventional on-chip ESD protection relies on in-Si PN junction-based device structures for ESD. However, such in-Si PN-based ESD protection solutions pos...
Recently, lumped Mach-Zehnder Modulators (MZMs) have received renewed attention due to their potential for low power consumption and compact size. However, the practicality of lumped MZMs with conventional lumped electrodes (C−LEs) is limited b...
This paper presents an in situ time-based sensor designed to provide process authentication. The proposed sensor leverages the inherent metal routing within the chip to measure the RC time-constants of interconnects. However, since the routing metal...
Analog layouts often use matched devices to reduce sensitivity to process gradients. However, the resulting interconnect can introduce parasitic coupling. We compare four DRC-clean, LVS-equivalent layouts of the same hysteresis comparator, implemente...
Through-glass vias (TGVs), as key vertical interconnect structures in 2.5-D/3-D advanced packaging, offer low dielectric loss, low parasitic capacitance, and excellent high-frequency transmission performance. However, several challenges remain in TGV...
This paper presents a CMOS-based optoelectronic receiver integrated circuit (CORIC) realized in a standard 180 nm CMOS technology for the applications of short-distance optical interconnects. The CORIC comprises a spatially modulated P+/N-well on-chi...
InGaAs detection systems have been increasingly used in the aerospace field, and due to the high signal-to-noise ratio requirements of short-wave infrared quantitative payloads, there is an urgent need for methods for the rapid and precise evaluation...
Reducing distortion of spectral simulation signals in infrared detection systems is essential to improve the precision of detecting fine spectra in space-based carbon monitoring satellites. The rigid-flex printed circuit board (PCB), a vital intercon...