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Graphene Nanoribbon as Potential On-Chip Interconnect Material—A Review

Department of Electrical & Electronics Engineering, Birla Institute of Technology & Science (BITS), Pilani 333031, India
Department of Physics &Materials Science, Jaypee University of Information Technology (JUIT), Solan 173234, India
Author to whom correspondence should be addressed.
Received: 29 July 2018 / Revised: 15 August 2018 / Accepted: 16 August 2018 / Published: 30 August 2018
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In recent years, on-chip interconnects have been considered as one of the most challenging areas in ultra-large scale integration. In ultra-small feature size, the interconnect delay becomes more pronounced than the gate delay. The continuous scaling of interconnects introduces significant parasitic effects. The resistivity of interconnects increases because of the grain boundary scattering and side wall scattering of electrons. An increased Joule heating and the low current carrying capability of interconnects in a nano-scale dimension make it unreliable for future technology. The devices resistivity and reliability have become more and more serious problems for choosing the best interconnect materials, like Cu, W, and others. Because of its remarkable electrical and its other properties, graphene becomes a reliable candidate for next-generation interconnects. Graphene is the lowest resistivity material with a high current density, large mean free path, and high electron mobility. For practical implementation, narrow width graphene sheet or graphene nanoribbon (GNR) is the most suitable interconnect material. However, the geometric structure changes the electrical property of GNR to a small extent compared to the ideal behavior of graphene film. In the current article, the structural and electrical properties of single and multilayer GNRs are discussed in detail. Also, the fabrication techniques are discussed so as to pattern the graphene nanoribbons for interconnect application and measurement. A circuit modeling of the resistive-inductive-capacitive distributed network for multilayer GNR interconnects is incorporated in the article, and the corresponding simulated results are compared with the measured data. The performance of GNR interconnects is discussed from the view of the resistivity, resistive-capacitive delay, energy delay product, crosstalk effect, stability analysis, and so on. The performance of GNR interconnects is well compared with the conventional interconnects, like Cu, and other futuristic potential materials, like carbon nanotube and doped GNRs, for different technology nodes of the International Technology Roadmap for Semiconductors (ITRS). View Full-Text
Keywords: multilayer graphene; graphene nanoribbon; on-chip interconnect; mean free path; edge backscattering; resistivity; RC delay multilayer graphene; graphene nanoribbon; on-chip interconnect; mean free path; edge backscattering; resistivity; RC delay

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This is an open access article distributed under the Creative Commons Attribution License which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited (CC BY 4.0).

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Hazra, A.; Basu, S. Graphene Nanoribbon as Potential On-Chip Interconnect Material—A Review. C 2018, 4, 49.

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