RMLP-Cap: An End-to-End Parasitic Capacitance Extraction Flow Based on ResMLP

Abstract

With continued transistor scaling and increasing interconnect density in very large-scale integration (VLSI) circuits, the parasitic capacitance of interconnect has become a major contributor to circuit delay and signal integrity degradation. Fast and accurate parasitic capacitance extraction is therefore essential in the back-end-of-line (BEOL) stage. Currently, 2.5D parasitic capacitance extraction flow based on the pattern matching method is widely used by commercial tools, which still suffer from lengthy pattern library construction, cross-section preprocessing, pattern mismatch, and poor accuracy for small capacitance extraction. To overcome these limitations, this work proposes an end-to-end parasitic capacitance extraction workflow, named residual multilayer perceptron interconnect parasitic capacitance extraction (RMLP-Cap), which leverages a residual multilayer perceptron (ResMLP) to enhance traditional workflow. RMLP-Cap integrates parasitic extraction (PEX) window acquisition, pattern definition, feature extraction, dataset generation, ResMLP model training, and capacitance aggregation into a unified flow. Experimental results show that RMLP-Cap can automatically define and model complex 2D patterns with 100% matching accuracy. Compared with a field solver based on the boundary element method (BEM), the ResMLP model achieves an average relative error below 0.9%, a standard deviation under 0.2%, and less than 0.5% error for small capacitances, while providing a 900% speed improvement for extraction speed.

1. Introduction

With the advancement of integrated circuit (IC) process nodes and the continuous scaling down of transistor feature sizes, the number of on-chip devices and the density of interconnects have increased rapidly, thereby amplifying the impact of on-chip parasitic effects on circuit performance [1]. The parasitic effects in circuits include parasitic resistance, parasitic capacitance, and parasitic inductance. Among them, the parasitic capacitance introduced by interconnects, especially the interconnects in lower layers, has a significant impact on circuit performance metrics such as power consumption, timing, reliability, and signal integrity. Therefore, the accurate and fast extraction of interconnect parasitic capacitance is essential for accelerating the back-end-of-line (BEOL) stage of integrated circuit manufacturing and enhancing the efficiency of circuit design iterations [2].

Currently, two parasitic capacitance extraction methods for interconnects are widely used, namely the field solver method (numerical method) and the pattern matching method (2.5D method) [1,2,3,4]. The field solver method determines parasitic capacitance by assigning a potential to the target conductor (i.e., the aggressor) and solving for its charge distribution in a non-uniform dielectric medium. Commonly used numerical methods include the boundary element method (BEM), the finite element method (FEM), and the floating random walk (FRW) method [1,5,6,7,8]. The extraction results obtained from the field solver offer high accuracy and are regarded as the gold standard for parasitic capacitance extraction. However, the enormous computational cost restricts the field solver’s application to parasitic capacitance extraction of small-scale circuits or validation of test structures [9]. Therefore, commercial tools for parasitic extraction (PEX), such as xRC from Mentor, QRC from Cadence, and StarRC from Synopsys, typically use the pattern matching method for full-chip parasitic capacitance extraction. The pattern matching method achieves a trade-off between extraction speed and accuracy by partitioning the layout into 2D cross-sections and simplifying these 2D cross-sections with respect to the aggressor. After that, pattern matching is performed by dividing each simplified 2D cross-section into several blocks, where the parasitic capacitances in blocks are calculated using a pre-characterized pattern library. Finally, by aggregating the extraction results of all 2D cross-sections, an approximation result of 3D parasitic capacitance extraction is achieved. The pattern matching method provides a parasitic capacitance extraction flow with acceptable computational cost and accuracy. However, the definition of individual patterns and the construction and correction of the pattern library are labor-intensive processes which require extensive efforts from experienced PEX engineers [9,10,11]. Moreover, when dealing with complex cross-sections in layouts at advanced process nodes, the pattern matching method often encounters issues, such as mismatch and insufficient pattern coverage, due to overly simplified pattern models in the current pattern library, thereby introducing additional errors in parasitic capacitance extraction [12].

Since the essence of the pattern matching method lies in constructing models for specific patterns, on the other hand, due to the rapid advance in machine learning (ML) algorithms in recent years, ML algorithms have demonstrated excellent capabilities in regression tasks, particularly in fitting high-dimensional nonlinear models [1]. Consequently, several ML-based methods have recently been proposed to address the aforementioned issues inherent in the pattern matching method [9,10,11]. In 2017, D. White et al. first proposed that ML could be employed to address interconnect parasitic capacitance extraction [13]. After that, Kasai et al. applied an artificial neural network (ANN) to extract parasitic capacitance in a uniform dielectric medium for specific 3D interconnect structures in 2019 [14]. M. S. Abouelyazid and his colleagues from Siemens EDA encoded 2D cross-sections using various discretization methods and constructed a convolutional neural network (CNN) to perform interconnect parasitic capacitance extraction [9,10,11]. However, the essence of the convolution procedure in the CNN model lies in an entropy reduction process. As a result, this method inevitably suffers from a certain loss of accuracy during extraction. To solve the issue above, Yu et al. developed a CNN model based on the ResNet architecture, which improved the extraction accuracy of parasitic capacitance in 2D cross-sections [15,16]. Although the above CNN-based models achieved high accuracy in parasitic capacitance extraction, the preprocessing and encoding of 2D cross-sections consume substantial computational resources, and the constructed neural network models are relatively complex, making the training process challenging. In 2024, Liu et al. innovatively proposed a graph neural network (GNN) model for full-chip interconnect parasitic capacitance extraction [17]. However, the training dataset of this GNN model must be sampled from actual layouts, which leads to a decline in extraction accuracy when the circuit or interconnect topology changes. The most recent work was proposed by Yu et al. in 2025 [18]. By employing adaptive incremental learning to optimize the training dataset, a deep neural network (DNN) model was constructed and demonstrated that, given an appropriate dataset, conventional neural networks can also achieve high accuracy in parasitic capacitance extraction. Although prior studies have employed ML-based methods for interconnect parasitic capacitance extraction, several limitations hinder their practical adoption within commercial PEX tools. Specifically, CNN models suffer from accuracy degradation due to entropy reduction during the convolution process. ResNet-based models exhibit complex architectures that impede efficient deployment, and GNN models are constrained by their dependency on specific interconnect topologies. These challenges collectively restrict the applicability of ML-based methods in existing PEX workflows. Moreover, existing ML-based methods typically adopt pattern libraries directly inherited from conventional 2.5D parasitic capacitance extraction flows. These studies predominantly focus on designing the pattern model and improving the extraction accuracy of these predefined patterns, while paying limited attention to how the patterns themselves are defined and constructed. As a consequence, such methods inevitably inherit the fundamental limitations of the traditional workflow, including the pattern mismatch, as well as the accuracy degradation introduced during capacitance aggregation due to the abstraction and simplification of the pattern.

To address the issues inherent in the aforementioned pattern matching method and the limitations observed in prior ML-based methods, this work proposes a residual multilayer perceptron interconnect parasitic capacitance extraction flow (RMLP-Cap) which is based on residual multilayer perceptron (ResMLP) models. The workflow first divides the layout into multiple full cross-sections along the X and Y directions based on conductor polygon boundaries. Subsequently, PEX windows incorporating process variations are obtained using a designed PEX window acquisition algorithm. After that, each PEX window is followed with pattern matching. For a known pattern that is present in the pattern library, the corresponding ResMLP model is directly used to extract the parasitic capacitances. For an unknown pattern that is absent from the pattern library, the workflow automatically performs unique pattern definition, features extraction, training dataset generation, model structure selection, and model training, thereby progressively completing the pattern library. Compared to the conventional pattern matching method and the aforementioned ML-based studies, the proposed RMLP-Cap flow offers the following advantages:

• A process-variation-aware PEX window acquisition algorithm is developed to segment long aggressors, thereby reducing the complexity of ResMLP modeling while maintaining extraction accuracy.
• An automated pattern library construction workflow is introduced, enabling the library to be constructed directly from the quality assurance (QA) library of a given process.
• The ResMLP-based modeling framework is proposed to enhance the extraction accuracy of small capacitances, mitigating the loss of extraction accuracy caused by neglecting such capacitances in conventional workflow.
• Compared with the previous works, the proposed RMLP-Cap workflow achieves an average relative error less than 1% while reducing the number of floating-point operations (FLOPs) within the same pattern by approximately 53%.

The remainder of this paper is organized as follows. The next section introduces the background of interconnect parasitic capacitance extraction, including the field solver method, the pattern matching method, the ML-based method, and the ResMLP model. Particular attention is paid to the existing pattern matching workflow and its limitations. Section 3 presents the proposed RMLP-Cap flow based on the ResMLP model, with detailed explanations of the pattern library construction process and workflow design. Section 4 validates the PEX window acquisition algorithm in the flow, shows the extraction accuracy and speed, and analyzes the model complexity and performance of the ResMLP model. Section 5 discusses the construction of the pattern library and the generation of the training dataset within the RMLP-Cap workflow. Finally, Section 6 provides a summary of this work.

2. Background of Parasitic Capacitance Extraction

2.1. Field Solver Method

In multiconductor systems within a non-uniform dielectric medium, the parasitic capacitance between conductors is typically calculated by assigning potentials to the conductors, solving for the spatial charge distribution and thereby indirectly obtaining the parasitic capacitance [7,8]. Assuming that there are N conductors in this system, one defines the capacitance matrix as $C\in {\mathbb{R}}^{N\times N}$, the charge matrix as $Q\in {\mathbb{R}}^{N\times 1}$, and the voltage matrix as $V\in {\mathbb{R}}^{N\times 1}$. Then, the following equation holds:

$$Q_i={\displaystyle \sum _{j=1}^N{C}_{ij}{V}_j}$$

(1)

where $Q_i$ denotes the charge on conductor $i$, $V_j$ represents the voltage of conductor $j$ with respect to ground, and $C_{ij}$ denotes the mutual capacitance (C_m) between conductor $i$ and conductor $j$. For $k\in \{1,2,\dots ,N\}$, given the boundary condition:

$$V_k=1, V_{j\ne k}=0$$

(2)

and the Equation (1) can be simplified to:

$$Q_i=C_{ik}{V}_k+{\displaystyle \sum _{j\ne k}{C}_{ij}{V}_j}=C_{ik}$$

(3)

Subsequently, based on the boundary condition (2), the Poisson equation is solved as follows:

$$\nabla \cdot \left(\epsilon \left(\overrightarrow{r}\right)\nabla \varphi \right)=0$$

(4)

and the potential distribution $\varphi$ of the conductor surfaces ($\epsilon$ stands for the dielectric constant) is obtained. From this, the surface charge $Q_i$ of the conductors are determined, corresponding to N mutual capacitance ($C_{1k}, C_{2k},\dots ,C_{Nk}$) in the capacitance matrix. Repeating this procedure N times ($k=1, 2, \dots , N$), the complete capacitance matrix can be obtained. To obtain the precise coupling capacitance (C_c) between conductor a and conductor b ($a, b\in \left\{1, 2, \dots , N\right\}, a\ne b$), let:

$$V_a=1, V_b=0, Q_l=0, l\in \left\{1,2,\dots ,N\right\}, l\ne a, l\ne b$$

(5)

Substituting (5) and the capacitance matrix C into (1), the linear equations:

$$\left[\begin{array}{c}0\\ ⋮\\ Q_a\\ ⋮\\ Q_b\\ ⋮\\ 0\end{array}\right]=\left[\begin{array}{ccc}{C}_{11}& \dots & C_{1N}\\ ⋮& ⋮& ⋮\\ C_{a1}& \dots & C_{aN}\\ ⋮& ⋮& ⋮\\ C_{b1}& \dots & C_{bN}\\ ⋮& ⋮& ⋮\\ C_{N1}& \dots & C_{NN}\end{array}\right]\cdot \left[\begin{array}{c}{V}_1\\ ⋮\\ 1\\ ⋮\\ 0\\ ⋮\\ V_N\end{array}\right]$$

(6)

are solved, thereby obtaining the accurate coupling capacitances:

$$C_{c, ab}=-Q_b, C_{c, ba}=-Q_a, C_{c, ab}\approx C_{c, ba}$$

(7)

To reduce the complexity of solving the Poisson equation in a non-uniform dielectric medium, the BEM method discretizes the conductor boundaries into multiple panels and approximates the $\epsilon \left(\overrightarrow{r}\right)$ of each panel as a constant $\epsilon$. The approximation transforms the Poisson equation into the Laplace equation:

$${\nabla }^2\varphi =0$$

(8)

However, during the 3D field-solving process, the computational cost of the BEM method increases significantly. Therefore, the Monte Carlo-based FRW method has become a common approach for parasitic capacitance extraction in a non-uniform dielectric medium. The FRW method assigns the potential of conductor a and conductor b ($V_a=1, V_b=0$) and then selects sampling point $x_i$ on the surface of conductor b. Starting from $x_i$, multiple random paths that reach the surface of either conductor a or conductor b are generated. The average potential value corresponding to these paths is used as the potential of $x_i$; thereby, the induced charge density on $x_i$ is obtained. After that, the induced charges over all sampling points on the surface of conductor b are integrated to obtain the total charge of conductor b ($Q_b$). According to (8), the coupling capacitance between conductor a and conductor b is derived as follows:

$$C_{c, ab}=-Q_b$$

(9)

2.2. Pattern Matching Method

As the commonly used method in existing commercial PEX tools, the extraction flow of the pattern matching method is shown in Figure 1. First, the layout is divided into a number of 2D cross-sections based on corresponding process files (i.e., tech file). Each cross-section is then partitioned into multiple blocks. After applying approximate processing to each block, pattern matching is performed against the pre-characterized pattern library. After that, the empirical formulas or lookup tables corresponding to the patterns in the pattern library are used to extract the parasitic capacitance within each block. Finally, the capacitances in all 2D cross-sections are aggregated to obtain the total parasitic capacitance of the circuit. In this workflow, pattern mismatch, block approximations of the pattern library, and the quality of the pattern library will have a significant impact on the extraction accuracy of the entire flow [1,9].

For a specific process, the construction of the pre-characterized pattern library is illustrated in Figure 2. First, a set of simple patterns is initially defined. For each pattern, several parameters, typically conductor width, spacings between adjacent polygons, etc., are varied to generate empirical formulas or lookup tables using the field solver. The accuracy of parasitic capacitance extraction and pattern coverage of the library are then checked against the QA library provided by the foundry. If the extraction accuracy does not meet the industrial production requirements (a mean relative error (MRE) less than 5%), the existing pattern library is corrected by modifying pattern parameters, adjusting interpolation methods, or adding new patterns. Through continuous iteration, a pattern library that satisfies the required accuracy is ultimately obtained. However, the construction of the pattern library is labor-intensive and time-consuming, requiring substantial iteration and maintenance by experienced PEX engineers. Moreover, as process nodes advance, the number of patterns required in the library grows steadily. Consequently, rapid and accurate construction of the pattern library is critical for pattern matching-based parasitic capacitance extraction [9,10].

2.3. Parasitic Capacitance Extraction Based on ML

The essence of the pattern matching method lies in modeling the patterns within the pattern library, and interdependencies among pattern parameters lead to nonlinear relationships between these parameters and the parasitic capacitance.

However, when lookup tables are employed, interpolation methods (e.g., multidimensional linear interpolation) cannot adequately capture the nonlinear relationships in high-dimensional spaces, resulting in errors during extraction. In contrast, the strong nonlinear fitting capability of ML in high-dimensional spaces provides a new perspective for parasitic capacitance extraction [18]. For a specific pattern with m features and n parasitic capacitances, the corresponding neural network uses $x\in {\mathbb{R}}^m$ as input and $y\in {\mathbb{R}}^n$ as output. The neural network can be abstracted as a mapping $y=f\left(x; \theta \right)$, where the weights and biases on the neurons in hidden layers of the network are denoted by $\theta$ [1].

2.4. Residual Multilayer Perceptron

Currently, several studies have explored ML-based parasitic capacitance extraction. These approaches often encode patterns in different ways to improve the accuracy of ML-based parasitic capacitance extraction. However, prior works typically relied on conventional ANN models for pattern modeling, which made the models neglect small capacitances (the capacitance value of small capacitance is less than 1% total capacitance (C_tot) of the corresponding net) in order to satisfy the predefined loss functions during the model training process [19,20]. Shook et al. estimated the parasitic capacitances of the layout with the schematic of the circuit [21]. However, the prediction accuracy was relatively large, and the applicability of the ANN model was restricted to only a limited set of circuit structures. Tsai et al. extracted parasitic capacitances within a standard cell by discretizing the layout and employing an ANN-modeling approach [22]. Nevertheless, the direct discretization produced feature vectors of considerable length, resulting in substantial computational overhead during model training. Ma et al. and Yang et al. employed ResNet-18 and ResNet-50 architectures, respectively, to achieve higher accuracy in pattern modeling; however, the preprocessing of cross-sections in CNNs is relatively complex [15,23]. Li et al. employed a GDB-SRSS encoding scheme to simplify the CNN input representation and adopted a ResNet-32 architecture to extract parasitic capacitances from 2D cross-sections. However, the entropy reduction inherent in convolution operations still leads to considerable MRE when extracting small capacitance [24].

In conventional ANN model training, the labels of small capacitances within certain patterns are two to three orders of magnitude smaller than those of typical capacitances. Consequently, the training loss becomes dominated by the errors associated with typical capacitances. Because the training loss contributed by typical capacitances is greater, backpropagation assigns large gradients to these terms, whereas the gradients corresponding to small capacitances are suppressed due to their very small numerical scale. As a result, the model tends to prioritize fitting typical capacitances during training process, while insufficiently learning the behavior of small capacitances, leading to poor extraction accuracy for the latter. The aforementioned issue cannot be resolved simply by increasing the number of hidden layers or by enhancing the complexity of the ANN model to transform it into a DNN model. To reduce model complexity while ensuring accurate extraction of small capacitances, this work proposes the RMLP-Cap flow based on the ResMLP model. The structure of ResMLP is illustrated in Figure 3. By introducing several residual blocks (RBs) at the output stage of the ANN model, the model can further refine the components that the main network fails to adequately capture. Since the predictions for typical capacitances are already close to their labels, the RBs generate only minor corrections for them. In contrast, the prediction errors of small capacitances are relatively larger, enabling the RBs to focus on learning these remaining residual signals and thereby substantially improving the model’s predictive capability for small capacitances. After residual refinement, the model not only maintains high accuracy for typical capacitances but also enhances the extraction accuracy of small capacitances. Furthermore, by incorporating RBs, the ResMLP model avoids performance degradation that typically occurs in complex pattern modeling when the depth and width of the network increase [25].

3. Interconnect Parasitic Capacitance Extraction Based on RMLP-Cap

This chapter presents the details of RMLP-Cap flow based on the ResMLP model. It begins with an overview of the proposed RMLP-Cap flow. Next, the chapter provides a detailed description of the automatic pattern library construction process, including the PEX window acquisition algorithm, pattern definition, and feature extraction. Finally, the chapter discusses the details of the workflow during extraction, including applying process variations to full cross-sections, the segmentation algorithm for the long aggressor, and the capacitance aggregation algorithm.

3.1. Overview of RMLP-Cap Flow

As shown in Figure 4, all PEX windows are first obtained from the layout combined with corresponding tech files. After that, each PEX window is followed by pattern matching. If a PEX window corresponds to a known pattern that exists in the current pattern library, the corresponding ResMLP model is directly used for extraction. On the contrary, if a PEX window corresponds to an unknown pattern that does not exist in the current pattern library, parasitic capacitances within this PEX window are extracted using the field solver. At the same time, the pattern is automatically defined, and its features are extracted. After generating the training dataset for the unknown pattern on a computing cluster with the field solver, the corresponding ResMLP model will be trained to convert the unknown pattern into a known pattern. Finally, the pattern library is updated to ensure an increase in pattern coverage.

3.2. The Construction of Pattern Library

After obtaining the layout, all PEX windows need to be generated. As shown in Figure 5, the boundaries of all polygons are first scanned along the x direction and y direction in the x-y plane to determine slice edges. The region between two adjacent slice edges defines a slice position. Using the metal thicknesses provided by tech files, the corresponding cross-section at this slice position is obtained. These cross-sections obtained in the x-z or y-z plane are referred to as full cross-sections. The distance between two adjacent slice edges is defined as the effective length of the corresponding full cross-section.

Since a full cross-section contains a large number of environmental conductors (ecs), directly using it for pattern definition would increase both the model complexity of the pattern and the total number of patterns in the pattern library. Therefore, to reduce the number of conductors in each full cross-section, a PEX window corresponding to the aggressor is required. As shown in Figure 6, for a full cross-section in the x-z plane, the PEX window is centered on the aggressor. In the x direction, the window width is $w_{agg}+2d$, where $w_{agg}$ is the width of the aggressor, $d$ is the expand distance in x direction of PEX window. In the z direction, the window height covers three metal layers.

After obtaining the PEX window, it is necessary to perform pattern definition for this window. The definition method is as follows: starting from the top metal layer, the number of conductors in each layer within the PEX window is counted, and these numbers are separated by cross signs. For example, in Figure 6c, the pattern is defined as a 2 × 3 × 1 pattern. If the pattern corresponds to an unknown pattern, feature parameters need to be extracted for it. First, the reference conductor of each metal layer and the reference layer within the PEX window must be determined. For a metal layer that contains N conductors, the index of the reference conductor of this metal layer (counting from left to right) is $⌊{\displaystyle \frac{N+1}{2}}⌋$. For example, in Figure 6c, the reference conductor in metal i − 1, metal i, and metal i + 1 is ec1, agg, and ec4, separately. On the other hand, for a PEX window containing M metal layers, the index of the reference layer (counting from bottom to top) is $⌊{\displaystyle \frac{M+1}{2}}⌋$. For example, the reference layer in Figure 6c is metal i. The reference conductor located in the reference layer is set with its center at the origin. Subsequently, the widths of conductors, the spacings between adjacent conductors, the heights of the corresponding layers, and the offsets between the reference conductor in the reference layer and reference conductors in other layers are obtained as features of this pattern. For example, $w_1-w_5$, $w_{agg}$, $s_{2a}$, $s_{a3}$, $s_{45}$, $d_{a1}$, $d_{a4}$, $h_{i-1}$, $h_i$, and $h_{i+1}$ in Figure 6. After obtaining the features of the unknown pattern, the variation range of each feature is set according to the tech file, and a large number of PEX windows are then generated by feature vectors. The 2D field solver based on BEM is employed to calculate the C_c within each PEX window, thereby obtaining the training dataset for the unknown pattern.

To minimize computational cost while ensuring sufficient fitting between input and output, the structure of ResMLP is dynamically designed according to the number of pattern features. Suppose an unknown pattern has m features and n outputs, each fully connected layer uses a hidden dimension of 10m, and the number of fully connected layers is fixed at nine. Two RBs are connected after the fully connected layers, and each RB contains three hidden layers; each hidden layer has a hidden dimension of 5n.

3.3. The Details of RMLP-Cap Flow

During the fabrication procedure of IC, process variations will induce non-ideal factors such as wire expansion and trapezoidal effect, which cause discrepancies between PEX results and capacitances measured in fabricated chips [9]. To mitigate the impact of process variations, the proposed RMLP-Cap flow incorporates the relevant process variations specified by the tech file during full cross-section acquisition. As shown in Figure 7, the widths and spacings of conductors in the ideal layout are first obtained. Based on the wire expand lookup table provided in the tech file, a bilinear interpolation algorithm is applied to determine the wire edge expansion (wee) on both sides of each conductor. Then, the conductor widths are modified accordingly, completing the initial correction. For the lower metal layers, if the tech file provides higher-order wire expand lookup tables, the above process needs to be repeated on the initially corrected full cross-section until all higher-order corrections are completed. Subsequently, trapezoidal effects are added to each conductor according to the tech file, and the widths of all conductors are converted to equivalent widths (w_eff), thereby completing the addition of process variations.

During the layout drawing process, design rules often require the metal layers to be routed in prescribed directions, and the routing directions of adjacent metal layers are typically orthogonal. As a result, when defining the PEX window, the width of the aggressor may become large. Such a conductor is referred to as a long aggressor. The long aggressor will result in an excessive number of conductors within the PEX window, thereby increasing the modeling complexity of the pattern. As shown in Figure 8, the segmentation algorithm is designed to address the issue. First, set the maximum width of the sub-aggressor as $w_m$, where the $w_m$ is equal to five times the minimum width of the corresponding tech file (the minimum width is automatically parsed from the tech file and incorporated as a parameter in the segmentation algorithm for the long aggressor segmentation algorithm). If $w_{agg}>w_m$, the long aggressor will be divided into n sub-aggressors. Among them, the widths of the first n − 1 sub-aggressors are $w_m$, while the width of the nth sub-aggressor is $w_{agg}-\left(n-1\right)w_m$ or $w_m$. For the ith ($i\le n$) sub-aggressor, its PEX window is defined by extending its edges outward by $d=w_m$. To avoid introducing additional parasitic capacitance caused by the segmentation of the long aggressor, it is necessary to add dummies for the PEX window corresponding to the sub-aggressor. The spacing of the dummy and sub-aggressor is set to the minimum layout unit, which is 1 nm for the 28 nm process. The width of the dummy on the right side of the sub-aggressor is $w_d$. The right boundaries of the original long aggressor and the ith sub-aggressor are $x_a$ and $x_{sa}$, respectively. And the right boundary of the PEX window corresponding to the sub-aggressor is $x_e$. If $x_a\ge x_e$, then $w_d=d-1$; otherwise, $w_d=\left(x_a-x_{sa}\right)-1$. The widths of the dummies on the left side of the sub-aggressor are calculated in the same way. The process of adding dummies is illustrated in Figure 8b–d.

After obtaining the parasitic capacitances within the PEX windows, the capacitance aggregation algorithm is applied to obtain the capacitance of a specific net. The capacitance aggregation algorithm is shown in Figure 9. For example, to obtain the parasitic capacitance of net 1 in Figure 9, all the PEX windows dominated by the net 1 (y.1, y.2, x.1, x.2 and x.3) and their corresponding effective length (l₁ to l₅) are first obtained on the x-z and y-z planes. After obtaining the capacitances within each PEX window with the corresponding ResMLP model, the parasitic capacitance between net 1 and net 2 can be calculated as:

$$C21=C{21}_1\times l_1+C{21}_2\times l_2+C{21}_3\times l_4$$

(10)

The capacitance between net 1 and substrate is:

$$C1b={\displaystyle \sum _{i=1}^{5}C1b_i\times l_i}$$

(11)

And the total parasitic capacitance of net 1 is:

$$C{1}_{tot}=C21+C1b$$

(12)

4. Experimental Results and Analysis

This chapter evaluates the performance of the proposed RMLP-Cap flow and shows the experiment results. First, the value of PEX window expansion d is determined to minimize accuracy loss during PEX window acquisition. Next, the proposed segmentation algorithm for the long aggressor is validated to ensure that the parasitic capacitance extraction accuracy of the original long aggressor remains within acceptable limits. In addition, the impact of dummy insertion on extraction accuracy is compared. Then, the performance metrics of the RMLP-Cap flow, including extraction accuracy, modeling time, and extraction speed, are analyzed. Finally, the extraction accuracy of the 2D cross-section obtained by RMLP-Cap flow in real design is evaluated and compared with that of the conventional SVR model. All experimental results are obtained based on the 28 nm process.

4.1. Determination of PEX Window Expansion

To ensure that the influence of conductors outside the PEX window on the parasitic capacitance of the aggressor is minimized, the PEX window expansion d needs to be determined. As shown in Figure 10a, the width of the aggressor and ec are $w_m$, and the distance d between them is gradually increased. The ratio of the C_c between the aggressor and ec to the C_tot of the aggressor is calculated, which represents the influence degree of the ec outside the PEX window on the parasitic capacitance of the aggressor. The results are shown in Figure 10b. For upper metal layers, the C_c between the aggressor and substrate decreases, resulting in the fact that only when d is large enough can the influence of ec on the aggressor be reduced to the industrial expectation. However, an excessively large window size will increase the number of conductors inside the PEX window, leading to higher model complexity. To balance extraction accuracy and model complexity, the PEX window expansion d is chosen as 1.5 µm.

4.2. Analysis of the Segmentation Algorithm for Long Aggressor

To verify the extraction accuracy of parasitic capacitance after applying the segmentation algorithm for the long aggressor, six possible topologies containing a long aggressor are tested. As shown in Figure 11, in terms of conductor width, the width of the ec is either shorter or longer than that of the long aggressor; in terms of topology, the ecs either fully cover, partially cover, or do not cover the long aggressor. The C_c between the original long aggressor and ec, as well as the C_tot of the original long aggressor, are calculated using a field solver and serve as the golden. In addition, after applying the segmentation algorithm, the aggregated parasitic capacitance of all sub-aggressors is calculated both without and with dummy insertion. These results are then compared with the original capacitances to compute the relative error. The results are shown in

Table 1. Parasitic capacitance extraction results of segmentation algorithm for long aggressor.

Capacitance Type	Case Type	Golden (10−16)	Without Dummy (10−16)	MRE (%)	With Dummy (10−16)	MRE (%)
Cc	case 1	0.806	1.244	54.41	0.809	0.38
	case 2	0.788	1.160	47.20	0.792	0.48
	case 3	0.518	0.489	−5.66	0.496	−4.14
	case 4	2.197	2.898	31.90	2.203	0.24
	case 5	2.079	2.763	32.91	2.080	0.07
	case 6	0.768	0.680	−11.46	0.746	−2.89
Ctot	case 1	1.873	2.788	48.34	1.877	0.23
	case 2	1.850	2.699	45.91	1.853	0.19
	case 3	1.545	2.176	40.88	1.493	−3.37
	case 4	3.042	4.055	33.30	3.049	0.23
	case 5	2.935	3.944	34.38	2.940	0.16
	case 6	1.694	2.305	36.06	1.637	−3.39

. As shown in Table 1, for a long aggressor, the aggregated capacitances of sub-aggressors deviate significantly from the original aggressor’s extraction results when dummies are not added. This is because, without dummies, additional edge capacitances (i.e., the fringing capacitance generated between the lateral sides of the sub-aggressor and the upper or lower surfaces of the adjacent environmental conductor [26]) are introduced in the PEX windows, resulting in an aggregated capacitance that is larger than the golden In contrast, after adding dummies to the PEX window of the corresponding sub-aggressor, the aggregated capacitances closely match the golden. This demonstrates that the proposed segmentation algorithm for the long aggressor can effectively simplify the PEX window while handling the long aggressor with no loss in extraction accuracy, thereby reducing the complexity of the corresponding ResMLP model.

4.3. Parasitic Capacitance Extraction Based on ResMLP Model

This section takes the 3 × 3 × 3 pattern as an example to demonstrate the construction process and performance of the proposed ResMLP model. The training dataset is generated on the cluster using five machines, with each configured with an Intel Xeon Platinum 8365H (3.9 GHz, 256 GB RAM with 32 slots). The ResMLP model is trained with the Pytorch framework, with a training machine configured as Intel i9-14900K (3.2 GHz, 128 GB RAM) and two NVIDIA RTX 4090 GPUs (24 GB RAM).

After obtaining the PEX window and determining that the pattern type is 3 × 3 × 3, the features of this pattern are first extracted. As shown in

Table 2. Features of 3 × 3 × 3 pattern type.

Feature Name	Variable Type	Variation Range
wm 1	Width	[min W, 5 min W]
wa 2	Width	[min W, 5 min W]
smn 3	Spacing	[1, 1500] nm
sax 4	Spacing	[1, 1500] nm
day 5	Offset	[min W, 5 min W]
hi 6	Height	[375, 550, 725, 900, 1075, 1250] nm

¹ Width of the ec (m = 1, 2, …, 8). ² Width of the aggressor. ³ Spacing of the ec (mn = 12, 23, 67, 78). ⁴ Spacing between the ec that is next to the aggressor in the same layer and the aggressor (x = 4 or 5). ⁵ The offset of the aggressor and the reference conductor in different layers (y = 2 or 7). ⁶ The height of the layer (i = 1, 2, …, 6).

, the features are divided into four types: width, spacing offset, and height. The 3 × 3 × 3 pattern type contains 20 features. Then, based on the variation range of each variable, random samples are generated to construct the input set for training the corresponding ResMLP model. Among them, conductors are randomly distributed across any three layers from M1 to M6. To minimize the computational resources required for generating the training dataset, the number of samples used for model training is dynamically adjusted according to the pattern type (the number of samples used for training is 5 × 10⁵ times the number of corresponding pattern features). For the 3 × 3 × 3 pattern type, the number of samples is 10 million. All samples are distributed to the cluster, and the field solver is employed to obtain the output set corresponding to the input set.

For the ResMLP model of this pattern, the number of input layer nodes is 20. The number of hidden nodes in each fully connected layer is 200, while the number of hidden nodes in each fully connected layer within the RBs is 100. The activation functions are applied in the order of ELU-ReLU-Tanh between adjacent layers in the model. Among them, the ELU function helps to smooth the current input; the ReLU function disconnects the inactive nodes in the current input flow, thereby reducing the noise caused by inactive nodes to the model output; and the Tanh function compresses the current input to ensure that the output values remain stable within a certain range, avoiding the influence of large output on small capacitances [27,28]. During training process, the batch size is set to 256, and the optimizer is Adam. The loss function is defined as the MRE of the output.

$$loss={\displaystyle \sum _{i=1}^N\left|\frac{{\widehat{y}}_i-y_i}{y_i+bias}\right|}$$

(13)

As shown in (13), ${\widehat{y}}_i$ stands for the predict value of the ith sample, while $y_i$ stands for the golden of the ith sample, N = 256 and bias = 10⁻⁹. The early stopping criterion is that the MRE on the training set falls below 1%. The model’s floating-point operations (FLOPs) for each sample are approximately 390,000, and the training process reached early stopping after 54 epochs.

After obtaining the trained ResMLP model of the 3 × 3 × 3 pattern type, the parasitic capacitance extraction accuracy was evaluated using 10,000 randomly generated samples, including 450,000 C_c, 100,000 C_tot, and 240,439 small capacitances, which were entirely excluded from the training dataset to ensure unbiased performance assessment. The results are shown in Figure 12. It can be observed that the ResMLP model demonstrates excellent extraction accuracy across C_c, C_tot, and small capacitances, with MREs all below 1% and standard deviations under 0.6%. Notably, for small capacitances, the fraction of capacitances exceeding the industrial extraction accuracy requirement is only 0.0008%. Furthermore, there is no C_tot exceeding the industrial extraction accuracy requirement. These results confirm that the proposed ResMLP model achieves outstanding accuracy in extracting parasitic capacitances in 2D cross-sections.

Subsequently, a conventional ANN model was constructed using the same training dataset. The ANN architecture consists of 15 hidden layers, which has 200 nodes in the first nine hidden layers and 100 nodes in the last six hidden layers. The FLOPs of this ANN model are approximately 400,000 for each sample. The ANN model was trained using the same loss function and number of epochs as the ResMLP model. The parasitic capacitance extraction accuracy was then evaluated using the same test dataset. As shown in Figure 13, although the MRE of C_tot meets the industrial extraction accuracy requirement, both the MRE and standard deviation of C_c are significantly higher compared to the ResMLP results. More importantly, for small capacitances, the prediction accuracy of the conventional ANN model is substantially inferior to that of the ResMLP model. This degradation arises because the representational capability of the ANN model diminishes as the model depth increases, leading to unstable training. Errors generated in the intermediate layers tend to accumulate toward the output, which severely undermines the prediction accuracy of small capacitances. In contrast, the ResMLP model leverages RBs that emphasize optimization of underfitted features after fully connecting layers, while alleviating the vanishing gradient problem during backpropagation and reducing the number of inactive nodes. Consequently, despite a comparable FLOP, the ResMLP model exhibits significantly superior extraction accuracy over the conventional ANN model.

4.4. The Performance of ResMLP Model in Real Design

To evaluate the parasitic capacitance extraction accuracy of the proposed ResMLP model in real designs, five patterns defined in the traditional 2.5D parasitic capacitance extraction flow (PLATE2L, PLATE3L_c1, PLATE3L_bc, STACK3L_c1, and STACK3L_c2) were selected for evaluation. Corresponding ResMLP models were constructed for each of these patterns, and their extraction accuracy was assessed. The test cases for the five patterns were derived from real designs, with conductors distributed from M1 to M3. Schematic illustrations of the five patterns are shown in Figure 14, while their definitions in the RMLP-Cap flow and corresponding extraction results are summarized in

Table 3. Extraction results of five patterns defined in the 2.5D parasitic capacitance extraction flow.

Pattern Based on 2.5D Pattern Matching Flow	Pattern Based on RMLP-Cap Flow	Test Cases Number	Extract Cap. Number	Max RE (%)	MRE (%)
PLATE2L	4; 2; 1	972	5049	8.86	0.94
PLATE_c1	1 × 4; 1 × 2; 1 × 1	972	6993	10.86	1.15
PLATE_bc	1 × 4; 1 × 2; 1 × 1	972	8775	16.3	0.97
STACK3L_c1	4 × 4; 2 × 2; 1 × 1	432	3726	4.54	0.79
STACK3L_c2	4 × 4; 2 × 2; 1 × 1	432	3726	8.17	1.21

. It is worth noting that although a single pattern defined in the 2.5D parasitic capacitance extraction flow may correspond to multiple distinct structures and require multiple ResMLP models for representation, the proposed RMLP-Cap flow is capable of consistently describing these variations. Furthermore, the ResMLP model achieves high extraction accuracy across all test cases, thereby demonstrating its robustness and practical applicability in handling diverse topologies.

To assess the computational efficiency of the proposed ResMLP model in parasitic capacitance extraction, 3780 test cases corresponding to the aforementioned pattern types were processed using the 2D field solver (fast mode), the support vector regression (SVR) model, a conventional ANN model, and the proposed ResMLP model. The results are shown in

Table 4. Comparison of parasitic capacitance extraction performance.

Method	MRE (%)	Max RE (%)	Avg. Extract Time (ms)
2D field solver (high)	-	-	64,162
2D field solver (fast)	0.80	3.53	3649
SVR	2.83	2288.73	34
ANN	1.56	−70.22	43
ResMLP	1.01	10.86	40

. The goldens are obtained from the 2D field solver under the highest accuracy mode. Due to the high boundary discretization required in the highest accuracy setting, the computational cost of the field solver increases substantially. In order to avoid overfitting, the SVR model often pays more attention to areas with denser samples, which results in a large MRE when extracting small capacitance in sparsely sampled regions. It is worth noting that both the ANN model and the ResMLP model achieve extraction speeds nearly 90 times faster than the 2D field solver while maintaining high accuracy. However, the ANN model exhibits limited expressive ability as network depth increases, leading to higher maximum MRE on test cases compared to the ResMLP model. In contrast, the ResMLP model enhances expressive capacity by incorporating RBs after fully connected layers, thereby improving feature learning. As a result, the ResMLP model achieves accuracy nearly identical to that of the 2D filed solver, while maintaining significantly computational efficiency.

Finally, the computational complexity of the ResMLP model was evaluated, and the results are shown in

Table 5. Evaluation of computational complexity.

Method	Model Architecture	Feature Vector Dimension	Number of Parameters	FLOPs	MRE (%)	Ref.
CNN-Cap	ResNet-50	267	~25.6 M	0.0366 G	0.816	[15]
GDB-Gray	ResNet-34	75	~21.8 M	0.0112 G	7.791	[24]
SDB-SRSS	ResNet-34	75	~21.8 M	0.0112 G	0.868	[24]
RMLP-Cap	ResMLP	14	~0.28 M	0.0059 G	0.317	This work

. The pattern used for testing was 2 × 3 × 1, with three metal layers distributed across M1 to M3. In previous studies, CNN-based parasitic capacitance extraction frameworks commonly relied on discretizing the extraction window to sufficiently represent the topological structure of the pattern. This procedure substantially increases the dimensionality of the input feature vectors, leading to a dramatic expansion of the parameter count in subsequently fully connected layers, while the convolutional feature extraction stage also incurs significant computational overhead, ultimately resulting in much higher FLOPs. Moreover, the convolution operations in CNNs inherently perform multi-level compression and reconstruction of the patterns, which inevitably causes loss of structural information, weakening the correspondence between the input features and the true pattern topology, thereby increasing the extraction errors. Since a pattern is highly sensitive to geometric details, CNN-based feature extraction can further introduce noise, increase model complexity, and make training more difficult. In contrast, the proposed ResMLP model directly uses topological parameters without window discretization, resulting in much lower feature dimensionality. These concise yet topology-preserving descriptors allow the ResMLP model to achieve accuracy comparable to or better than the CNN-based model while significantly reducing FLOPs. Thus, the ResMLP model attains efficient and accurate prediction with substantially lower computational cost, making it more suitable for industrial workflows.

5. Discussion

For a new process node, the pattern library must be reconstructed. The initial pattern library is established by utilizing the QA library provided by the foundry and the PEX window acquisition algorithm. For each pattern, the corresponding feature vector is generated through the parsing of the associated tech files. The resulting feature vectors are then used to produce the training datasets on a computing cluster. Throughout this process, the tech files supplied by different foundries typically exhibit substantial differences in structure and formatting. Therefore, the parsers required to extract technology parameters must be independently designed and tailored to the specific format of the tech files used in each process.

During the dataset construction for individual patterns, the variation ranges of different features can differ significantly. For example, the height of the conductor in z-direction (i.e., h_i) usually consists of a small number of discrete values (six in this work), whereas conductor width and spacings are represented by more highly continuous discrete parameters (e.g., the width variations within the range [min W, 5min W]). As a result, achieving adequate coverage of the parameter space necessitates the generation of a large number of randomized samples. For complex pattern types, the required dataset size typically reaches the order of millions, thereby imposing considerable demands on computational resources.

Moreover, the degree of coverage across the pattern parameter space exerts a direct impact on the accuracy and generalization capability of the ResMLP model. Insufficient representation of certain feature combinations can lead to degraded prediction performance, especially for sparse or extreme geometric configurations. Comprehensive and uniformly distributed sampling therefore remains critical for maintaining accuracy stability. In practical layout design, however, the conductor widths and spacings employed are usually confined to a limited set of values, indicating that uniform large-scale sampling may not constitute the most efficient strategy. Future research directions include the adoption of dynamic dataset generation techniques inspired by Ref. [18], in which the number of generated samples is adaptively adjusted according to the occurrence frequency of feature regions. Such an approach is expected to reduce the computational burden associated with pattern library construction while preserving the robustness and accuracy of the resulting models.

6. Conclusions

In this work, an end-to-end parasitic capacitance extraction flow based on the ResMLP model, named RMLP-Cap, is proposed. The RMLP-Cap flow incorporates a full cross-sections acquisition algorithm and PEX window acquisition algorithm, enabling the determination of appropriate extraction windows for the corresponding net. For an excessively long aggressor, a segmentation algorithm for the long aggressor is introduced to reduce the number of conductors within the PEX window. This effectively decreases the complexity of the corresponding ResMLP model without compromising extraction accuracy. Moreover, for each full cross-section, the RMLP-Cap flow can automatically incorporate process variations according to the tech file, thereby improving the accuracy of 2D cross-sectional parasitic extraction. Compared with the extraction using the traditional 2D field solver, the proposed ResMLP model achieves a 90-fold speedup while maintaining comparable accuracy. In terms of precision, the ResMLP model outperforms conventional SVR and ANN models, achieving a MRE of less than 1% for C_c and C_tot and less than 0.5% for small capacitance. Regarding computational resource consumption, the proposed approach reduces FLOPs by approximately 53% under the same pattern settings compared to the CNN model. In addition, the RMLP-Cap flow not only enables rapid extraction for patterns already included in the pattern library but also supports automatic modeling for unknown patterns. The automatic modeling process consists of four steps: pattern definition, feature vector extraction, training dataset generation, and ResMLP model training, which mitigates the need for PEX engineers to frequently update and fix the pattern library when new process nodes arrive, thereby accelerating the BEOL process in IC manufacturing.