Open AccessReview
Metal-Insulator-Metal Single Electron Transistors with Tunnel Barriers Prepared by Atomic Layer Deposition
by
Golnaz Karbasian 1,3, Michael S. McConnell 1,*, Hubert George 1,4, Louisa C. Schneider 1,5, Matthew J. Filmer 1, Alexei O. Orlov 1, Alexei N. Nazarov 2 and Gregory L. Snider 1
1
Department of Electrical Engineering, University of Notre Dame, Notre Dame, IN 46556, USA
2
Lashkaryov Institute of Semiconductor Physics, 03028 Kyiv, Ukraine
3
Present address: Electrical Engineering and Computer Sciences, University of California, Berkeley, Berkeley, CA 94720-1770, USA
4
Present address: Intel Corp, 2501 NW 229th Ave., Hillsboro, OR 97124, USA
5
Present address: Cypress Semiconductor Corp, 2401 East 86th St., Bloomington, MN 55425, USA
Cited by 15 | Viewed by 7281
Abstract
Single electron transistors are nanoscale electron devices that require thin, high-quality tunnel barriers to operate and have potential applications in sensing, metrology and beyond-CMOS computing schemes. Given that atomic layer deposition is used to form CMOS gate stacks with low trap densities and
[...] Read more.
Single electron transistors are nanoscale electron devices that require thin, high-quality tunnel barriers to operate and have potential applications in sensing, metrology and beyond-CMOS computing schemes. Given that atomic layer deposition is used to form CMOS gate stacks with low trap densities and excellent thickness control, it is well-suited as a technique to form a variety of tunnel barriers. This work is a review of our recent research on atomic layer deposition and post-fabrication treatments to fabricate metallic single electron transistors with a variety of metals and dielectrics.
Full article
►▼
Show Figures