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A Special Issue of Electronics (ISSN 2079-9292) belonging to the section "Artificial Intelligence".

Deadline for manuscript submissions: 15 November 2026 | Viewed by 2198

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Editors

Dr. Sergio Spanò

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Guest Editor

Department of Electronic Engineering, University of Rome Tor Vergata, 00133 Rome, Italy
Interests: digital signal processing; machine learning; artificial intelligence; hardware acceleration; IoT; embedded systems; VLSI
Special Issues, Collections and Topics in MDPI journals

Prof. Dr. Gian Carlo Cardarilli

E-Mail Website
Guest Editor

Department of Electronic Engineering, Tor Vergata University of Rome, 00133 Rome, Italy
Interests: digital signal processing; machine learning; digital architectures; digital electronics for space
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Dr. Luca Di Nunzio

E-Mail Website
Guest Editor

Department of Electronic Engineering, University of Rome Tor Vergata, 00133 Rome, Italy
Interests: electronics and communication engineering; digital signal processing; machine learning; FPGA
Special Issues, Collections and Topics in MDPI journals

Special Issue Information

Dear Colleagues,

Non-functional constraints such as execution time, memory capacity, and energy consumption pose significant challenges for designers in the field of machine learning systems. New applications are being proposed that integrate various functionalities into everyday objects, imposing several additional requirements on embedded system designers, such as the following:

Increased computing workloads when elaborating and fusing multiple data, even when using advanced machine learning techniques;
Reduced power consumption, allowing for smaller batteries and renewable power sources;
Faster interaction with the environment, requiring a high level of data processing performance often reached using hardware implementations.

For example, the physical dimensions and power consumption of embedded Internet of Things systems are frequently of interest. However, the need for small systems does not prevent greater demands from being made with regard to functionality and speed. Simultaneously, designers must respond to a growing need for more powerful edge systems capable of managing vast fleets of connected devices while running resource-intensive algorithms such as sensor fusion, feedback control, and machine learning algorithms. Developers must understand the nature of hardware architectures and strategies for extracting their full performance potential in this environment as well as embedded design in general.

For this Special Issue, we invite researchers to contribute original research, case studies, and reviews that address topics related to the design and application of hardware accelerators for machine learning.

The topics relevant for this Special Issue include (but are not limited to) the following:

Low-power IoT applications;
Embedded FPGA and SoC implementations;
Embedded ASIC implementations;
Machine learning on Edge;
Efficient data processing algorithms.

Dr. Sergio Spanò
Prof. Dr. Gian Carlo Cardarilli
Dr. Luca Di Nunzio
Guest Editors

Manuscript Submission Information

Manuscripts should be submitted online at www.mdpi.com by registering and logging in to this website. Once you are registered, click here to go to the submission form. Manuscripts can be submitted until the deadline. All submissions that pass pre-check are peer-reviewed. Accepted papers will be published continuously in the journal (as soon as accepted) and will be listed together on the special issue website. Research articles, review articles as well as short communications are invited. For planned papers, a title and short abstract (about 250 words) can be sent to the Editorial Office for assessment.

Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-anonymized peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Electronics is an international peer-reviewed open access semimonthly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 2400 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

Keywords

embedded systems
digital electronics
low-power IoT
edge computing
FPGA
ASIC
systems-on-chips
machine learning

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Hardware Acceleration for Machine Learning in Electronics (9 articles)

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Research

33 pages, 2122 KB

Open AccessArticle

Asynchronous Co-Execution of PyTorch on Zynq-7000: FPGA Matrix Delegation and PS–PL Overlap for End-to-End Inference Throughput

by Omar Hernandez-Yañez, Alejandro Juarez-Lora, Jesús Yalja Montiel-Pérez, Victor H. Ponce-Ponce and Heron Molina-Lozano

Electronics 2026, 15(15), 3308; https://doi.org/10.3390/electronics15153308 - 27 Jul 2026

Viewed by 540

Abstract

Embedded systems increasingly require on-device deep learning, yet their processors must simultaneously handle real-time sensing, networking administration, and data control. Existing Field-Programmable Gate Array (FPGA) accelerators typically target peak per-operator throughput without addressing concurrent execution demands of real-time embedded platforms. This paper presents a systolic array-based accelerator prototype implemented on the Zynq-7000 SoC integrated directly into PyTorch, enabling dense linear algebra to be delegated to the FPGA chip while Cortex-A9 continues executing the software stack uninterrupted. Unlike traditional accelerators optimized for peak per-operator speed, this design prioritizes asynchronous co-executionbetween the processing system (PS, the dual-core Cortex-A9) and the programmable logic (PL): The PL performs tiled matrix multiplication, while the PS executes preprocessing, orchestration, and I/O data concurrently, increasing effective end-to-end throughput regardless of the relative isolated performance of CPU and FPGA. The proposed module includes high-level-synthesis (HLS)-based matrix multiplication, activation functions, and Advanced eXtensible Interface (AXI)-Stream Direct Memory Access (DMA) interfaces, wrapped as custom PyTorch kernels under the PetaLinux operating system. The results obtained on the PYNQ-Z2 board show that, once the DMA transfer time is included in the measurement, the FPGA path does not surpass Cortex-A9 in isolated per-operator latencies across the evaluated range; the benefit lies instead in delegating the matrix compute to the fabric at low incremental power while the host CPU cores stay available for concurrent tasks. A concurrent workload sweep across matrix sizes from

8 \times 8

256 \times 256

confirms that the co-execution mode sustains 98–99% of available PS compute throughput compared with a constant ≈50% in single-core blocking mode; the difference is statistically significant for all evaluated sizes (see Mann–Whitney U:

U = 25

p = 3.97 \times 10^{- 3}

, perfect discrimination,

n = 5

). A fair dual-core CPU-only baseline attains comparable PS availability, so this figure reflects the dual-core scheduling that co-execution enables rather than a per-operator advantage of the fabric; the accelerator’s distinct role is to perform the matrix arithmetic off the general-purpose cores at low incremental power. The design occupies only 8% of available look-up tables (LUTs) and 5% of digital signal processing (DSP) blocks, maintains 1.69 W power with a junction temperature of 44.5 °C, and achieves 96.10% MNIST accuracy under fixed-point arithmetic. Full article

(This article belongs to the Special Issue Hardware Acceleration for Machine Learning, 2nd Edition)

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23 pages, 4461 KB

Open AccessArticle

RTL-Level Power Optimization of CNN Accelerators via Clock Gating and Sparsity-Aware MAC Suppression on FPGA

by Dev Gohel, Achyuth Gundrapally and Kyuwon (Ken) Choi

Electronics 2026, 15(11), 2492; https://doi.org/10.3390/electronics15112492 - 5 Jun 2026

Viewed by 763

Abstract

Convolutional Neural Network (CNN) accelerators are widely deployed in edge Artificial Intelligence (AI), embedded vision, and object detection systems, but their hardware designs often incur significant power consumption due to intensive multiply–accumulate (MAC) operations, frequent register toggling, memory transactions, and persistent signal switching. This study examines Register Transfer Level (RTL)-level power optimization of a CNN accelerator on a Field-Programmable Gate Array (FPGA) using three design approaches: a baseline, a Local Explicit Clock Gating (LECG) + Memory Split scheme, and a sparsity-aware scheme. The LECG + Memory Split approach reduces redundant sequential and memory-switching operations, while the sparsity-aware scheme further minimizes arithmetic operations on zero-valued operands. FPGA power measurements on a Xilinx ZCU102 platform reveal a total power decrease from 3.644 W in the baseline to 2.775 W with LECG + Memory Split and 2.442 W with sparsity-aware optimization. This achieves up to a 32.99% reduction in total power without increasing Digital Signal Processing (DSP) block or Block Random Access Memory (BRAM) usage. The findings confirm that integrating control-based, memory-aware, and data-aware RTL methods enhances the power efficiency of CNN accelerators while maintaining the main compute and memory architectures. Full article

(This article belongs to the Special Issue Hardware Acceleration for Machine Learning, 2nd Edition)

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37 pages, 39405 KB

Open AccessArticle

Digital-Twin-Assisted Adaptive Sensor Scheduling for Energy Optimization in Battery-Powered Indoor Air Quality (IAQ) IoT Nodes

by Angel Marinov, Firgan Feradov, Tamer Abu-Alam and Boyan Shabanski

Electronics 2026, 15(11), 2395; https://doi.org/10.3390/electronics15112395 - 1 Jun 2026

Viewed by 551

Abstract

Battery-powered Internet of Things (IoT) sensor nodes for environmental monitoring face strict energy constraints, particularly when employing high-consumption sensors such as particulate matter sensors or gas analyzers. Extending operational lifetime without sacrificing measurement reliability remains a key challenge for large-scale air-quality monitoring deployments. This paper proposes a digital-twin-assisted adaptive sensing algorithm for reducing energy consumption by dynamically optimizing sensor usage for Indoor Air Quality (IAQ) monitoring system. The system consists of distributed sensing nodes and a central station that maintains digital twins to evaluate candidate sensing strategies based on historical data and environmental patterns. Strategies are assessed in terms of energy consumption and measurement fidelity and deployed only when a measurable improvement is achieved. The approach is evaluated across mobile and stationary sensor configurations used for monitoring indoor air quality in university laboratories while educational and research activities are carried out. For stationary nodes, clustering-based scheduling reduces the activation of high-power sensors, while for mobile nodes, variation-based triggering exploits correlations between equivalent and reference CO₂ measurements to limit energy-intensive sensing. Results demonstrate energy savings of up to approximately 70% while maintaining acceptable measurement fidelity. The findings show that reduced sensing can be used for system initialization, while digital twin evaluation enables reliable transition to adaptive sensing under suitable conditions. Full article

(This article belongs to the Special Issue Hardware Acceleration for Machine Learning, 2nd Edition)

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