Electronics 2025, 14(13), 2698; https://doi.org/10.3390/electronics14132698 (registering DOI) - 3 Jul 2025
Abstract
Next-generation smart sensing devices necessitate on-chip integration of power-efficient reference circuits. The latters are required to provide other circuit blocks with highly reliable bias signals, even in the presence of temperature shifts and supply voltage disturbances, while draining a small fraction of the
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Next-generation smart sensing devices necessitate on-chip integration of power-efficient reference circuits. The latters are required to provide other circuit blocks with highly reliable bias signals, even in the presence of temperature shifts and supply voltage disturbances, while draining a small fraction of the overall power budget. In particular, it is especially challenging to design current references with enhanced robustness and efficiency; hence, thorough exploration of novel architectures and design approaches is needed for this type of circuits. In this work, we propose a novel CMOS-only current reference, achieving temperature compensation by exploiting geometry dependences of the threshold voltage (specifically, the reverse short-channel effect and the narrow-channel effect). This allows reaching first-order temperature compensation within a single current reference core. Implemented in 0.18 µm CMOS, a version of the proposed current reference designed to deliver 141 nA (with 377 nW of total power consumption) achieved an average temperature coefficient equal to 194 ppm/°C (from −20 °C to 80 °C) and an average line sensitivity of −0.017%/V across post-layout statistical Monte Carlo simulations. Based on such findings, the newly proposed design methodology stands out as a noteworthy solution to design robust current references for power-constrained mixed-signal systems-on-chip.
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(This article belongs to the Section Microelectronics)
