Trustworthy AI Chips: Design, Verification and Defense Mechanisms

Dear Colleagues,

The rapid proliferation of artificial intelligence has made specialized AI chips (including DNN accelerators, NPUs, TPUs and edge AI processors) foundational to modern computing systems. As the bedrock of all AI systems, the trustworthiness and security of AI chips are of paramount importance to the entire AI ecosystem. The purpose of this Special Issue is to advance the state of the art in designing, verifying and defending trustworthy AI chips. This collection seeks to convey the most up-to-date topics and challenges in the AI chip security community. We seek original research that addresses the full lifecycle of AI chips—from architecture and circuit-level design through rigorous verification methodologies to practical defense mechanisms against both physical and algorithmic attacks. This Special Issue welcomes original research on (but not limited to) the following topics:

• Architectural support for AI security and privacy
• Cryptography and isolation-based approaches to achieve AI security and privacy
• Architectural and microarchitectural attacks and defenses for AI chip
• Defensive accelerator architecture for AI algorithmic defense methods
• Side-channel attack and defense, fault injection and physical tampering for AI chips
• Reverse engineering for AI chip models (model extraction from chips)
• Hardware Trojan detection, prevention and mitigation in AI chips
• Trusted execution environments (TEEs) and confidential computing for AI training and inference
• Hardware-software co-design for trustworthy AI systems
• Emerging threats and defenses in multi-tenant AI chips, edge AI
• Post-quantum secure AI hardware and lightweight cryptographic implementations
• Formal and ML-assisted verification techniques tailored to AI chips

Existing research on AI chips has primarily focused on improving computational efficiency, energy optimization and scalability of AI accelerators. In parallel, the hardware security community has extensively studied threats such as side-channel leakage, fault injection and hardware Trojans. This collection will usefully supplement existing literature in several ways. Hardware security venues (e.g., IEEE HOST, CHES, IEEE TIFS) have traditionally focused on general-purpose processors and cryptographic modules; AI hardware venues (e.g., IEEE Micro, ISCA, MICRO, DAC) have prioritized performance and efficiency. By centering on the unique security challenges of AI accelerators, this issue bridges these communities.

Prof. Dr. Xingbin Wang
Dr. Jiaji He
Guest Editors

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