Journal Description
Journal of Low Power Electronics and Applications
Journal of Low Power Electronics and Applications
is an international, peer-reviewed, open access journal on low power electronics published quarterly online by MDPI.
- Open Access— free for readers, with article processing charges (APC) paid by authors or their institutions.
- High Visibility: indexed within Scopus, ESCI (Web of Science), Inspec, and other databases.
- Rapid Publication: manuscripts are peer-reviewed and a first decision is provided to authors approximately 23.4 days after submission; acceptance to publication is undertaken in 2.8 days (median values for papers published in this journal in the first half of 2025).
- Journal Rank: CiteScore - Q2 (Electrical and Electronic Engineering)
- Recognition of Reviewers: reviewers who provide timely, thorough peer-review reports receive vouchers entitling them to a discount on the APC of their next publication in any MDPI journal, in appreciation of the work done.
- Journal Cluster of Electronic Engineering and Hardware Systems: Chips, Electronics, Hardware, Journal of Low Power Electronics and Applications, Microelectronics and Microwave.
Impact Factor:
1.8 (2024);
5-Year Impact Factor:
1.6 (2024)
Latest Articles
Adaptive Hybrid Switched-Capacitor Cell Balancing for 4-Cell Li-Ion Battery Pack with a Study of Pulse-Frequency Modulation Control
J. Low Power Electron. Appl. 2025, 15(4), 61; https://doi.org/10.3390/jlpea15040061 - 1 Oct 2025
Abstract
►
Show Figures
Battery cell balancing is crucial in series-connected lithium-ion packs to maximize usable capacity, ensure safe operation, and prolong cycle life. This paper presents a comprehensive study and a novel adaptive duty-cycled hybrid balancing system that combines passive bleed resistors and an active switched-capacitor
[...] Read more.
Battery cell balancing is crucial in series-connected lithium-ion packs to maximize usable capacity, ensure safe operation, and prolong cycle life. This paper presents a comprehensive study and a novel adaptive duty-cycled hybrid balancing system that combines passive bleed resistors and an active switched-capacitor (SC) balancer, specifically designed for a 4-cell series-connected battery pack. This work also explored open circuit voltage (OCV)-driven adaptive pulse-frequency modulation (PFM) active balancing to achieve higher efficiency and better balancing speed based on different system requirements. Finally, this paper compares passive, active (SC-based), and adaptive duty-cycled hybrid balancing strategies in detail, including theoretical modeling of energy transfer and efficiency for each method. Simulation showed that the adaptive hybrid balancer speeds state-of-charge (SoC) equalization by 16.24% compared to active-only balancing while maintaining an efficiency of 97.71% with minimal thermal stress. The simulation result also showed that adaptive active balancing was able to achieve a high efficiency of 99.86% and provided an additional design degree of freedom for different applications. The results indicate that the adaptive hybrid balancer offered an excellent trade-off between balancing speed, efficiency, and implementation simplicity for 4-cell Li-ion packs, making it highly suitable for applications such as high-voltage portable chargers.
Full article
Open AccessReview
MCU Intelligent Upgrades: An Overview of AI-Enabled Low-Power Technologies
by
Tong Zhang, Bosen Huang, Xiewen Liu, Jiaqi Fan, Junbo Li, Zhao Yue and Yanfang Wang
J. Low Power Electron. Appl. 2025, 15(4), 60; https://doi.org/10.3390/jlpea15040060 - 1 Oct 2025
Abstract
►▼
Show Figures
Microcontroller units (MCUs) serve as the core components of embedded systems. In the era of smart IoT, embedded devices are increasingly deployed on mobile platforms, leading to a growing demand for low-power consumption. As a result, low-power technology for MCUs has become increasingly
[...] Read more.
Microcontroller units (MCUs) serve as the core components of embedded systems. In the era of smart IoT, embedded devices are increasingly deployed on mobile platforms, leading to a growing demand for low-power consumption. As a result, low-power technology for MCUs has become increasingly critical. This paper systematically reviews the development history and current technical challenges of MCU low-power technology. It then focuses on analyzing system-level low-power optimization pathways for integrating MCUs with artificial intelligence (AI) technology, including lightweight AI algorithm design, model pruning, AI acceleration hardware (NPU, GPU), and heterogeneous computing architectures. It further elaborates on how AI technology empowers MCUs to achieve comprehensive low power consumption from four dimensions: task scheduling, power management, inference engine optimization, and communication and data processing. Through practical application cases in multiple fields such as smart home, healthcare, industrial automation, and smart agriculture, it verifies the significant advantages of MCUs combined with AI in performance improvement and power consumption optimization. Finally, this paper focuses on the key challenges that still need to be addressed in the intelligent upgrade of future MCU low power consumption and proposes in-depth research directions in areas such as the balance between lightweight model accuracy and robustness, the consistency and stability of edge-side collaborative computing, and the reliability and power consumption control of the sensor-storage-computing integrated architecture, providing clear guidance and prospects for future research.
Full article

Figure 1
Open AccessEditorial
Ultra-Low-Power ICs for the Internet of Things (2nd Edition)
by
Orazio Aiello
J. Low Power Electron. Appl. 2025, 15(4), 59; https://doi.org/10.3390/jlpea15040059 - 1 Oct 2025
Abstract
After the success of the first edition [...]
Full article
(This article belongs to the Special Issue Ultra-Low-Power ICs for the Internet of Things (2nd Edition))
Open AccessArticle
Active Quasi-Circulator Based on Wilkinson Power Divider for Low-Power Wireless Communication Systems
by
Kaijun Song, Xinsheng Chen and Zongrui He
J. Low Power Electron. Appl. 2025, 15(4), 58; https://doi.org/10.3390/jlpea15040058 - 1 Oct 2025
Abstract
►▼
Show Figures
This paper presents a microstrip active quasi-circulator designed for low-power wireless communication systems. The circuit consists of a second-order Wilkinson power divider and two power amplifiers with high gain and ultra-low noise characteristics. By leveraging the unidirectional transmission characteristics of the transistors and
[...] Read more.
This paper presents a microstrip active quasi-circulator designed for low-power wireless communication systems. The circuit consists of a second-order Wilkinson power divider and two power amplifiers with high gain and ultra-low noise characteristics. By leveraging the unidirectional transmission characteristics of the transistors and the isolation provided by resistors within the power divider, the interference between the transmitter (TX) and receiver (RX) is effectively suppressed. Additionally, thanks to the dual-amplifier architecture, no extra power amplification circuitry is required, thereby reducing the overall complexity and power consumption of the communication system. The detailed design procedure of the proposed quasi-circulator is presented. The measurement results show that, within the frequency range of 4.75 GHz to 6.11 GHz, the isolation between the TX and RX ports exceeds 20 dB, the return loss at each port is greater than 10 dB, and the transmission gains from the TX port to the antenna and from the antenna to the RX port are 3.1–8.7 dB and 2.7–4.0 dB, respectively, demonstrating a relative bandwidth of 25%.
Full article

Figure 1
Open AccessArticle
Research on Frequency Characteristic Fitting of LLC Switching-Mode Power Supply Under All Operating Conditions Based on FT-WOA-MLP
by
Jiale Guo, Rongsheng Han, Zibo Yang, Guoqing An, Rui Li and Long Zhang
J. Low Power Electron. Appl. 2025, 15(4), 57; https://doi.org/10.3390/jlpea15040057 - 28 Sep 2025
Abstract
►▼
Show Figures
The frequency characteristics of the switching-mode power supply (SMPS) control loop under all operating conditions are crucial for performance evaluation and defect detection. Traditional methods, relyingon experiments under preset conditions, struggle to achieve comprehensive evaluation. This study proposes a frequency characteristic fitting method
[...] Read more.
The frequency characteristics of the switching-mode power supply (SMPS) control loop under all operating conditions are crucial for performance evaluation and defect detection. Traditional methods, relyingon experiments under preset conditions, struggle to achieve comprehensive evaluation. This study proposes a frequency characteristic fitting method for all operating conditions based on FT-WOA-MLP. A discrete-point dataset covering all conditions of an LLC SMPS was obtained using the small-signal perturbation method, including input voltage, output current, injection frequency, and corresponding amplitude- and phase-frequency characteristics. The multilayer perceptron (MLP) model was trained on the training set covering all operating conditions, with the whale optimization algorithm (WOA) used to optimize the learning rate, and fine tuning (FT) applied to further enhance accuracy. Independent test set validation showed that, for amplitude-frequency characteristics, the mean absolute error (MAE) was 2.0995, the mean absolute percentage error (MAPE) was 0.0974, the root mean square error (RMSE) was 4.0474, and the coefficient of determination (R2) reached 0.92; for phase-frequency characteristics, the MAE was 3.502, the MAPE was 0.0956, the RMSE was 10.5192, and the R2 reached 0.94. The method accurately fits frequency characteristics under all conditions, supporting defect identification and performance optimization.
Full article

Figure 1
Open AccessArticle
Data Analysis of Electrical Impedance Spectroscopy-Based Biosensors Using Artificial Neural Networks for Resource Constrained Devices
by
Marco Grossi and Martin Omaña
J. Low Power Electron. Appl. 2025, 15(4), 56; https://doi.org/10.3390/jlpea15040056 - 26 Sep 2025
Abstract
►▼
Show Figures
Portable and wearable sensors have gained attention in recent years to perform measurements in many different applications. Sensors based on Electrical Impedance Spectroscopy (EIS) are particularly promising, because they can make accurate measurements with minimum perturbation to the sample under test. Electrochemical biosensors
[...] Read more.
Portable and wearable sensors have gained attention in recent years to perform measurements in many different applications. Sensors based on Electrical Impedance Spectroscopy (EIS) are particularly promising, because they can make accurate measurements with minimum perturbation to the sample under test. Electrochemical biosensors are devices that use electrochemical techniques to measure a target analyte. In the case of electrochemical biosensors based on EIS, the measured impedance spectrum is fitted to that of an equivalent electrical circuit, whose component values are then used to estimate the concentration of the target analyte. Fitting EIS data is usually carried out by sophisticated algorithms running on a PC. In this paper, we have evaluated the feasibility to perform EIS data fitting using simple Artificial Neural Networks (ANNs) that can be run on resource constrained microcontrollers, which are typically used for portable and wearable sensors. We considered a typical case of an impedance spectrum in the range 0.1–10 kHz, modeled by using the simplified Randles equivalent circuit. Our analyses have shown that simple ANNs can be a low power alternative to perform EIS data fitting on low-cost microcontrollers with a memory occupation in the order of kilo bytes and a measurement accuracy between 1% and 3%.
Full article

Figure 1
Open AccessReview
Wake-Up Receivers: A Review of Architectures Analysis, Design Techniques, Theories and Frontiers
by
Suhao Chen, Xiaopeng Yu and Xiongchun Huang
J. Low Power Electron. Appl. 2025, 15(4), 55; https://doi.org/10.3390/jlpea15040055 - 23 Sep 2025
Abstract
The rapid growth of the Internet of Things (IoT) has driven the need for ultra-low-power wireless communication systems. Wake-up receivers (WuRXs) have emerged as a key technology to enable energy-efficient, near-always-on operation for IoT devices. This review explores the state of the art
[...] Read more.
The rapid growth of the Internet of Things (IoT) has driven the need for ultra-low-power wireless communication systems. Wake-up receivers (WuRXs) have emerged as a key technology to enable energy-efficient, near-always-on operation for IoT devices. This review explores the state of the art in WuRXs design, focusing on low-power architectures, key trade-offs, and recent advancements. We discuss the challenges in achieving low power consumption while maintaining sensitivity, power consumption, and interference resilience. The review highlights the evolution from radio frequency (RF) envelope detection architectures to more complex heterodyne and subthreshold designs and concludes with future directions for WuRXs research.
Full article
(This article belongs to the Topic Advanced Integrated Circuit Design and Application)
►▼
Show Figures

Figure 1
Open AccessArticle
Class E ZVS Resonant Inverter with CLC Filter and PLL-Based Resonant Frequency Tracking for Ultrasonic Piezoelectric Transducer
by
Apinan Aurasopon, Boontan Sriboonrueng, Jirapong Jittakort and Saichol Chudjuarjeen
J. Low Power Electron. Appl. 2025, 15(3), 54; https://doi.org/10.3390/jlpea15030054 - 22 Sep 2025
Abstract
►▼
Show Figures
This paper presents a Class E zero-voltage soft-switching (ZVS) resonant inverter integrated with a CLC filter and a digital resonant frequency tracking technique for driving a piezoelectric ceramic transducer (PZT) in ultrasonic cleaning applications. A digital signal processor (DSP) is used to dynamically
[...] Read more.
This paper presents a Class E zero-voltage soft-switching (ZVS) resonant inverter integrated with a CLC filter and a digital resonant frequency tracking technique for driving a piezoelectric ceramic transducer (PZT) in ultrasonic cleaning applications. A digital signal processor (DSP) is used to dynamically monitor and adjust the operating frequency in response to slight variations in the cleaning load, employing a phase-locked loop (PLL) control scheme. The proposed method ensures that the inverter maintains ZVS operation across a frequency range from 30.0 kHz to 34.0 kHz, thereby improving energy efficiency and reducing switching losses. The system is capable of delivering a stable power output of 100 W. Both the simulation and experimental results validate the effectiveness of the proposed technique, demonstrating improved performance under varying load conditions. The combination of CLC filtering and frequency tracking offers a compact and robust solution suitable for ultrasonic cleaner systems and similar resonant-load applications.
Full article

Figure 1
Open AccessArticle
A Physical Unclonable Function Based on a Differential Subthreshold PMOS Array with 9.73 × 10−4 Stabilized BER and 1.3 pJ/bit in 65 nm
by
Benjamin Zambrano, Sebastiano Strangio, Esteban Garzón, Alessandro Catania, Giuseppe Iannaccone and Marco Lanuzza
J. Low Power Electron. Appl. 2025, 15(3), 53; https://doi.org/10.3390/jlpea15030053 - 17 Sep 2025
Abstract
This paper introduces a physical unclonable function (PUF) based on a differential array of minimum-sized PMOS devices. Each response bit is obtained by comparing the two analog outputs of the differential array through a dynamic comparator with a trimmable offset. This offset is
[...] Read more.
This paper introduces a physical unclonable function (PUF) based on a differential array of minimum-sized PMOS devices. Each response bit is obtained by comparing the two analog outputs of the differential array through a dynamic comparator with a trimmable offset. This offset is effectively used to mask potentially unstable response bits. To further improve PUF reliability, spatial majority voting is also implemented, resulting in a near-zero (< ) bit error rate (BER) at 1.2 V and 25 . Under variations in supply voltage (0.8–1.3 V) and temperature (0–75 ), the native bit error rate of 3.5% is reduced to after stabilization, consuming only 1.37 per output bit.
Full article
(This article belongs to the Topic Advanced Integrated Circuit Design and Application)
►▼
Show Figures

Figure 1
Open AccessArticle
A Low-Voltage, Low-Power 2.5 GHz Ring Oscillator with Process and Temperature Compensation
by
Dimitris Patrinos and George Souliotis
J. Low Power Electron. Appl. 2025, 15(3), 52; https://doi.org/10.3390/jlpea15030052 - 17 Sep 2025
Abstract
►▼
Show Figures
A ring-oscillator based voltage-controlled oscillator (VCO) architecture with reduced frequency drift across temperature and process variations is presented in this paper. The frequency stability is achieved through two dedicated compensation techniques: a temperature compensation circuit that generates a proportional-to-absolute-temperature (PTAT) current to mitigate
[...] Read more.
A ring-oscillator based voltage-controlled oscillator (VCO) architecture with reduced frequency drift across temperature and process variations is presented in this paper. The frequency stability is achieved through two dedicated compensation techniques: a temperature compensation circuit that generates a proportional-to-absolute-temperature (PTAT) current to mitigate frequency shifts due to temperature changes, and a process compensation circuit that dynamically adjusts the frequency based on detected process corners. The proposed design is implemented in a 22 nm CMOS technology with a 0.8 V supply voltage and targets a nominal oscillation frequency of 2.5 GHz. The post-layout simulation results demonstrate a significant improvement in frequency stability, reducing temperature-induced frequency drift from 23.9% to a range of 5.4% over the −40 °C to 125 °C temperature range for the typical corner. Combining temperature and process compensation, the frequency drift is improved from 47.3% to better than 7.2%. The VCO also achieves a phase noise value about −80 dBc/Hz at a 1 MHz offset with an average power consumption of 380 µW, including the tuning mechanism and the compensation circuits.
Full article

Figure 1
Open AccessArticle
Design of Tri-Mode Frequency Reconfigurable UAV Conformal Antenna Based on Frequency Selection Network
by
Teng Bao, Mingmin Zhu, Zhifeng He, Yi Zhang, Guoliang Yu, Yang Qiu, Jiawei Wang, Yan Li, Haibin Zhu and Hao-Miao Zhou
J. Low Power Electron. Appl. 2025, 15(3), 51; https://doi.org/10.3390/jlpea15030051 - 10 Sep 2025
Abstract
►▼
Show Figures
With the rapid growth of unmanned aerial vehicles (UAVs) and IoT users, spectrum resources are becoming increasingly scarce, making cognitive radio (CR) technology a key approach to improving spectrum utilization. However, traditional antennas are difficult to meet the lightweight, compact, and low-drag requirements
[...] Read more.
With the rapid growth of unmanned aerial vehicles (UAVs) and IoT users, spectrum resources are becoming increasingly scarce, making cognitive radio (CR) technology a key approach to improving spectrum utilization. However, traditional antennas are difficult to meet the lightweight, compact, and low-drag requirements of small UAVs due to spatial constraints. This paper proposes a tri-mode frequency reconfigurable flexible antenna that can be conformally integrated onto UAV wing arms to enable CR dynamic frequency communication. The antenna uses a polyimide (PI) substrate and has compact dimensions of 31.4 × 58 × 0.05 mm3. A microstrip line-based frequency-selective network is designed, incorporating PIN and varactor diodes to realize three operation modes, dual-band (2.25~3.55 GHz, 5.6~6.75 GHz), single-band (3.35~5.3 GHz), and continuous tuning (4.3~6.1 GHz), covering WLAN, WiMAX, and 5G NR bands. Test results show that the antenna maintains stable performance under conformal conditions, with frequency shifts less than 4%, gain (3.65~4.77 dBi), and radiation efficiency between 67.2% and 82.9%. The tuning ratio reaches 38.8% in the continuous mode. This design offers a new solution for CR communication in compact UAV platforms and shows promising application potential.
Full article

Figure 1
Open AccessArticle
Alleviating the Communication Bottleneck in Neuromorphic Computing with Custom-Designed Spiking Neural Networks
by
James S. Plank, Charles P. Rizzo, Bryson Gullett, Keegan E. M. Dent and Catherine D. Schuman
J. Low Power Electron. Appl. 2025, 15(3), 50; https://doi.org/10.3390/jlpea15030050 - 8 Sep 2025
Abstract
For most, if not all, AI-accelerated hardware, communication with the agent is expensive and heavily bottlenecks the hardware performance. This omnipresent hardware restriction is also found in neuromorphic computing: a novel style of computing that involves deploying spiking neural networks to specialized hardware
[...] Read more.
For most, if not all, AI-accelerated hardware, communication with the agent is expensive and heavily bottlenecks the hardware performance. This omnipresent hardware restriction is also found in neuromorphic computing: a novel style of computing that involves deploying spiking neural networks to specialized hardware to achieve low size, weight, and power (SWaP) compute. In neuromorphic computing, spike trains, times, and values are used to communicate information to, from, and within the spiking neural network. Input data, in order to be presented to a spiking neural network, must first be encoded as spikes. After processing the data, spikes are communicated by the network that represent some classification or decision that must be processed by decoder logic. In this paper, we first present principles for interconverting between spike trains, times, and values using custom-designed spiking subnetworks. Specifically, we present seven networks that encompass the 15 conversion scenarios between these encodings. We then perform three case studies where we either custom design a novel network or augment existing neural networks with these conversion subnetworks to vastly improve their communication performance with the outside world. We employ a classic space vs. time tradeoff by pushing spike data encoding and decoding techniques into the network mesh (increasing space) in order to minimize intra- and extranetwork communication time. This results in a classification inference speedup of 23× and a control inference speedup of 4.3× on field-programmable gate array hardware.
Full article
(This article belongs to the Special Issue Neuromorphic Computing for Edge Applications)
►▼
Show Figures

Figure 1
Open AccessArticle
Fast Energy Recovery During Motor Braking: Analysis and Simulation
by
Lin Xu, Wengan Li, Zenglong Zhao and Fanyi Meng
J. Low Power Electron. Appl. 2025, 15(3), 49; https://doi.org/10.3390/jlpea15030049 - 22 Aug 2025
Abstract
►▼
Show Figures
At present, environmental pollution is becoming more and more serious, and the energy problem is becoming more prominent. Energy-braking recovery can collect the mechanical energy lost in the traditional braking process and convert it into electricity or other forms of energy for vehicle
[...] Read more.
At present, environmental pollution is becoming more and more serious, and the energy problem is becoming more prominent. Energy-braking recovery can collect the mechanical energy lost in the traditional braking process and convert it into electricity or other forms of energy for vehicle reuse, thus reducing carbon emissions, achieving energy saving and emission reduction, and promoting green development. Based on this, this paper studies the energy-braking recovery method. The study focuses specifically on the recovery of energy during vehicle braking triggered by brake-signal activation, without addressing alternative deceleration strategies under braking conditions. The proposed energy-braking recovery scheme is evaluated primarily through simulation, with the analysis grounded in practical application scenarios and leveraging existing technologies. Firstly, the principle of energy-braking recovery is introduced, and the method of estimating the State on Charge (SOC) of the battery and controlling the motor speed is determined. Then, the simulation model of the energy brake recovery system is built with MATLAB R2023b (MathWorks, Natick, MA, USA), and the design ideas and specific structures of the three modules of the simulation model are introduced in detail. Finally, the results of the simulated motor speed and SOC value of the battery are analysed, and it is confirmed that they meet the requirements of the system and achieve close to the ideal effect.
Full article

Figure 1
Open AccessArticle
A Non-Isolated High Gain Step-Up DC/DC Converter Based on Coupled Inductor with Reduced Voltage Stresses
by
Yuqing Yang, Song Xu, Wei Jiang and Seiji Hashimoto
J. Low Power Electron. Appl. 2025, 15(3), 48; https://doi.org/10.3390/jlpea15030048 - 22 Aug 2025
Abstract
Hybrid electric vehicles (HEVs) have gained significant attention for their superior energy efficiency and are becoming a predominant mode of urban transportation. The DC/DC converter plays a critical role in HEV energy management systems, especially in matching the voltage levels between the battery
[...] Read more.
Hybrid electric vehicles (HEVs) have gained significant attention for their superior energy efficiency and are becoming a predominant mode of urban transportation. The DC/DC converter plays a critical role in HEV energy management systems, especially in matching the voltage levels between the battery and DC bus. This paper proposes a novel high-gain DC/DC converter with a wide input voltage range based on coupled inductors. The innovation lies in the integration of a resonant cavity and the simultaneous realization of zero-voltage switching (ZVS) and zero-current switching (ZCS), effectively reducing both voltage/current stresses on the power switches and switching losses. Compared with conventional topologies, the proposed design achieves higher voltage gain without extreme duty cycles, improved conversion efficiency, and enhanced reliability. Detailed operating principles are analyzed, and design conditions for voltage stress reduction, gain extension, and soft switching are derived. The simulation model has been conducted in a PSIM environment, and a 300 W experimental prototype, implemented using a dsPIC33FJ64GS606 digital controller, has been established and demonstrates 93% peak efficiency at a 10 times voltage gain. The performance and practical feasibility of the proposed topology have been evaluated by both simulation and experiments.
Full article
(This article belongs to the Topic Advanced Integrated Circuit Design and Application)
►▼
Show Figures

Figure 1
Open AccessArticle
Design of a Power-Aware Reconfigurable and Parameterizable Pseudorandom Pattern Generator for BIST-Based Applications
by
Geethu Remadevi Somanathan, Ujarla Harshavardhan Reddy and Ramesh Bhakthavatchalu
J. Low Power Electron. Appl. 2025, 15(3), 47; https://doi.org/10.3390/jlpea15030047 - 15 Aug 2025
Abstract
►▼
Show Figures
This paper presents a power-aware Reconfigurable Parameterizable Pseudorandom Pattern Generator (RP-PRPG) for a number of applications, including built in self-testing (BIST) and cryptography. Linear Feedback Shift Registers (LFSRs) are broadly utilized in pattern generation due to their efficiency and simplicity. However, the diversity
[...] Read more.
This paper presents a power-aware Reconfigurable Parameterizable Pseudorandom Pattern Generator (RP-PRPG) for a number of applications, including built in self-testing (BIST) and cryptography. Linear Feedback Shift Registers (LFSRs) are broadly utilized in pattern generation due to their efficiency and simplicity. However, the diversity of generated patterns, as well as their power consumption, improves through circuit modifications. This work explores enhancements to LFSR structures to achieve broader range of patterns with reduced power consumption for BIST-based applications. The proposed circuit constructed on the LFSR platform can be programmed to generate patterns with varying degrees of different LFSR configurations. Diverse set of patterns of any circuit arrangement can be created using any characteristic polynomial and by utilizing the reseeding capacity of the circuit. The circuit combines a double-tier linear feedback circuit with zero forcing methods, resulting in more than 70% transition reduction, thus significantly lowering power dissipation. The behaviour of the proposed circuit is assessed for characteristic polynomials with degrees ranging from 4 to 128 using various Linear Feedback Shift Register (LFSR) topologies. For reconfigurable HDL and ASIC synthesis, the power-aware RP-PRPG can be used to generate an efficient set of stream ciphers as well as applications involving the scan-for-test protocol.
Full article

Figure 1
Open AccessArticle
Federated Multi-Stage Attention Neural Network for Multi-Label Electricity Scene Classification
by
Lei Zhong, Xuejiao Jiang, Jialong Xu, Kaihong Zheng, Min Wu, Lei Gao, Chao Ma, Dewen Zhu and Yuan Ai
J. Low Power Electron. Appl. 2025, 15(3), 46; https://doi.org/10.3390/jlpea15030046 - 5 Aug 2025
Abstract
Privacy-sensitive electricity scene classification requires robust models under data localization constraints, making federated learning (FL) a suitable framework. Existing FL frameworks face two critical challenges in multi-label electricity scene classification: (1) Label correlations and their strengths significantly impact classification performance. (2) Electricity scene
[...] Read more.
Privacy-sensitive electricity scene classification requires robust models under data localization constraints, making federated learning (FL) a suitable framework. Existing FL frameworks face two critical challenges in multi-label electricity scene classification: (1) Label correlations and their strengths significantly impact classification performance. (2) Electricity scene data and labels show distributional inconsistencies across regions. However, current FL frameworks lack explicit modeling of label correlation strengths, and locally trained regional models naturally capture these differences, leading to regional differences in their model parameters. In this scenario, the server’s standard single-stage aggregation often over-averages the global model’s parameters, reducing its discriminative ability. To address these issues, we propose FMMAN, a federated multi-stage attention neural network for multi-label electricity scene classification. The main contributions of this FMMAN lie in label correlation learning and the stepwise model aggregation. It splits the client–server interaction into multiple stages: (1) Clients train models locally to encode features and label correlation strengths after receiving the server’s initial model. (2) The server clusters these locally trained models into K groups to ensure that models within a group have more consistent parameters and generates K prototype models via intra-group aggregation to reduce over-averaging. The K models are then distributed back to the clients. (3) Clients refine their models using the K prototypes with contrastive group-specific consistency regularization to further mitigate over-averaging, and sends the refined model back to the server. (4) Finally, the server aggregates the models into a global model. Experiments on multi-label benchmarks verify that FMMAN outperforms baseline methods.
Full article
(This article belongs to the Special Issue Advances in Low Power Neuromorphic Computing: Models, Algorithms, and Applications)
►▼
Show Figures

Figure 1
Open AccessArticle
Event-Triggered Model Predictive Control of Buck Converter with Disturbances: Design and Experimentation
by
Ziyuan Yang, Shengquan Li, Kaiwen Cao, Donglei Chen, Juan Li and Wei Cao
J. Low Power Electron. Appl. 2025, 15(3), 45; https://doi.org/10.3390/jlpea15030045 - 1 Aug 2025
Abstract
►▼
Show Figures
Considering the challenges posed by traditional continuous control set model predictive control (CCS-MPC) calculations, this paper proposes an event-triggered-based model predictive control (ET-MPC). First, a novel tracking error state-space model is proposed to improve tracking performance. Second, a reduced-order extended state observer (RESO)
[...] Read more.
Considering the challenges posed by traditional continuous control set model predictive control (CCS-MPC) calculations, this paper proposes an event-triggered-based model predictive control (ET-MPC). First, a novel tracking error state-space model is proposed to improve tracking performance. Second, a reduced-order extended state observer (RESO) is designed to estimate and compensate for the total disturbances, thereby effectively improving robustness against the variations of the load resistance and reference voltage. At the same time, RESO significantly reduces computational complexity and accelerates the convergence speed of state estimation. Subsequently, an event trigger mechanism is introduced to enhance the MPC with a threshold function for the converter status. Finally, the reduced-order extended state observer-based model predictive control (RESO-MPC) is compared with the proposed ET-MPC through experiments. The ripple voltage of ET-MPC is within 2%, and the computational burden is reduced by more than 57%, verifying the effectiveness of the proposed ET-MPC.
Full article

Figure 1
Open AccessArticle
Simulation of Propagation Characteristics and Field Distribution in Cylindrical Photonic Crystals Composed of Near-Zero Materials and Metal
by
Zhihao Xu, Dan Zhang, Rongkang Xuan, Shenxiang Yang and Na Wang
J. Low Power Electron. Appl. 2025, 15(3), 44; https://doi.org/10.3390/jlpea15030044 - 31 Jul 2025
Abstract
►▼
Show Figures
This study investigates the propagation characteristics and field distribution of photonic crystals composed of epsilon-near-zero (ENZ) materials and metal cylinders. The research reveals that the cutoff frequency of the photonic crystal formed by combining metal cylinders with an ENZ background is independent of
[...] Read more.
This study investigates the propagation characteristics and field distribution of photonic crystals composed of epsilon-near-zero (ENZ) materials and metal cylinders. The research reveals that the cutoff frequency of the photonic crystal formed by combining metal cylinders with an ENZ background is independent of the volume fraction of the metal cylinders and exhibits a stop-band profile within the measured frequency range. This unique behavior is attributed to the scattering of long-wavelength light when the wavelength approaches the effective wavelength range of the ENZ material. Taking advantage of this feature, the study selectively filters specific wavelength ranges from the mid-frequency band by varying the ratio of cylinder radius to lattice constant (R/a). Decreasing the R/a ratio enables the design of waveguide devices that operate over a broader guided wavelength range within the intermediate-frequency band. The findings emphasize the importance of the interaction between light and ENZ materials in shaping the transmission characteristics of photonic crystal structures.
Full article

Figure 1
Open AccessArticle
A Novel Low-Power Bipolar DC–DC Converter with Voltage Self-Balancing
by
Yangfan Liu, Qixiao Li and Zhongxuan Wang
J. Low Power Electron. Appl. 2025, 15(3), 43; https://doi.org/10.3390/jlpea15030043 - 24 Jul 2025
Abstract
►▼
Show Figures
Bipolar power supply can effectively reduce line losses and optimize power transmission. This paper proposes a low-power bipolar DC–DC converter with voltage self-balancing, which not only achieves bipolar output but also automatically balances the inter-pole voltage under load imbalance conditions without requiring additional
[...] Read more.
Bipolar power supply can effectively reduce line losses and optimize power transmission. This paper proposes a low-power bipolar DC–DC converter with voltage self-balancing, which not only achieves bipolar output but also automatically balances the inter-pole voltage under load imbalance conditions without requiring additional voltage balancing control. This paper first elaborates on the derivation process of the proposed converter, then analyzes its working principles and performance characteristics. A 400 W experimental prototype is built to validate the correctness of the theoretical analysis and the voltage self-balancing capability. Finally, loss analysis and conclusions are presented.
Full article

Figure 1
Open AccessArticle
Microstrip Line Modeling Taking into Account Dispersion Using a General-Purpose SPICE Simulator
by
Vadim Kuznetsov
J. Low Power Electron. Appl. 2025, 15(3), 42; https://doi.org/10.3390/jlpea15030042 - 22 Jul 2025
Abstract
►▼
Show Figures
XSPICE models for a generic transmission line, a microstrip line, and coupled microstrips are presented. The developed models extend general-purpose circuit simulation tools using RF circuits design features. The models could be used for circuit simulation in frequency, DC, and time domains for
[...] Read more.
XSPICE models for a generic transmission line, a microstrip line, and coupled microstrips are presented. The developed models extend general-purpose circuit simulation tools using RF circuits design features. The models could be used for circuit simulation in frequency, DC, and time domains for any active or passive RF or microwave schematic (including microwave monolithic integrated circuits—MMICs) involving transmission lines. The presented models could be used with any circuit simulation backend supporting XSPICE extensions and could be integrated without patching the core simulator code. The presented XSPICE models for microstrip lines take into account the frequency dependency of characteristic impedance and dispersion. The models were designed using open-source circuit simulation software. This study provides a practical example of the low-noise RF amplifier (LNA) design with Ngspice simulation backend using the proposed models.
Full article

Figure 1
Highly Accessed Articles
Latest Books
E-Mail Alert
News
Topics
Topic in
Electronics, Eng, JLPEA, Micromachines, Nanomaterials
Advanced Integrated Circuit Design and Application
Topic Editors: Shoue Chen, Xiaolong Wang, Ke XieDeadline: 30 April 2026
Topic in
Applied Mechanics, JLPEA, JSAN
Application of IOT on Manufacturing, Communication and Engineering, 2nd Volume
Topic Editors: Teen-Hang Meen, Chun-Yen Chang, Charles Tijus, Cheng-Fu Yang, Shu-Han LiaoDeadline: 31 May 2026

Conferences
Special Issues
Special Issue in
JLPEA
Emerging Trends in Low-Power CMOS Technologies
Guest Editor: Hongming LyuDeadline: 15 October 2025
Special Issue in
JLPEA
Ultra-Low-Power ICs for the Internet of Things (3rd Edition)
Guest Editor: Orazio AielloDeadline: 31 October 2025
Special Issue in
JLPEA
Energy Consumption Management in Electronic Systems
Guest Editors: Spyridon Nikolaidis, Ronald TetzlaffDeadline: 31 December 2025
Special Issue in
JLPEA
Electron Devices and Solid-State Circuits (EDSSC 2025)
Guest Editors: Lei Xu, Yuan Xiao Ma, Yitu Wang, Zhihua ZhuDeadline: 31 January 2026