Neuromorphic Computing for Edge Applications

Special Issue Editors


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Guest Editor
Department of Computer Science, The University of Manchester, Manchester M13 9PL, UK
Interests: neuromorphic computing; SNNs; event-driven perception; low-energy computing; embedded systems; sensor fusion

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Guest Editor
Department of Computer Science, University of Manchester, Manchester M13 9PL, UK
Interests: neuromorphic computing; spiking neural networks; real-time computing; low-power computing

Special Issue Information

Dear Colleagues,

Our society’s growing demand to integrate artificial intelligence in edge devices poses a significant challenge to traditional computing systems, which struggle to maintain low-power requirements while performing online real-time computational tasks. Neuromorphic computing, taking inspiration from biological computational principles, offers a valid low-energy alternative for real-time edge applications, bridging novel engineering principles with artificial intelligence.

This Special Issue aims to present the latest advances in low-energy neuromorphic technologies and algorithms for edge computing applications. Contributions in the form of original research articles, comprehensive review papers, and case studies are all welcome.

This Special Issue will cover topics including, but not limited to, the following:

  • Energy-efficient neuromorphic architectures for edge computing applications;
  • Event-based sensing technologies and algorithms;
  • Low-power sensor fusion applications;
  • Biologically inspired algorithms for low-power edge applications;
  • Emerging technologies and concepts for low-energy computing;
  • In/near-memory computing paradigms for edge applications;
  • Reversible neuromorphic architectures.

Dr. Luca Peres
Dr. Oliver Rhodes
Guest Editors

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Keywords

  • neuromorphic computing
  • low-energy computing
  • event-based sensing
  • spiking neural networks
  • edge computing
  • IoT

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Published Papers (1 paper)

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Research

27 pages, 730 KB  
Article
Alleviating the Communication Bottleneck in Neuromorphic Computing with Custom-Designed Spiking Neural Networks
by James S. Plank, Charles P. Rizzo, Bryson Gullett, Keegan E. M. Dent and Catherine D. Schuman
J. Low Power Electron. Appl. 2025, 15(3), 50; https://doi.org/10.3390/jlpea15030050 - 8 Sep 2025
Abstract
For most, if not all, AI-accelerated hardware, communication with the agent is expensive and heavily bottlenecks the hardware performance. This omnipresent hardware restriction is also found in neuromorphic computing: a novel style of computing that involves deploying spiking neural networks to specialized hardware [...] Read more.
For most, if not all, AI-accelerated hardware, communication with the agent is expensive and heavily bottlenecks the hardware performance. This omnipresent hardware restriction is also found in neuromorphic computing: a novel style of computing that involves deploying spiking neural networks to specialized hardware to achieve low size, weight, and power (SWaP) compute. In neuromorphic computing, spike trains, times, and values are used to communicate information to, from, and within the spiking neural network. Input data, in order to be presented to a spiking neural network, must first be encoded as spikes. After processing the data, spikes are communicated by the network that represent some classification or decision that must be processed by decoder logic. In this paper, we first present principles for interconverting between spike trains, times, and values using custom-designed spiking subnetworks. Specifically, we present seven networks that encompass the 15 conversion scenarios between these encodings. We then perform three case studies where we either custom design a novel network or augment existing neural networks with these conversion subnetworks to vastly improve their communication performance with the outside world. We employ a classic space vs. time tradeoff by pushing spike data encoding and decoding techniques into the network mesh (increasing space) in order to minimize intra- and extranetwork communication time. This results in a classification inference speedup of 23× and a control inference speedup of 4.3× on field-programmable gate array hardware. Full article
(This article belongs to the Special Issue Neuromorphic Computing for Edge Applications)
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