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Ultra-Low-Power ICs for the Internet of Things (3rd Edition)
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Ultra-Low-Power ICs for the Internet of Things (3rd Edition)

A special issue of Journal of Low Power Electronics and Applications (ISSN 2079-9268).

Deadline for manuscript submissions: 31 October 2026 | Viewed by 4138

Special Issue Editor

Dr. Orazio Aiello

E-Mail Website
Guest Editor
Department of Electrical, Electronic, Telecommunications Engineering and Naval Architecture (DITEN), University of Genoa, Via Opera Pia 11a, I-16145 Genova, Italy
Interests: energy-efficient integrated circuit design; mostly-digital/synthesizable interfaces; ultra low power ICs for the Internet of Things (IoT); ultra-low-voltage and voltage scalable ICs
Special Issues, Collections and Topics in MDPI journals

Special Issue Information

Dear Colleagues,

Ultra-low-voltage/power analog and digital ICs, powered by energy harvesters, face the challenges of small area occupation, low design effort, and technology/design portability, which are needed in this Internet-of-Things (IoT) era, which, in itself, has experienced exponential growth in relation to interconnected sensor nodes.

This Special Issue aims to attract original research articles related to the design and application of ultra-low-voltage/power, digital-based, and fully synthesizable ICs in this framework.

The topics of this Special Issue include but are not limited to

  • Ultra-low-power interfaces for the Internet of Things: energy-efficient and power/voltage scalable, analog, and mixed-signal IC;
  • Inverter- and digital-based design methodologies of ultra-low power ICs;
  • IC solution for ultra-low-voltage, energy, and standby power consumption systems;
  • Automated design methodology to decrease the time-to-market;
  • Energy harvesting and power management circuit for IoT devices;
  • Ultra-low-power/voltage ICs for instrumentation and communication applications.

Dr. Orazio Aiello
Guest Editor

Manuscript Submission Information

Manuscripts should be submitted online at www.mdpi.com by registering and logging in to this website. Once you are registered, click here to go to the submission form. Manuscripts can be submitted until the deadline. All submissions that pass pre-check are peer-reviewed. Accepted papers will be published continuously in the journal (as soon as accepted) and will be listed together on the special issue website. Research articles, review articles as well as short communications are invited. For planned papers, a title and short abstract (about 250 words) can be sent to the Editorial Office for assessment.

Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Journal of Low Power Electronics and Applications is an international peer-reviewed open access quarterly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 1800 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

Keywords

  • ultra-low-power/voltage ICs for IoT applications
  • advancements in energy-aware design techniques
  • ultra-low-power front-end electronics
  • energy-efficient ICs
  • digital-based design methodologies
  • ultra-low-power sensors and energy-neutral devices
  • energy harvesting and power management circuit

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Related Special Issues

Published Papers (4 papers)

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Research

14 pages, 4372 KB  
Article
A Low-Power 68.4 dB Signal-to-Noise-and-Distortion Ratio Noise-Shaping SAR ADC for Biomedical Applications
by Thi Phuong Ha, The Khai Chu, Van Tung Nguyen, Orazio Aiello and Xuan Thanh Pham
J. Low Power Electron. Appl. 2026, 16(2), 17; https://doi.org/10.3390/jlpea16020017 - 7 May 2026
Viewed by 164
Abstract
This paper introduces a novel analog-to-digital converter (ADC) employing a passive noise-shaping (NS) technique combined with a chopper-stabilized comparator, enhancing performance and reducing ripple factor while maintaining low power consumption. The NS architecture is built on a cascade-integrator feedforward (CIFF) structure, using both [...] Read more.
This paper introduces a novel analog-to-digital converter (ADC) employing a passive noise-shaping (NS) technique combined with a chopper-stabilized comparator, enhancing performance and reducing ripple factor while maintaining low power consumption. The NS architecture is built on a cascade-integrator feedforward (CIFF) structure, using both infinite- and finite-impulse response filters to minimize quantization and kT/C noise. Additionally, it employs a low-power two-stage chopper amplifier to compensate for the offset voltage and enhance system stability. Validated according to the 180 nm CMOS process, the proposed ADC has an effective number of bits of 10.6, a signal-to-noise-and-distortion ratio of 68.4 dB, and a signal-to-noise ratio of 59.33 dB. With a compact area of 0.17 mm2 and a power consumption of 650 µW from a 1.8 V supply, the proposal is well suited to biomedical sensor applications requiring strict accuracy and low energy consumption. Full article
(This article belongs to the Special Issue Ultra-Low-Power ICs for the Internet of Things (3rd Edition))
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18 pages, 3099 KB  
Article
A 0.3 V Nanowatt Bulk-Driven CCII− in 0.18-µm CMOS for Ultra-Low-Power Current-Mode Interfaces
by Giovanni Nicolini, Alessio Passaquieti, Giuseppe Scotti and Riccardo Della Sala
J. Low Power Electron. Appl. 2026, 16(2), 12; https://doi.org/10.3390/jlpea16020012 - 8 Apr 2026
Viewed by 386
Abstract
A 0.3 V nanowatt CCII− is presented in 0.18 μm TSMC CMOS, targeting ultra-low-power current-mode interfaces. Post-layout extracted simulations demonstrate correct conveying operation with a total DC power consumption of less than 2.40 nW. The low-frequency tracking factors evaluated at 1 [...] Read more.
A 0.3 V nanowatt CCII− is presented in 0.18 μm TSMC CMOS, targeting ultra-low-power current-mode interfaces. Post-layout extracted simulations demonstrate correct conveying operation with a total DC power consumption of less than 2.40 nW. The low-frequency tracking factors evaluated at 1 Hz are β0=0.9452 (−0.48 dB) and α0=0.9609 (≈−0.35 dB), with −3 dB bandwidths of 22.95 kHz and 63.95 kHz for the voltage and current transfers, respectively. Small-signal extraction confirms the intended impedance profile, yielding RX=46.73 MΩ, RZ=1.204 GΩ, and a very high input resistance RY=392 GΩ. Robustness is verified through full PVT and mismatch analyses, showing stable functionality across process corners, a 0–80 °C temperature range, and 270–330 mV supply variations while maintaining nanowatt-level dissipation. Full article
(This article belongs to the Special Issue Ultra-Low-Power ICs for the Internet of Things (3rd Edition))
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15 pages, 2557 KB  
Article
Post-Implementation Evaluation of CIC Filters for Digital Audio Applications on FPGA
by Elisei Ilies, Magdalena Marinca and Aurel Gontean
J. Low Power Electron. Appl. 2026, 16(1), 5; https://doi.org/10.3390/jlpea16010005 - 26 Jan 2026
Viewed by 1093
Abstract
This paper examines the implementation and resource utilization of Cascaded Integrator Comb (CIC) filters within FPGA-based Pulse Density Modulation (PDM) microphone applications. Three CIC filter designs were analyzed: one generated using MATLAB’s HDL Coder toolbox, one generated via AMD’s CIC Compiler IP, and [...] Read more.
This paper examines the implementation and resource utilization of Cascaded Integrator Comb (CIC) filters within FPGA-based Pulse Density Modulation (PDM) microphone applications. Three CIC filter designs were analyzed: one generated using MATLAB’s HDL Coder toolbox, one generated via AMD’s CIC Compiler IP, and one generated using an open-source CIC filter architecture. The study compares the efficiency of these three implementations in terms of slice LUTs and slice register usage. The maximum working frequency was also investigated. The results demonstrate that filters generated with the CIC Compiler require fewer FPGA resources, provide optimized multi-channel support, and have the option to utilize DSP48 slices for enhanced performance, while MATLAB-generated filters have higher working frequency and have great flexibility regarding the parameter, like the open-source CIC filter version. Full article
(This article belongs to the Special Issue Ultra-Low-Power ICs for the Internet of Things (3rd Edition))
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11 pages, 1151 KB  
Article
Current-Mode Quadrature Oscillator Simple Designs
by Julia Nako, Costas Psychalinos and Shahram Minaei
J. Low Power Electron. Appl. 2025, 15(1), 13; https://doi.org/10.3390/jlpea15010013 - 7 Mar 2025
Viewed by 1560
Abstract
Simple designs of current-mode quadrature oscillators are presented in this work. The main achievement, with regards to the literature, is the minimization of the required transistor count accomplished by the utilization of a suitable lossless integration stage. The derived post-layout simulation results confirm [...] Read more.
Simple designs of current-mode quadrature oscillators are presented in this work. The main achievement, with regards to the literature, is the minimization of the required transistor count accomplished by the utilization of a suitable lossless integration stage. The derived post-layout simulation results confirm the validity of the presented concept and show that the resulting structure has attractive characteristics in both frequency and time-domain. Full article
(This article belongs to the Special Issue Ultra-Low-Power ICs for the Internet of Things (3rd Edition))
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