Journal of Low Power Electronics and Applications

Single-Input, Multi-Output (SIMO) converters present significant challenges when operated under current-mode control, due to their strongly non-linear dynamics and susceptibility to bifurcation phenomena. To mitigate the effects on the converter’s steady-state, a double slope compensation solution is proposed. The compensation parameters play a critical role in shaping the system dynamics and rejecting the susceptibility to bifurcation. This paper proposes a detailed analysis methodology to investigate the design parameter space regarding the slope compensations with respect to bifurcation phenomena. The approach is validated on a CMOS integrated converter, where theoretical predictions are compared to the simulation results of a full transistor-level model of the circuit.

As technologies like Artificial Intelligence, Blockchain, Virtual Reality, etc., are advancing, there is a high requirement for High-Performance Computers and multi-core processors to find many applications in today’s Cyber–Physical World. Subsequently, multi-core systems have now become ubiquitous. The core temperature is affected by intensive computational tasks, parallel execution of tasks, thermal coupling effects, and limitations on cooling methods. High temperatures may further decrease the performance of the chip and the overall system. In this paper, we have studied different parameters related to core performance. The MSI Afterburner utility is used to extract the hardware parameters. Single and multivariate analyses are carried out on core temperature, core usage, and core clock to study the performance of all cores. Single-variate analysis shows the need for action when core temperatures, core usage, and clock speeds exceed threshold values. Multivariate analysis reveals correlations between these parameters, guiding optimization strategies. We have also implemented the ARIMA model for core temperature estimation and obtained an average RMSE of 2.44 °C. Our analysis and ARIMA model for temperature estimation are useful in developing smart scheduling algorithms that optimize thermal management and energy efficiency.

Low noise and low power neural recording amplifiers are required for implantable devices measuring action potentials. This paper presents a dynamic current pulsing technique combined with a special type of two-stage low-pass filter (LPF) that demonstrates an improvement in the noise efficiency factor (NEF) beyond that achievable using traditional design. A low NEF of 1.55 is achieved at an average power consumption of 587.8 nW and 5.18 µVrms noise, integrated from 0.1 to 9.8 kHz, inclusive of the impacts of sampling and aliasing. The NEF is improved from 1.76 in the static low current state (LCS) and 1.67 in the static high current state (HCS), measured on the same amplifier chip.