Journal of Low Power Electronics and Applications

Large language models (LLMs) commonly employ key–value (KV) caching to avoid recomputing previous attention states during autoregressive inference. However, its measured performance benefit depends on workload characteristics and the memory environment. This study presents a controlled systems characterization across input context length, model-specific grouped-query attention configurations, and GPU-memory residency. Experiments use Qwen2.5-3B and SmolLM3-3B under verified fully resident conditions with fixed 128-token generation, prompt lengths from 128 to 2048 tokens, randomized cache-enabled/cache-disabled execution, GPU telemetry, and repeated paired validation. End-to-end generation speedup increases from 1.34× to 8.31× for Qwen2.5-3B and from 1.28× to 8.62× for SmolLM3-3B. At 2048 prompt tokens, 30 randomized paired trials confirm mean speedups of 8.10× and 8.51×, corresponding to runtime reductions of 87.65% and 88.25%, while physical GPU-memory utilization remains below 61%. SmolLM3-3B requires twice the theoretical KV-cache storage per token, yet both models show comparable context-dependent scaling in the fully resident regime. Because the models differ in characteristics beyond KV-head count, this cross-model comparison is descriptive and does not attribute the observed performance difference causally to GQA configuration. A separate Mistral-7B case study shows that apparent end-to-end speedup changes substantially under memory pressure; the underlying memory-system mechanism is not isolated. These results establish cache-related end-to-end generation speedup as workload- and system-dependent and demonstrate that meaningful benchmarking requires reporting context length, cache configuration, model and cache footprints, physical accelerator-memory residency, runtime, throughput, and relevant GPU-memory conditions during each inference experiment.

Processing-in-memory (PIM) architectures have emerged as promising alternatives to conventional von Neumann architectures for accelerating memory-bound applications, such as Graph Neural Networks (GNNs), by reducing data movement between memory and processing units, thereby improving energy efficiency and reducing computational latency. Feature aggregation is a fundamental operation in GNNs; however, the sparsity of graph data leads to poor spatial and temporal locality. This results in dynamic and irregular memory access patterns, ultimately limiting performance and increasing latency. To address this issue, we propose LUPIN, a look-up table (LUT)-based PIM architecture to accelerate GNNs. In this design, logic-based processing is replaced with precalculated results stored in LUTs to perform the required computations within the DRAM memory platform. The proposed LUPIN architecture achieves enhanced performance and markedly improved energy efficiency compared to conventional bitwise-parallel PIM designs. Moreover, it avoids the fabrication challenges associated with integrating logic circuits into memory. It leverages the extensive internal parallelism of DRAM to accelerate the execution of GNN models while maintaining high energy efficiency. Our results demonstrate that LUPIN achieves geometric-mean energy improvements of 32× and 51× on GCN and GIN, respectively, over the CPU and 15× and 19.5×, respectively, over the GPU. Moreover, LUPIN reduces latency by 35.8× and 25.7× on GCN and GIN, respectively, compared with the CPU and 29.6× and 20.5×, respectively, compared with the GPU. The proposed LUPIN architecture achieves nearly 10× higher energy efficiency and 5× speedup compared with the state-of-the-art PIM architectures.

Permanent magnet synchronous motors (PMSMs) are widely used in electric vehicle (EV) traction, where speed control must be accurate, robust, and executable in real time on resource-limited embedded hardware. This paper presents an adaptive nonsingular terminal sliding-mode controller combined with a radial basis function neural network (NTSMC–RBFNN), in which the network estimates and compensates the lumped disturbance online. Stability is analyzed in continuous time under stated assumptions and, for the sampled-data implementation, only in a conditional, practical sense. The controller is reformulated in fixed-point arithmetic and deployed on a Xilinx Zynq-7000 FPGA through a parallel, pipelined architecture. In FPGA-in-the-loop (FIL) tests, it achieves a speed-tracking RMSE of 0.072 rad/s and recovers from a step load change within 4 ms, and it remains stable under ±50% variations in rotor inertia and flux linkage. One control update takes 3.2 µs (0.32% of the 1 ms sampling period), uses less than 6% of the device resources, and consumes an estimated 1.02 µJ of dynamic energy (Vivado post-implementation estimate). In an ablation study, removing the RBFNN estimate multiplies the load-step RMSE by 3.7, and replacing the nonsingular terminal surface by a conventional one increases the tracking RMSE by 75%. A sensitivity study identifies $N_h$ = 7 hidden neurons as the retained compromise between accuracy, resources, and energy. The plant is simulated and the power figures are estimates; experimental validation on a physical drive is left for future work.