Journal of Low Power Electronics and Applications doi: 10.3390/jlpea16030031

Authors: Kai-Ting Huang You-Wen Fan Jung-Yi Lin Chien-Lung Chen Yen-Chih Yeh Yu-Chen Ou Li-Chen Lin Yu-Hsien Lin Guang-Li Luo Yung-Chun Wu Fu-Ju Hou

In this work, a plasma-free atomic layer deposition (ALD)-based H2O post-treatment method is proposed to precisely modulate hydrogen-related (H-related) traps in indium gallium zinc oxide (IGZO) thin-film transistors (TFTs) by the number of H2O treatment cycles. Under the optimized condition, the scaled device with a channel length of 70 nm exhibits a near-ideal subthreshold swing of 62.9 mV/dec, a low threshold voltage (VTH) of 0.18 V, an acceptable static leakage current, and a high drive current of 3.29 μA/μm at an overdrive voltage and drain voltage of 1 V. In addition, the treated device shows only a 13 mV of VTH shift after 1000 s positive bias stress (PBS), corresponding to a 94% improvement compared with the pristine device. These improvements are attributed to the introduction of two different polarities of hydrogen-related traps after H2O treatment. Furthermore, the influence of H-related traps on bias stability and the mechanisms responsible for VTH shift are systematically clarified. These results establish that an optimized hydrogen incorporation window that maximizes the beneficial effects while balancing severe hydrogen-induced degradation caused by excessive hydrogen incorporation. Consequently, scaled IGZO TFTs with fast switching, low-power operation, high performance, and high reliability can be achieved, providing strong potential for back-end-of-line (BEOL)-compatible electronics and monolithic three-dimensional integrated applications.

Journal of Low Power Electronics and Applications doi: 10.3390/jlpea16030030

Authors: Joel Artemio Morales-Viscaya Martin Moreno Alberto Traslosheros-Michel H. J. Vergara-Hernández

This paper proposes a sensorless current estimation method for piezoelectric energy harvesting (PEH) systems using a first-order Takagi–Sugeno fuzzy system. Unlike invasive current sensing, the proposed estimator uses only non-invasive measurements: output voltage VO, its derivative V˙O, and load resistance RL. The fuzzy rules are initialized directly from the physical equivalent circuit parameters and trained via the ANFIS on a large-scale dataset (78 million samples). The proposed model achieves a mean coefficient of determination R2=0.9999 (95% CI: [0.99989, 0.99991]), root mean square error RMSE=3.12×10−8 A, mean absolute percentage error MAPE = 2.51% (95% CI: [1.98, 3.04]%), and fitness FIT = 98.98%—outperforming multiple linear regression (R2=0.9738 and MAPE = 116.25%) and a shallow neural network with 211 parameters (R2=0.9991 and MAPE = 13.85%) despite having only 170 trainable parameters. Unlike black-box neural networks, the fuzzy model provides interpretable rules whose consequent parameters map directly to physical quantities (effective capacitance Cp(eff) and leakage conductance 1/Rp(eff)). The low computational footprint (170 parameters, <5 μs inference, and ≈1.4 kB of memory) makes it suitable for real-time deployment on low-power microcontrollers. These results demonstrate the viability of the proposed approach under controlled laboratory conditions for the single, series, and parallel PEH configurations considered. This work establishes that physically informed fuzzy modeling is a viable, interpretable, and efficient alternative to deep learning for sensorless monitoring in low-power energy harvesting systems.

Journal of Low Power Electronics and Applications doi: 10.3390/jlpea16030029

Authors: Erick Iván Barros de la Cruz Juan David Salazar Cardona Maria Teresa Sanz-Pascual Nicolás Medrano Belén Calvo

This paper presents a low-power fully integrated sine signal generator for on-chip bioimpedance spectroscopy applications. The circuit is based on a relaxation oscillator, which generates a triangular signal, followed by a sixth-order Gm-C bandpass filter (BPF) that linearizes the waveform. Both blocks, designed in a 0.18 μm CMOS process with 1.8 V supply, make use of a current division technique to generate low-frequency signals without requiring high-valued passive components. The relaxation oscillator features an extended frequency tuning range from 300 Hz to 300 kHz, controlled via a tuning current and a digital capacitor bank. The sine output waveform spans from 1 kHz to 50 kHz, and exhibits a −48.8 dB total harmonic distortion at 10 kHz with 18 mV amplitude. The overall system area is 0.7 mm2 and the power consumption is lower than 30 μW.

Journal of Low Power Electronics and Applications doi: 10.3390/jlpea16030028

Authors: Alishba Masood Muhammad Khurram

Recent advances in biologically inspired neural computation have sparked increasing interest in developing hardware-efficient architectures capable of emulating brain-like cognitive abilities like low power consumption and less inference latency. However, significant hardware overhead and spike-processing complexity remain major challenges in FPGA implementations of spiking neural networks. In this work, we propose a sparse spike-aware and weight pruning FPGA architecture based on LIF neurons that minimizes spike activity and synaptic operations through pruning-aware event-driven computation. The proposed sparse spike-aware SNN architecture was evaluated using the Iris dataset. The dataset was divided into 80% training and 20% testing samples. Pre-trained weights obtained from software-level training were deployed onto the FPGA-based LIF classifier. Classification accuracy was computed by comparing predicted output spikes against ground-truth class labels. Experimental results demonstrated that the proposed architecture achieved an overall classification accuracy of 93.3% while maintaining low hardware resource utilization and reduced power consumption. Moreover, the implementation achieves superior energy efficiency, consuming only 3.5 W total on-chip power and utilizing 587 logic cells, confirming its suitability for compact, real-time edge computing neuromorphic applications.

Journal of Low Power Electronics and Applications doi: 10.3390/jlpea16030027

Authors: Xu Wang Guanyu Fu Zhiwei Xu Yuelong Zhang Junchao Zhang Yinlong Zhu Ying Liu

Achieving precise microstructure control in composite dielectric layers remains a key challenge for enhancing the sensitivity and reducing the power consumption of flexible capacitive sensors. In this work, an ultrasonic needle-induced acoustic streaming strategy is proposed to regulate the spatial distribution of Fe particles within a silicone matrix, enabling controllable particle migration and aggregation in liquid silicone. Multiphysics simulations reveal that, at an excitation frequency of 75.49 kHz, Fe particles are effectively driven toward the ultrasonic focal region, forming a tunable microstructure. Experimental results confirm that this method enables precise morphological control of the composite dielectric layer. The composite with 25 wt% Fe exhibits the highest measured relative permittivity of about 3.45, enabling a capacitive sensor sensitivity of 0.423 kPa−1 in the 0–1 kPa range. After acoustic-streaming optimization and integration into a four-unit capacitive array, the device achieved 0.509 kPa−1 sensitivity, retained 92.04% of its response after 5000 cycles at 3 kPa, and maintained 97.8% of its initial capacitance after 24 h. The proposed approach provides an effective route to improving sensor performance through microstructure engineering while maintaining low electrical loss. This work not only advances the design of high-performance functional composites but also expands the application of acoustic streaming techniques in low-power flexible electronics.

Journal of Low Power Electronics and Applications doi: 10.3390/jlpea16030026

Authors: Mrittika Chowdhury Ziyi Niu Shuai Song Anurag Dhungel Md Sakib Hasan

In this work, we present a systematic framework to optimize robust 1-D chaotic maps, focusing on expanding the uninterrupted chaotic region and enhancing chaotic properties throughout the entire parameter space. To achieve these objectives, we propose three distinct techniques, each involving systematic manipulations of chaotic seed maps. These manipulations include shifts and operations such as multiplication and division, which result in significant improvements in their chaotic characteristics. The effectiveness of the proposed methods is demonstrated through a comprehensive analysis using bifurcation plots, the maximum Lyapunov exponent, the correlation coefficient, Shannon entropy, the average Lyapunov exponent, and the chaotic ratio. The results illustrate the attainment of an extensive and uninterrupted chaotic range, alongside enhanced chaotic behavior due to the application of shifted maps. Additionally, in this work we also investigate the impact of combining general shifted maps with halfway-shifted maps, showing that their product leads to further improvements in chaotic properties and their division widens the chaotic ratio. In the last proposed method, the combined product division (CPD) maps achieve the highest overall performance, attaining a maximum Lyapunov exponent of 1.3567 and an average Lyapunov exponent of 1.3498, while maintaining a perfect chaotic ratio (CR = 1) across the entire parameter space. To demonstrate hardware feasibility, some of the proposed maps were also implemented on an FPGA, and the results were compared with MATLAB R2022b simulations. The close match between the two validates the practicality of implementing these chaotic systems in hardware. The proposed techniques have potential applications in areas such as random number generation, chaos-based cryptography, and secure communication, among others. To prove this, the optimized maps are leveraged to design a chaos-based pseudo-random number generator (PRNG) that passes statistical tests including NIST SP 800-22 (all 15 sub-tests passed) and TestU01 (38/38 Rabbit, 17/17 Alphabit, 102/102 BlockAlphabit), validating cryptographic-grade randomness.

Journal of Low Power Electronics and Applications doi: 10.3390/jlpea16030025

Authors: Kaijun Song Hanzhou Luo Yuting Yuan Yong Fan

This paper presents a compact, ultra-wideband (UWB) antenna designed for low-power wireless systems requiring upper WLAN (5.725–5.825 GHz) interference mitigation. The antenna integrates a tapered-slot radiator for broadband impedance matching with a dual C-shaped slot resonator on the ground plane to achieve targeted signal rejection. By leveraging the resonant properties of the slots, interference from the WLAN band is suppressed without requiring any active components, ensuring zero additional power consumption for the filtering function. The fabricated prototype, with a compact size of 31 × 40 mm2, demonstrates an operational bandwidth from 2.68 to 16 GHz (S11 < −10 dB) with a stable peak realized gain of 2–10 dB and a radiation efficiency above 80% across the passband. At the notch center frequency of 5.72 GHz, the gain decreases by 6.4 dB and the radiation efficiency falls to 0.6, there is effective signal rejection in the target notch band, and there are stable, omnidirectional H-plane radiation patterns. The reflection coefficient at the notch frequency rises to approximately −2.2 dB, effectively suppressing radiation in the WLAN band while maintaining stable gain and omnidirectional patterns in the remaining UWB spectrum. The proposed design offers a simple, low-cost, and energy-efficient solution for achieving spectral coexistence in power-constrained UWB applications.

Journal of Low Power Electronics and Applications doi: 10.3390/jlpea16030024

Authors: Tymoteusz Miller Irmina Durlik

The proliferation of Internet of Things (IoT) devices operating at the network edge has created unprecedented demand for distributed machine learning capable of functioning under severe resource constraints. Federated learning (FL) has emerged as a promising paradigm for privacy-preserving collaborative model training across distributed nodes; however, its application to energy-constrained edge environments remains insufficiently characterized at the system level, particularly with respect to reproducible evaluation of resource consumption and communication efficiency. In this paper, we present EcoFL (Energy-Conscious Federated Learning), a modular, energy-aware benchmarking and orchestration framework for systematic evaluation of lightweight machine learning models under emulated edge hardware constraints. Rather than proposing a new federated optimization algorithm, EcoFL extends a standard FedAvg-based training pipeline with three principal components: (i) an energy-aware communication scheduler that dynamically adapts aggregation rounds and client participation based on per-node resource availability; (ii) a comprehensive system-level profiling pipeline capturing CPU utilization, RAM consumption, inference latency, communication overhead, and estimated computational energy consumption per training round; and (iii) a reproducible benchmarking methodology enabling fair comparison of centralized, standard federated (FedAvg), and energy-aware federated configurations. We evaluate five lightweight model families—Logistic Regression, Random Forest, XGBoost, Multilayer Perceptron, and Isolation Forest—under emulated Raspberry Pi 4 hardware constraints using an anomaly detection task on synthetic IoT sensor telemetry (50,000 samples, 12 features, Dirichlet non-IID partitioning). Experimental results across five independent seeds show that, within the evaluated benchmark setting, EcoFL reduces estimated federated training energy by 79.9–92.9% (mean 84.4%) relative to standard FedAvg through adaptive round termination (4–7 rounds versus 20 fixed rounds), while showing no statistically significant F1-score degradation for four of the five evaluated model families under the tested seed regime. Notably, EcoFL achieves a higher F1-score than FedAvg for Random Forest (+0.052), which we attribute to reduced overfitting resulting from earlier convergence under non-IID data distributions. The full EcoFL framework is released as open-source software to promote reproducibility in energy-aware federated learning research and to facilitate systematic investigation of the trade-offs between predictive performance, resource utilization, and communication overhead in resource-constrained edge environments.

Journal of Low Power Electronics and Applications doi: 10.3390/jlpea16030023

Authors: Tao Zhang Yao Zhang Yufeng Zhang Zhonghua Yao Yunhong Shao

This paper proposes a practical heuristic engineering strategy for automated capacity allocation in a multifunctional parallel active power filter (PAPF) that simultaneously provides harmonic and reactive power compensation. Unlike theoretically optimal methods, our approach prioritizes real-time feasibility and ease of implementation. The key features are: (1) an event-triggered, closed-loop THD-feedback mechanism that dynamically recalculates the minimum active power required for harmonic compensation only when the load harmonic content changes, avoiding periodic computational waste; (2) a strict priority handling that guarantees grid current THD below 5% (IEEE-519 compliant) under all operating conditions, even when capacity is severely insufficient; (3) a closed-loop transition mechanism that uses measured grid current THD and remaining capacity as feedback inputs to continuously adapt power distribution. The proposed rule-based strategy does not claim theoretical optimality but provides a verifiable, ready-to-implement solution with experimental evidence. Simulation and experimental results on a three-level NPC PAPF prototype demonstrate that the strategy maintains grid current THD below 5% while keeping the apparent power within the rated capacity, achieving near-optimal reactive compensation (92–96% of the optimum) without iterative optimization. The experimental validation includes efficiency measurements, switching-loss estimation, DSP timing analysis, and robustness tests under grid disturbances. Future work will extend the concept to multi-inverter systems using multi-objective optimization and AI-based allocation.

Journal of Low Power Electronics and Applications doi: 10.3390/jlpea16030022

Authors: David Ng King Hang Lam Si Qi Bu Wen Chin Lo Chi Hong Chan Roy Ng Sunny Chan Matt Mak Hugo Wong Steve Chim Patrick Chang Raymond Chik Steven Wong Wai Ming To

Analog in-memory computing (AIMC) has emerged as a promising approach to mitigate the Von Neumann bottleneck in matrix operations, which are common in deep learning applications. However, the practical implementation of resistive crossbar arrays is limited by challenges in signed weight representation, conductance quantization, and device nonlinearity. This paper presents a differential mixed-signal architecture for accurate signed matrix–vector multiplication (MVM), integrated with a RISC-V microcontroller for edge inference applications. A structured digital-to-analog mapping framework encodes quantized neural network weights into programmable conductance values while preserving arithmetic correctness. The design employs voltage-mode input encoding, differential current summation, and transimpedance-based readout followed by analog-to-digital conversion, enabling single-cycle signed accumulation without duplicating crossbar resources. A 32 × 16 dual-layer prototype crossbar was fabricated and experimentally characterized. Measurements demonstrate a mean absolute percentage error (MAPE) below 1% within the linear operating region and below 4% over the full-scale conductance range. These results validate the robustness of the proposed mapping methodology and confirm the feasibility of hybrid analog–digital acceleration for edge AI systems. Consequently, this discrete prototype serves as a physical verification platform for the AIMC approach, providing valuable insights for more efficient mixed-signal computing integrated circuit (IC) designs.

Journal of Low Power Electronics and Applications doi: 10.3390/jlpea16020021

Authors: Abrar Abdurrob Aristotelis Tsekouras Evangelos Tzouvaras Vasilis F. Pavlidis Emre Salman

The rapid growth of Deep Neural Networks (DNNs) has led to the development of application-specific DNN accelerators. Conventional 2D von Neumann architectures suffer from memory bandwidth limitations between the memory and the processing core. 3D DNN accelerators have emerged as a promising solution by leveraging 3D integration to enable near-memory logic or in-memory computation. By shifting computation closer to memory, these accelerators significantly reduce data movement and therefore latency, resulting in more energy-efficient operations. Monolithic 3D (M3D) integration, in particular, enables high-bandwidth systems by utilizing high-density monolithic inter-tier vias (MIVs). This paper provides a critical review of recent advances in 3D DNN accelerators that combine near-memory and compute-in-memory with various 3D technologies, offering a useful discussion and future prospects of the available technologies and architectures that have advanced the performance of DNN accelerators. Particular attention is devoted to accelerators for emerging transformer-based large language model (LLM) networks due to the higher memory demands. Thermal-aware design techniques of 3D DNN accelerators are also discussed as a means to address the fundamental challenge of heat dissipation. A detailed review is finally conducted on package-level constraints, considering signal integrity, power delivery, and thermo-mechanical reliability.

Journal of Low Power Electronics and Applications doi: 10.3390/jlpea16020020

Authors: Jegan Rajendran Nimi Wilson Sukumari Manikandan Rajendran

The increasing demand of digital technologies and their integration with wearable health devices provides an efficient trigger for next-generation wearable healthcare devices for long-term physiological monitoring. The advancement of energy harvesting mechanism, nanomaterial-based sensor fabrication and their integration with digital technologies have emerged as a promising solution for transforming future of digital health. This study provides a comprehensive summary and framework for wearable self-powered electronic devices, enabling continuous, battery-free health monitoring and advancing the development of sustainable, next-generation digital healthcare systems. This review paper presents a broad and detailed overview of current technologies and sensors advancement in developing low-power wearable, self-powered electronic devices suitable for healthcare applications. The importance and reliable use of key energy harvesting approaches including triboelectric, piezoelectric, thermoelectric, and photovoltaic approaches are systematically presented which focused on development of energy efficient wearable devices. This review further examines the low-power circuit design strategies for flexible electronics focusing personalized healthcare monitoring. Current challenges and limitations related to advanced manufacturing of wearable health devices focusing on large-scale deployment are also analyzed. Finally, the key future research directions are outlined for advancing a next-generation intelligent digital health system.

Journal of Low Power Electronics and Applications doi: 10.3390/jlpea16020019

Authors: Yen-Ying Peng Syu-Bin Li Sen Wang Chatrpol Pakasiri

This paper presents the design and implementation of an X-band voltage-controlled oscillator (VCO) fabricated in a standard 180-nm CMOS process. To sustain stable oscillation under a constrained power budget, a gm-boosted topology is employed, integrating vertically stacked cross-coupled transistors with a center-tapped transformer to enhance the equivalent negative conductance. The boosting is achieved through two complementary mechanisms: the center-tapped transformer performs an impedance transformation that repurposes the layout parasitic capacitances into transconductance-enhancing elements, while the stacked cross-coupled pair reuses the DC current and suppresses the source-degeneration of a conventional pair, jointly sustaining a robust start-up margin at a low 0.75 V supply. On-wafer measurement results demonstrate a frequency tuning range from 8.78 GHz to 9.13 GHz as the control voltage is swept from 0 V to 1.8 V, with an average VCO gain KVCO of 447.5 MHz/V. Under a total DC power consumption of 6.9 mW, the oscillator delivers an output power of 4.54 dBm and exhibits a measured phase noise of −103 dBc/Hz at a 1-MHz offset.

Journal of Low Power Electronics and Applications doi: 10.3390/jlpea16020018

Authors: Larisa Goffman-Vinopal

AI accelerators increasingly operate under tight power, thermal, voltage, and timing margins, making workload-dependent thermal nonuniformity an important reliability concern. In systolic AI accelerators, localized activity concentration can create spatially uneven thermal stress, but thermal or timing-exposure analysis alone does not determine whether such stress remains benign, becomes numerically masked, or propagates into silent corruption. This paper presents a cross-layer early-stage screening methodology for thermal nonuniformity-aware reliability analysis in systolic arrays. The framework links workload-aware activity extraction, relative power concentration modeling, diffusion-based thermal proxy analysis, an explicit thermal-to-timing stress abstraction, path class-aware corruption modeling, and clean/masked/silent outcome classification. The revised framework is formalized mathematically and evaluated across dense, low-dynamic-range, and sparse GEMM workloads under weight-stationary and output-stationary execution. To strengthen statistical and methodological confidence, the study includes 100-seed corruption reruns with Wilson confidence intervals, thermal scaling across 8×8, 16×16, and 32×32 arrays, calibration sensitivity, path weight sensitivity, component ablations, and preliminary compact thermal reference alignment. The results show that sparse workloads consistently produce the largest thermal spread across tested array sizes, while dense and low-dynamic-range workloads remain more spatially uniform. Under the default calibrated screening regime at 16×16, sparse output-stationary and sparse weight-stationary cases reach 49% and 40% silent corruption rates, respectively, while dense cases remain mostly clean or masked and low-dynamic-range cases remain largely clean. Sensitivity and ablation experiments show that the sparse workload risk is not caused by one isolated modeling component, although the masked/silent split depends on path class weighting and thermal diffusion assumptions. The main contribution is not signoff-accurate silicon failure prediction, but a reproducible screening front end for identifying workload, dataflow, and path class combinations that deserve deeper thermal, timing, RTL-level, and application-level validation.

Journal of Low Power Electronics and Applications doi: 10.3390/jlpea16020017

Authors: Thi Phuong Ha The Khai Chu Van Tung Nguyen Orazio Aiello Xuan Thanh Pham

This paper introduces a novel analog-to-digital converter (ADC) employing a passive noise-shaping (NS) technique combined with a chopper-stabilized comparator, enhancing performance and reducing ripple factor while maintaining low power consumption. The NS architecture is built on a cascade-integrator feedforward (CIFF) structure, using both infinite- and finite-impulse response filters to minimize quantization and kT/C noise. Additionally, it employs a low-power two-stage chopper amplifier to compensate for the offset voltage and enhance system stability. Validated according to the 180 nm CMOS process, the proposed ADC has an effective number of bits of 10.6, a signal-to-noise-and-distortion ratio of 68.4 dB, and a signal-to-noise ratio of 59.33 dB. With a compact area of 0.17 mm2 and a power consumption of 650 µW from a 1.8 V supply, the proposal is well suited to biomedical sensor applications requiring strict accuracy and low energy consumption.

Journal of Low Power Electronics and Applications doi: 10.3390/jlpea16020016

Authors: Mohammad Okour Mohannad Alkhalil Mutaz Al Fayad Juhyun Bak Kevin R. James Sulaiman Mohaidat Xiaoqi Liu Fadi Alsaleem Michael Hempel Hamid Sharif-Kashani Mahmoud Alahmad

Accurate estimation of lithium-ion battery State of Health (SoH) is critical for emerging applications such as reconfigurable battery systems. Although data-driven machine learning methods are promising, they often rely on costly, time-intensive aging experiments and extensive feature engineering. This work proposes a lightweight SoH-prediction framework validated on both physics-informed synthetic aging data and the NASA battery aging dataset. We evaluated Random Forest (RF) and Feedforward Neural Network (FNN) models that use only a limited number of samples from an early segment of the raw discharge voltage curve as input. Results show that RF consistently outperforms FNN across input sizes in deterministic or noise-free environments, achieving an RMSE of 0.07% SoH using just 5 voltage samples. In inherently stochastic experimental data, however, FNN can achieve an RMSE 50% lower than RF (1.28 vs. 2.87), but requires 37× more mathematical operations per inference. These findings emphasize the predictive value of the early-discharge-voltage region and demonstrate that compact, low-feature-complexity models can deliver accurate SoH estimates. Overall, the approach supports a goal of combining informed synthetic data with limited real measurements to build robust, scalable SoH predictors, reducing dependence on labor-intensive degradation testing and feature-heavy pipelines.

Journal of Low Power Electronics and Applications doi: 10.3390/jlpea16020015

Authors: Nicolas Medrano Diego Antolin Daniel Eneriz Belen Calvo

The measurement of the magnetic field generated by a flowing current constitutes a non-invasive sensing technique for online energy consumption monitoring. In this work, based on the use of low-cost linear Hall effect sensors, a low-form-factor custom contactless ammeter probe is presented. The differential configuration of the sensor module and the subsequent fully digital programmability in range and sensitivity, together with the included self-calibration and compensation circuits for mismatching, managed by a microcontroller, allow for optimum detection for both continuous and mains current with a resolution of 10 mA for input ranges of 2 A. The proposed ammeter power consumption and measurement accuracy in different scenarios are tested, including the power monitoring of an IoT-based device, obtaining results matched to those featured by a commercial oscilloscope current probe, which validates its suitability and reliability as autonomous low-cost probe for portable contactless power monitoring.

Journal of Low Power Electronics and Applications doi: 10.3390/jlpea16020014

Authors: Manfredi Caruso Andrea Ballo Minoo Eghtesadi Egidio Ragonese

This paper provides a comprehensive analysis of active frequency doubler architectures adopted for efficient generation of millimeter-wave (mm-wave) signals. The operational principles of each topology are explained to address a thorough comparison based on essential performance metrics such as conversion gain, power efficiency, and spectral purity. The review covers several topologies from the standard push–push (PP) doubler to its power-efficient evolution, the complementary push–push (CPP) doubler. Furthermore, this paper focuses on more recent and advanced topologies, including the complementary common gate capacitive cross-coupled (CCGCCC) doubler. Finally, this work proposes and evaluates an improved version of the CCCGCC doubler, offering insights into the state of the art and future directions in mm-wave frequency multiplication.

Journal of Low Power Electronics and Applications doi: 10.3390/jlpea16020013

Authors: Juan Cruz-Cozar Javier Mendez Miguel Molina Jorge Perez-Martinez Alberto Martin-Martin Noel Rodriguez Diego P. Morales

Distributed energy systems open up a vast field of research in power electronics. Local solar power generation requires DC-DC converters that adapt the energy generated by the panels to on-site distribution buses. In addition, the control of the power converter to obtain the maximum possible energy from the solar source is crucial for the correct deployment of these distributed grids. In this work, system-level solutions are proposed for this application as follows: On the one hand, the use of novel resonant forward-flyback converters allows for a higher energy density than that of a conventional flyback and more relaxed withstand voltages on the switching elements. On the other hand, the implementation of maximum power point tracking algorithms for solar energy using Edge AI enables the deployment of algorithms that maximize the energy obtained locally. These improvements are shown by means of a prototype demonstrator, using cutting-edge microcontrollers and the implementation of a DC-DC power converter based on the proposed topology.

Journal of Low Power Electronics and Applications doi: 10.3390/jlpea16020012

Authors: Giovanni Nicolini Alessio Passaquieti Giuseppe Scotti Riccardo Della Sala

A 0.3 V nanowatt CCII− is presented in 0.18 μm TSMC CMOS, targeting ultra-low-power current-mode interfaces. Post-layout extracted simulations demonstrate correct conveying operation with a total DC power consumption of less than 2.40 nW. The low-frequency tracking factors evaluated at 1 Hz are β0=0.9452 (−0.48 dB) and α0=0.9609 (≈−0.35 dB), with −3 dB bandwidths of 22.95 kHz and 63.95 kHz for the voltage and current transfers, respectively. Small-signal extraction confirms the intended impedance profile, yielding RX=46.73 MΩ, RZ=1.204 GΩ, and a very high input resistance RY=392 GΩ. Robustness is verified through full PVT and mismatch analyses, showing stable functionality across process corners, a 0–80 °C temperature range, and 270–330 mV supply variations while maintaining nanowatt-level dissipation.

Journal of Low Power Electronics and Applications doi: 10.3390/jlpea16020011

Authors: Qiang Wang Libo Yang Mengdi Wang Bin Ma Long Yuan Shaobo Li Zhangjie Liu

High penetration of renewable energy sources (RESs) introduces significant power fluctuations, threatening voltage and frequency stability in modern power systems. This paper presents an integrated framework for static voltage stability assessment and stability-constrained optimization of under-frequency load shedding (UFLS) in renewable-dominated grids. A low-conservativeness analytical criterion is first derived for static voltage stability margin assessment. Then, a hybrid Deep Belief Network–Long Short-Term Memory (DBN–LSTM) model is developed for accurate renewable power forecasting, capturing temporal variability and uncertainty. Finally, UFLS-based stability-constrained dispatch is formulated to prevent voltage collapse, enhance the system stability, and minimize RES curtailment. Simulations on a modified IEEE benchmark system demonstrate that the proposed approach improves voltage and frequency stability while maintaining high renewable energy utilization.

Journal of Low Power Electronics and Applications doi: 10.3390/jlpea16010010

Authors: Yu Qi Hossein Yaghobi Hossein Miri Lavasani

This paper presents a secure 2.4 GHz frequency shift keying (FSK) transmitter front-end with minimal overhead on the data stream using analog obfuscation techniques applied to the modulated waveform. An off-chip true random number generator (TRNG) unit is used to generate the required key for the encryption. Moving away from traditional FSK schemes, which benefit from constant local oscillator (LO) frequency within the channel, the proposed secure FSK scheme shifts the LO frequency in very small steps using an innovative capacitor-bank structure with a calibrated digitally controlled oscillator (DCO). The proposed capacitor bank uses a combination of parallel switches and series capacitors to minimize the impact of the layout parasitics on the minimum capacitor in the bank, thereby reliably creating sub-fF unit capacitors. When combined with the proposed capacitor bank, the cross-coupled CMOS LC voltage-controlled oscillator (VCO) forms a digitally controlled oscillator (DCO). The post-layout simulation results of the DCO reveal that the proposed scheme can achieve a resolution of <20 kHz for the LO frequency shifting while maintaining the phase-noise performance. The reported phase shift allows an equivalent entropy > 6 bits in the implemented analog-inspired secure transmitter front-end.

Journal of Low Power Electronics and Applications doi: 10.3390/jlpea16010009

Authors: Gerardo Arno Sonck-Martinez Victor A. Gonzalez-Huitron Abraham Efraím Rodríguez-Mata Isidro Robledo-Vega Guillermo Valencia-Palomo Jose-Agustin Almaraz-Damian

This research addresses the increasing need for efficient energy management in residential settings in response to the increasing global energy demands, focusing on the integration of artificial intelligence to identify energy burdens. We employ and compare some machine learning models, like Decision Trees, K-nearest neighbors, and Feedforward Neural Networks, with a primary focus on electrical current as a key parameter. The Fine K-NN model shows notable efficiency, achieving an accuracy of 99.1% in the identification of active household appliances using a single sensor. Our methodology encompasses rigorous data acquisition and preprocessing under controlled experimental conditions, ensuring the integrity and reliability of our results. This study contributes to the field by illustrating the effectiveness of specific AI models in energy management under controlled conditions, paving the way for future advancements in AI-driven energy conservation strategies.

Journal of Low Power Electronics and Applications doi: 10.3390/jlpea16010008

Authors: Yifeng Fu Jianguang Xu

In the post-Moore’s Law era, conventional Von Neumann architectures face critical limitations, such as the “memory wall” and excessive power consumption, particularly when processing unstructured data. Neuromorphic computing, inspired by the human brain, offers a promising solution through parallel processing and adaptive learning. Among the candidates for artificial synapses, memristors based on two-dimensional MXenes (specifically Ti3C2Tx) have attracted significant attention due to their unique layered structure, high metallic conductivity, and tunable physicochemical properties. This review provides a comprehensive analysis of MXene-based memristors, from material synthesis to system-level applications. We examine how different synthesis strategies, including etching methods, directly influence device performance and elucidate the underlying resistive switching mechanisms driven by ion migration, valence change, and interfacial processes. Furthermore, the review demonstrates the efficacy of MXenes in emulating biological synaptic functions—such as spike-timing-dependent plasticity (STDP) and long-term potentiation/depression (LTP/LTD)—and their application in tasks like handwritten digit recognition. Finally, we highlight emerging frontiers in flexible electronics and in-sensor computing, offering insights into the future trajectory of integrated sensing, memory, and computation.

Journal of Low Power Electronics and Applications doi: 10.3390/jlpea16010007

Authors: Paolo Esposito Vincenzo Stornelli Giuseppe Ferri

In this work, the authors introduce an entirely solar-powered LoRa-based WSN consisting of several nodes, two stoplights, and four cameras. The system has been used to monitor the semi-rural area of Panni (FG), Puglia, Italy. The WSN has a totally custom implementation in both the node-gateway side and the gateway-user interface side. In particular, the communication framework is entirely IoT-based, featuring both the MQTT protocol, for the direct control of apparatuses from the system user interface, and the more traditional TCP/IP protocol, implemented on NB-IoT. The proposed system is entirely solar-powered and features a 34.68 mWh/day consumption. Around a single communication session, the average power consumption inside the single node amounts to 1.4 mW. This paper gives an overview of the proposed system, with detailed explanations of each part, and measurements retrieved over a wide period to assess the functionality of the system.

Journal of Low Power Electronics and Applications doi: 10.3390/jlpea16010006

Authors: Andreas Tsiougkos Georgia Amanatiadou Vasilis F. Pavlidis

A new approach to end-to-end power delivery for increasingly sought-after hierarchical power delivery units (PDUs) is presented, improving the power efficiency of portable systems. The benefits of the technique are demonstrated through a PDU comprising multiple DC–DC converters, such as low-dropout regulators (LDOs), and the support of heterogeneous loads. A properly tailored Q-algorithm is combined with power gating to manage the power supplied by a multi-level PDU. The effectiveness of the proposed method is evaluated via a realistic PDU for different combinations of loads. The learning-based technique yields up to 13% higher total end-to-end power efficiency in the case of similar loads by utilizing four available LDOs compared to the case of a single LDO, which supports the same span of loads. Moreover, the proposed method improves power efficiency by up to 5% in the case of heterogeneous loads when compared to other autonomous state-of-the-art power management units.

Journal of Low Power Electronics and Applications doi: 10.3390/jlpea16010005

Authors: Elisei Ilies Magdalena Marinca Aurel Gontean

This paper examines the implementation and resource utilization of Cascaded Integrator Comb (CIC) filters within FPGA-based Pulse Density Modulation (PDM) microphone applications. Three CIC filter designs were analyzed: one generated using MATLAB’s HDL Coder toolbox, one generated via AMD’s CIC Compiler IP, and one generated using an open-source CIC filter architecture. The study compares the efficiency of these three implementations in terms of slice LUTs and slice register usage. The maximum working frequency was also investigated. The results demonstrate that filters generated with the CIC Compiler require fewer FPGA resources, provide optimized multi-channel support, and have the option to utilize DSP48 slices for enhanced performance, while MATLAB-generated filters have higher working frequency and have great flexibility regarding the parameter, like the open-source CIC filter version.

Journal of Low Power Electronics and Applications doi: 10.3390/jlpea16010004

Authors: Yeh-Liang Hsu Chun-Hung Yi Shu-Chiung Lee Kuei-Hua Yen

(1) Background: In hospitals, mattresses are often relocated for cleaning or patient transfer, leading to mismatches between actual and recorded bed locations. Manual updates are time-consuming and error-prone, requiring an automatic localization system that is cost-effective and easy to deploy to ensure traceability and reduce nursing workload. (2) Purpose: This study presents a pragmatic, large-scale implementation and validation of a BLE-based localization system using RSSI measurements. The goal was to achieve reliable room-level identification of smart mattresses by leveraging existing hospital infrastructure. (3) Results: The system showed stable signals in the complex hospital environment, with a 12.04 dBm mean gap between primary and secondary rooms, accurately detecting mattress movements and restoring location confidence. Nurses reported easier operation, reduced manual checks, and improved accuracy, though occasional mismatches occurred when receivers were offline. (4) Conclusions: The RSSI-based system demonstrates a feasible and scalable model for real-world asset tracking. Future upgrades include receiver health monitoring, watchdog restarts, and enhanced user training to improve reliability and usability. (5) Method: RSSI–distance relationships were characterized under different partition conditions to determine parameters for room differentiation. To evaluate real-world scalability, a field validation involving 266 mattresses in 101 rooms over 42 h tested performance, along with relocation tests and nurse feedback.

Journal of Low Power Electronics and Applications doi: 10.3390/jlpea16010003

Authors: Tanzeel-ur-Rehman Khan Sanghamitra Roy Koushik Chakraborty

In the pursuit of real-time object detection with constrained computational resources, the optimization of neural network architectures is paramount. We introduce novel sparsity induction methods within the YOLOv4-Tiny framework to significantly improve computational efficiency while maintaining high accuracy in pedestrian detection. We present three sparsification approaches: Homogeneous, Progressive, and Layer-Adaptive, each methodically reducing the model’s complexity without compromising its detection capability. Additionally, we refine the model’s output with a memory-efficient sliding window approach and a Bounding Box Sorting Algorithm, ensuring precise Intersection over Union (IoU) calculations. Our results demonstrate a substantial reduction in computational load by zeroing out over 50% of the weights with only a minimal 6% loss in IoU and 0.6% loss in F1-Score.

Journal of Low Power Electronics and Applications doi: 10.3390/jlpea16010002

Authors: Arnab Raha Shamik Kundu Arghadip Das Soumendu Kumar Ghosh Deepak A. Mathaikutty

Modern deep neural network (DNN) accelerators must sustain high throughput while avoiding performance degradation from supply voltage (VDD) droop, which occurs when large arrays of multiply–accumulate (MAC) units switch concurrently and induce high peak current (ICCmax) transients on the power delivery network (PDN). In this work, we focus on ASIC-class DNN accelerators with tightly synchronized MAC arrays rather than FPGA-based implementations, where such cycle-aligned switching is most pronounced. Conventional guardbanding and reactive countermeasures (e.g., throttling, clock stretching, or emergency DVFS) either waste energy or incur non-trivial throughput penalties. We propose SparseDroop, a unified hardware-conscious framework that proactively shapes instantaneous current demand to mitigate droop without reducing sustained computing rate. SparseDroop comprises two complementary techniques. (1) SparseStagger, a lightweight hardware-friendly droop scheduler that exploits the inherent unstructured sparsity already present in the weights and activations—it does not introduce any additional sparsification. SparseStagger dynamically inspects the zero patterns mapped to each processing element (PE) column and staggers MAC start times within a column so that high-activity bursts are temporally interleaved. This fine-grain reordering smooths ICC trajectories, lowers the probability and depth of transient VDD dips, and preserves cycle-level alignment at tile/row boundaries—thereby maintaining no throughput loss and negligible control overhead. (2) SparseBlock, an architecture-aware, block-wise-structured sparsity induction method that intentionally introduces additional sparsity aligned with the accelerator’s dataflow. By co-designing block layout with the dataflow, SparseBlock reduces the likelihood that all PEs in a column become simultaneously active, directly constraining ICCmax and peak dynamic power on the PDN. Together, SparseStagger’s opportunistic staggering (from existing unstructured weight zeros) and SparseBlock’s structured, layout-aware sparsity induction (added to prevent peak-power excursions) deliver a scalable, low-overhead solution that improves voltage stability, energy efficiency, and robustness, integrates cleanly with the accelerator dataflow, and preserves model accuracy with modest retraining or fine-tuning.

Journal of Low Power Electronics and Applications doi: 10.3390/jlpea16010001

Authors: Ziyang Chen Ming Hao Xinye Cao Jingwei Zhang Chaoyao Shen Guoqing Li Meng Zhang

The Transformer architecture has achieved remarkable success across numerous computer vision tasks due to its superior capability for global dependency modeling. However, the high computational complexity and hardware-unfriendly operations such as Layer Normalization (LN), Softmax, and GELU severely hinder its deployment on resource-constrained platforms. To address these challenges, this paper proposes a hardware-friendly CNN-Transformer hybrid pyramid architecture that effectively balances accuracy, efficiency, and deployability. The proposed model integrates convolutional bottlenecks with Transformer encoders to capture both local and global contextual information while maintaining low computational cost. A pyramid feature extraction structure is further introduced to enhance multi-scale semantic representation. To improve hardware efficiency, we redesign key nonlinear components by introducing hardware-friendly activation, normalization, and Softmax approximations. Specifically, GELU and LN are replaced by ReLU and Batch Normalization (BN), and a simplified logarithmic-exponential formulation termed Softmax2 is proposed, which eliminates complex exponential and division operations, significantly reducing hardware implementation cost. Extensive experiments demonstrate the effectiveness of the proposed framework. The experimental results validate that the proposed architecture offers a promising and practical solution for real-time and embedded vision applications.

Journal of Low Power Electronics and Applications doi: 10.3390/jlpea15040071

Authors: Michelle Libang Kriz Kevin Adrivan Jefferson A. Hora Charade G. Avondo Robert M. Comaling Xi Zhu Yichuang Sun

This paper presents a self-contained startup charging circuit designed for energy-harvesting batteryless IoT devices. The proposed circuit consists of a current-biasing block, a current mirror, a reference voltage generator, and a comparator circuit. The current-biasing circuit drives the current mirror, which supplies the charging current to the energy storage element. Simultaneously, the reference voltage generator—also biased by the current source—produces a stable DC reference voltage. When the energy storage device (e.g., a supercapacitor) lacks sufficient charge, the comparator enables the charging path by activating the current-biasing and mirror circuits. Once adequate energy is stored, the comparator disables these circuits to prevent overcharging. This self-contained solution is intended to autonomously initialize and manage the cold-start charging process in energy-harvesting systems without relying on external controllers. This paper highlights the circuit architecture and validated performance, demonstrating a charging current of up to 27 mA, a reference voltage of 700 mV, and an operating range from 0.9 V to 1.8 V across a temperature range of −40 °C to 85 °C.

Journal of Low Power Electronics and Applications doi: 10.3390/jlpea15040070

Authors: Sreehari K. Narayanan Ramesh Bhakthavatchalu Remya Ajai Ajayan Sarala

Physically unclonable functions (PUFs) generate keys for cryptographic applications, eliminating the need for conventional key storage mechanisms. Since PUF responses are inherently noise-sensitive, their reliability can decrease under varying conditions. Integrating channel coding can enhance response stability and consistency. This work presents an efficient scheme that integrates a delay-base d PUF with a Low-Density Parity-Check (LDPC) code. Specifically, a feed-forward PUF is combined with LDPC coding to reliably regenerate the cryptographic key. Our design reproduces the key with minimal error using channel coding. The scheme achieves 96% key-generation reliability, representing a notable improvement over PUF-based key generation without error-correction coding. LDPC decoding with the min-sum algorithm provides better error correction than the bit-flipping algorithm, but it is more computationally intensive. We could design the proposed scheme with minimum hardware resource utilization using Xilinx Vivado 2018.2 and Cadence Genus tools.

Journal of Low Power Electronics and Applications doi: 10.3390/jlpea15040069

Authors: Mathieu Ginet Eric Feltrin Nicolas Jeanniot Bruno Allard Xuefang Lin-Shi

Single-Input, Multi-Output (SIMO) converters present significant challenges when operated under current-mode control, due to their strongly non-linear dynamics and susceptibility to bifurcation phenomena. To mitigate the effects on the converter’s steady-state, a double slope compensation solution is proposed. The compensation parameters play a critical role in shaping the system dynamics and rejecting the susceptibility to bifurcation. This paper proposes a detailed analysis methodology to investigate the design parameter space regarding the slope compensations with respect to bifurcation phenomena. The approach is validated on a CMOS integrated converter, where theoretical predictions are compared to the simulation results of a full transistor-level model of the circuit.

Journal of Low Power Electronics and Applications doi: 10.3390/jlpea15040068

Authors: Leena Ladge Y. Srinivasa Rao

As technologies like Artificial Intelligence, Blockchain, Virtual Reality, etc., are advancing, there is a high requirement for High-Performance Computers and multi-core processors to find many applications in today’s Cyber–Physical World. Subsequently, multi-core systems have now become ubiquitous. The core temperature is affected by intensive computational tasks, parallel execution of tasks, thermal coupling effects, and limitations on cooling methods. High temperatures may further decrease the performance of the chip and the overall system. In this paper, we have studied different parameters related to core performance. The MSI Afterburner utility is used to extract the hardware parameters. Single and multivariate analyses are carried out on core temperature, core usage, and core clock to study the performance of all cores. Single-variate analysis shows the need for action when core temperatures, core usage, and clock speeds exceed threshold values. Multivariate analysis reveals correlations between these parameters, guiding optimization strategies. We have also implemented the ARIMA model for core temperature estimation and obtained an average RMSE of 2.44 °C. Our analysis and ARIMA model for temperature estimation are useful in developing smart scheduling algorithms that optimize thermal management and energy efficiency.

Journal of Low Power Electronics and Applications doi: 10.3390/jlpea15040067

Authors: Yujia Huo Roy H. Olsson

Low noise and low power neural recording amplifiers are required for implantable devices measuring action potentials. This paper presents a dynamic current pulsing technique combined with a special type of two-stage low-pass filter (LPF) that demonstrates an improvement in the noise efficiency factor (NEF) beyond that achievable using traditional design. A low NEF of 1.55 is achieved at an average power consumption of 587.8 nW and 5.18 µVrms noise, integrated from 0.1 to 9.8 kHz, inclusive of the impacts of sampling and aliasing. The NEF is improved from 1.76 in the static low current state (LCS) and 1.67 in the static high current state (HCS), measured on the same amplifier chip.

Journal of Low Power Electronics and Applications doi: 10.3390/jlpea15040066

Authors: Jing Zhou Xiangyu Zhao Shengbing Zhang Lei Chen Ke Xiao Shuo Wang

SRAM-based FPGAs, with their flexible programmability and parallel execution features, have been widely used, and the security of such devices has drawn significant attention. Especially in the era of artificial intelligence, FPGA architectural optimizations and evolving application models have introduced novel security characteristics and threats. In this work, we introduce a taxonomy of FPGA threats and explore new threat features and potential countermeasures in the era of AI. We focus on evaluating the research trends of FPGA security, including both security threats and protection measures. Then, we propose a new perspective on the involvement of FPGA manufacturers in FPGA security and introduce the main security measures used in COTS FPGA products. Finally, we summarize the security challenges and offer future research directions.

Journal of Low Power Electronics and Applications doi: 10.3390/jlpea15040065

Authors: Mehdi Shahabi Noemi Perez Hector Solar Andoni Beriain

This work presents an ultra-low-power on-chip energy management (EM) circuit, which is the most critical and power-intensive block in power management integrated circuits (PMICs) used for energy harvesting (EH) applications. Ultra-low power consumption was the primary design priority to ensure suitability for systems operating under strict energy limitations. The design relies on a compact latch-based core and avoids the need for extra circuits such as voltage references, comparators, or logic blocks, which helps reduce both area and power. To implement the required high resistance, a series of diode-connected zero-threshold NMOS transistors is used. This approach enables very high resistance in a compact area without additional power consumption or biasing issues at low voltages. A PMOS transistor is also integrated at the EM output to directly control different types of loads. The circuit was designed and fabricated using a 65 nm CMOS standard process. Experimental measurements from the fabricated chips show a quiescent current of 170 nA at 3 V and a voltage hysteresis of over 0.9 V. In addition, temperature and process variation were simulated to verify robust operation. These results confirm that the circuit operates reliably under ultra-low-power conditions and is well-suited for EH systems.

Journal of Low Power Electronics and Applications doi: 10.3390/jlpea15040064

Authors: Devendra G. Sutar Nitesh B. Guinde

Accurate branch prediction is crucial for achieving high instruction throughput and minimizing control hazards in modern pipelines. This paper presents a novel LXOR (Local eXclusive-OR) branch predictor, which enhances prediction accuracy while reducing hardware complexity and memory usage. Unlike traditional predictors (GAg, GAp, PAg, PAp, Gshare, Gselect) that rely on large Pattern History Tables (PHTs) or intricate global/local history combinations, the LXOR predictor employs complemented local history and XOR-based indexing, optimizing table access and reducing aliasing. Implemented and evaluated using the MARSS-RISCV simulator on a 64-bit in-order RISC-V core, the LXOR’s performance was compared against traditional predictors using Coremark and SPEC CPU2017 benchmarks. The LXOR consistently achieved competitive results, with a prediction accuracy of up to 83.92%, lower misprediction rates, and instruction flushes as low as 5.83%. It also attained an IPC rate of up to 0.83, all while maintaining a compact memory footprint of approximately 2 KB, significantly smaller than current alternatives. These findings demonstrate that the LXOR predictor not only matches the performance of more complex predictors but does so with less memory and logic overhead, making it ideal for embedded systems, low-power RISC-V processors, and resource-constrained IoT and edge devices. By balancing prediction accuracy with simplicity, the LXOR offers a scalable and cost-effective solution for next-generation microprocessors.

Journal of Low Power Electronics and Applications doi: 10.3390/jlpea15040063

Authors: John Reuben Felix Zeller Benjamin Seiler Dietmar Fey

Image convolution is a commonly required task in machine vision and Convolution Neural Networks (CNNs). Due to the large data movement required, image convolution can benefit greatly from in-memory computing. However, image convolution is very computationally intensive, requiring (n−(k−1))2 Inner Product (IP) computations for convolution of a n×n image with a k×k kernel. For example, for a convolution of a 224 × 224 image with a 3 × 3 kernel, 49,284 IPs need to be computed, where each IP requires nine multiplications and eight additions. This is a major hurdle for in-memory implementation because in-memory adders and multipliers are extremely slow compared to CMOS multipliers. In this work, we revive an old technique called ‘Distributed Arithmetic’ and judiciously apply it to perform image convolution in memory without area-intensive hard-wired multipliers. Distributed arithmetic performs multiplication using shift-and-add operations, and they are implemented using CMOS circuits in the periphery of ReRAM memory. Compared to Google’s TPU, our in-memory architecture requires 56× less energy while incurring 24× more latency for convolution of a 224 × 224 image with a 3 × 3 filter.

Journal of Low Power Electronics and Applications doi: 10.3390/jlpea15040062

Authors: Shivakumar Rajagopal Viet-Thanh Pham Fatemeh Parastesh Karthikeyan Rajagopal Sajad Jafari

Neuromorphic circuits emulate the brain’s massively parallel, energy-efficient, and robust information processing by reproducing the behavior of neurons and synapses in dense networks. Memristive technologies have emerged as key enablers of such systems, offering compact and low-power implementations. In particular, locally active memristors (LAMs), with their ability to amplify small perturbations within a locally active domain to generate action potential-like responses, provide powerful building blocks for neuromorphic circuits and offer new perspectives on the mechanisms underlying neuronal firing dynamics. This paper introduces a novel second-order locally active memristor (LAM) governed by two coupled state variables, enabling richer nonlinear dynamics compared to conventional first-order devices. Even when the capacitances controlling the states are equal, the device retains two independent memory states, which broaden the design space for hysteresis tuning and allow flexible modulation of the current–voltage response. The second-order LAM is then integrated into a FitzHugh–Nagumo neuron circuit. The proposed circuit exhibits oscillatory firing behavior under specific parameter regimes and is further investigated under both DC and AC external stimulation. A comprehensive analysis of its equilibrium points is provided, followed by bifurcation diagrams and Lyapunov exponent spectra for key system parameters, revealing distinct regions of periodic, chaotic, and quasi-periodic dynamics. Representative time-domain patterns corresponding to these regimes are also presented, highlighting the circuit’s ability to reproduce a rich variety of neuronal firing behaviors. Finally, two unknown system parameters are estimated using the Aquila Optimization algorithm, with a cost function based on the system’s return map. Simulation results confirm the algorithm’s efficiency in parameter estimation.

Journal of Low Power Electronics and Applications doi: 10.3390/jlpea15040061

Authors: Wu Cong Lim Liter Siek Eng Leong Tan

Battery cell balancing is crucial in series-connected lithium-ion packs to maximize usable capacity, ensure safe operation, and prolong cycle life. This paper presents a comprehensive study and a novel adaptive duty-cycled hybrid balancing system that combines passive bleed resistors and an active switched-capacitor (SC) balancer, specifically designed for a 4-cell series-connected battery pack. This work also explored open circuit voltage (OCV)-driven adaptive pulse-frequency modulation (PFM) active balancing to achieve higher efficiency and better balancing speed based on different system requirements. Finally, this paper compares passive, active (SC-based), and adaptive duty-cycled hybrid balancing strategies in detail, including theoretical modeling of energy transfer and efficiency for each method. Simulation showed that the adaptive hybrid balancer speeds state-of-charge (SoC) equalization by 16.24% compared to active-only balancing while maintaining an efficiency of 97.71% with minimal thermal stress. The simulation result also showed that adaptive active balancing was able to achieve a high efficiency of 99.86% and provided an additional design degree of freedom for different applications. The results indicate that the adaptive hybrid balancer offered an excellent trade-off between balancing speed, efficiency, and implementation simplicity for 4-cell Li-ion packs, making it highly suitable for applications such as high-voltage portable chargers.

Journal of Low Power Electronics and Applications doi: 10.3390/jlpea15040060

Authors: Tong Zhang Bosen Huang Xiewen Liu Jiaqi Fan Junbo Li Zhao Yue Yanfang Wang

Microcontroller units (MCUs) serve as the core components of embedded systems. In the era of smart IoT, embedded devices are increasingly deployed on mobile platforms, leading to a growing demand for low-power consumption. As a result, low-power technology for MCUs has become increasingly critical. This paper systematically reviews the development history and current technical challenges of MCU low-power technology. It then focuses on analyzing system-level low-power optimization pathways for integrating MCUs with artificial intelligence (AI) technology, including lightweight AI algorithm design, model pruning, AI acceleration hardware (NPU, GPU), and heterogeneous computing architectures. It further elaborates on how AI technology empowers MCUs to achieve comprehensive low power consumption from four dimensions: task scheduling, power management, inference engine optimization, and communication and data processing. Through practical application cases in multiple fields such as smart home, healthcare, industrial automation, and smart agriculture, it verifies the significant advantages of MCUs combined with AI in performance improvement and power consumption optimization. Finally, this paper focuses on the key challenges that still need to be addressed in the intelligent upgrade of future MCU low power consumption and proposes in-depth research directions in areas such as the balance between lightweight model accuracy and robustness, the consistency and stability of edge-side collaborative computing, and the reliability and power consumption control of the sensor-storage-computing integrated architecture, providing clear guidance and prospects for future research.

Journal of Low Power Electronics and Applications doi: 10.3390/jlpea15040059

Authors: Orazio Aiello

After the success of the first edition [...]

Journal of Low Power Electronics and Applications doi: 10.3390/jlpea15040058

Authors: Kaijun Song Xinsheng Chen Zongrui He

This paper presents a microstrip active quasi-circulator designed for low-power wireless communication systems. The circuit consists of a second-order Wilkinson power divider and two power amplifiers with high gain and ultra-low noise characteristics. By leveraging the unidirectional transmission characteristics of the transistors and the isolation provided by resistors within the power divider, the interference between the transmitter (TX) and receiver (RX) is effectively suppressed. Additionally, thanks to the dual-amplifier architecture, no extra power amplification circuitry is required, thereby reducing the overall complexity and power consumption of the communication system. The detailed design procedure of the proposed quasi-circulator is presented. The measurement results show that, within the frequency range of 4.75 GHz to 6.11 GHz, the isolation between the TX and RX ports exceeds 20 dB, the return loss at each port is greater than 10 dB, and the transmission gains from the TX port to the antenna and from the antenna to the RX port are 3.1–8.7 dB and 2.7–4.0 dB, respectively, demonstrating a relative bandwidth of 25%.

Journal of Low Power Electronics and Applications doi: 10.3390/jlpea15040057

Authors: Jiale Guo Rongsheng Han Zibo Yang Guoqing An Rui Li Long Zhang

The frequency characteristics of the switching-mode power supply (SMPS) control loop under all operating conditions are crucial for performance evaluation and defect detection. Traditional methods, relyingon experiments under preset conditions, struggle to achieve comprehensive evaluation. This study proposes a frequency characteristic fitting method for all operating conditions based on FT-WOA-MLP. A discrete-point dataset covering all conditions of an LLC SMPS was obtained using the small-signal perturbation method, including input voltage, output current, injection frequency, and corresponding amplitude- and phase-frequency characteristics. The multilayer perceptron (MLP) model was trained on the training set covering all operating conditions, with the whale optimization algorithm (WOA) used to optimize the learning rate, and fine tuning (FT) applied to further enhance accuracy. Independent test set validation showed that, for amplitude-frequency characteristics, the mean absolute error (MAE) was 2.0995, the mean absolute percentage error (MAPE) was 0.0974, the root mean square error (RMSE) was 4.0474, and the coefficient of determination (R2) reached 0.92; for phase-frequency characteristics, the MAE was 3.502, the MAPE was 0.0956, the RMSE was 10.5192, and the R2 reached 0.94. The method accurately fits frequency characteristics under all conditions, supporting defect identification and performance optimization.

Journal of Low Power Electronics and Applications doi: 10.3390/jlpea15040056

Authors: Marco Grossi Martin Omaña

Portable and wearable sensors have gained attention in recent years to perform measurements in many different applications. Sensors based on Electrical Impedance Spectroscopy (EIS) are particularly promising, because they can make accurate measurements with minimum perturbation to the sample under test. Electrochemical biosensors are devices that use electrochemical techniques to measure a target analyte. In the case of electrochemical biosensors based on EIS, the measured impedance spectrum is fitted to that of an equivalent electrical circuit, whose component values are then used to estimate the concentration of the target analyte. Fitting EIS data is usually carried out by sophisticated algorithms running on a PC. In this paper, we have evaluated the feasibility to perform EIS data fitting using simple Artificial Neural Networks (ANNs) that can be run on resource constrained microcontrollers, which are typically used for portable and wearable sensors. We considered a typical case of an impedance spectrum in the range 0.1 Hz–10 kHz, modeled by using the simplified Randles equivalent circuit. Our analyses have shown that simple ANNs can be a low power alternative to perform EIS data fitting on low-cost microcontrollers with a memory occupation in the order of kilo bytes and a measurement accuracy between 1% and 3%.

Journal of Low Power Electronics and Applications doi: 10.3390/jlpea15040055

Authors: Suhao Chen Xiaopeng Yu Xiongchun Huang

The rapid growth of the Internet of Things (IoT) has driven the need for ultra-low-power wireless communication systems. Wake-up receivers (WuRXs) have emerged as a key technology to enable energy-efficient, near-always-on operation for IoT devices. This review explores the state of the art in WuRXs design, focusing on low-power architectures, key trade-offs, and recent advancements. We discuss the challenges in achieving low power consumption while maintaining sensitivity, power consumption, and interference resilience. The review highlights the evolution from radio frequency (RF) envelope detection architectures to more complex heterodyne and subthreshold designs and concludes with future directions for WuRXs research.

Journal of Low Power Electronics and Applications doi: 10.3390/jlpea15030054

Authors: Apinan Aurasopon Boontan Sriboonrueng Jirapong Jittakort Saichol Chudjuarjeen

This paper presents a Class E zero-voltage soft-switching (ZVS) resonant inverter integrated with a CLC filter and a digital resonant frequency tracking technique for driving a piezoelectric ceramic transducer (PZT) in ultrasonic cleaning applications. A digital signal processor (DSP) is used to dynamically monitor and adjust the operating frequency in response to slight variations in the cleaning load, employing a phase-locked loop (PLL) control scheme. The proposed method ensures that the inverter maintains ZVS operation across a frequency range from 30.0 kHz to 34.0 kHz, thereby improving energy efficiency and reducing switching losses. The system is capable of delivering a stable power output of 100 W. Both the simulation and experimental results validate the effectiveness of the proposed technique, demonstrating improved performance under varying load conditions. The combination of CLC filtering and frequency tracking offers a compact and robust solution suitable for ultrasonic cleaner systems and similar resonant-load applications.

Journal of Low Power Electronics and Applications doi: 10.3390/jlpea15030053

Authors: Benjamin Zambrano Sebastiano Strangio Esteban Garzón Alessandro Catania Giuseppe Iannaccone Marco Lanuzza

This paper introduces a physical unclonable function (PUF) based on a differential array of minimum-sized PMOS devices. Each response bit is obtained by comparing the two analog outputs of the differential array through a dynamic comparator with a trimmable offset. This offset is effectively used to mask potentially unstable response bits. To further improve PUF reliability, spatial majority voting is also implemented, resulting in a near-zero (<3.12×10−9) bit error rate (BER) at 1.2 V and 25 °C. Under variations in supply voltage (0.8–1.3 V) and temperature (0–75 °C), the native bit error rate of 3.5% is reduced to 9.73×10−4 after stabilization, consuming only 1.37 pJ per output bit.

Journal of Low Power Electronics and Applications doi: 10.3390/jlpea15030052

Authors: Dimitris Patrinos George Souliotis

A ring-oscillator based voltage-controlled oscillator (VCO) architecture with reduced frequency drift across temperature and process variations is presented in this paper. The frequency stability is achieved through two dedicated compensation techniques: a temperature compensation circuit that generates a proportional-to-absolute-temperature (PTAT) current to mitigate frequency shifts due to temperature changes, and a process compensation circuit that dynamically adjusts the frequency based on detected process corners. The proposed design is implemented in a 22 nm CMOS technology with a 0.8 V supply voltage and targets a nominal oscillation frequency of 2.5 GHz. The post-layout simulation results demonstrate a significant improvement in frequency stability, reducing temperature-induced frequency drift from 23.9% to a range of 5.4% over the −40 °C to 125 °C temperature range for the typical corner. Combining temperature and process compensation, the frequency drift is improved from 47.3% to better than 7.2%. The VCO also achieves a phase noise value about −80 dBc/Hz at a 1 MHz offset with an average power consumption of 380 µW, including the tuning mechanism and the compensation circuits.

Journal of Low Power Electronics and Applications doi: 10.3390/jlpea15030051

Authors: Teng Bao Mingmin Zhu Zhifeng He Yi Zhang Guoliang Yu Yang Qiu Jiawei Wang Yan Li Haibin Zhu Hao-Miao Zhou

With the rapid growth of unmanned aerial vehicles (UAVs) and IoT users, spectrum resources are becoming increasingly scarce, making cognitive radio (CR) technology a key approach to improving spectrum utilization. However, traditional antennas are difficult to meet the lightweight, compact, and low-drag requirements of small UAVs due to spatial constraints. This paper proposes a tri-mode frequency reconfigurable flexible antenna that can be conformally integrated onto UAV wing arms to enable CR dynamic frequency communication. The antenna uses a polyimide (PI) substrate and has compact dimensions of 31.4 × 58 × 0.05 mm3. A microstrip line-based frequency-selective network is designed, incorporating PIN and varactor diodes to realize three operation modes, dual-band (2.25~3.55 GHz, 5.6~6.75 GHz), single-band (3.35~5.3 GHz), and continuous tuning (4.3~6.1 GHz), covering WLAN, WiMAX, and 5G NR bands. Test results show that the antenna maintains stable performance under conformal conditions, with frequency shifts less than 4%, gain (3.65~4.77 dBi), and radiation efficiency between 67.2% and 82.9%. The tuning ratio reaches 38.8% in the continuous mode. This design offers a new solution for CR communication in compact UAV platforms and shows promising application potential.

Journal of Low Power Electronics and Applications doi: 10.3390/jlpea15030050

Authors: James S. Plank Charles P. Rizzo Bryson Gullett Keegan E. M. Dent Catherine D. Schuman

For most, if not all, AI-accelerated hardware, communication with the agent is expensive and heavily bottlenecks the hardware performance. This omnipresent hardware restriction is also found in neuromorphic computing: a novel style of computing that involves deploying spiking neural networks to specialized hardware to achieve low size, weight, and power (SWaP) compute. In neuromorphic computing, spike trains, times, and values are used to communicate information to, from, and within the spiking neural network. Input data, in order to be presented to a spiking neural network, must first be encoded as spikes. After processing the data, spikes are communicated by the network that represent some classification or decision that must be processed by decoder logic. In this paper, we first present principles for interconverting between spike trains, times, and values using custom-designed spiking subnetworks. Specifically, we present seven networks that encompass the 15 conversion scenarios between these encodings. We then perform three case studies where we either custom design a novel network or augment existing neural networks with these conversion subnetworks to vastly improve their communication performance with the outside world. We employ a classic space vs. time tradeoff by pushing spike data encoding and decoding techniques into the network mesh (increasing space) in order to minimize intra- and extranetwork communication time. This results in a classification inference speedup of 23× and a control inference speedup of 4.3× on field-programmable gate array hardware.

Journal of Low Power Electronics and Applications doi: 10.3390/jlpea15030049

Authors: Lin Xu Wengan Li Zenglong Zhao Fanyi Meng

At present, environmental pollution is becoming more and more serious, and the energy problem is becoming more prominent. Energy-braking recovery can collect the mechanical energy lost in the traditional braking process and convert it into electricity or other forms of energy for vehicle reuse, thus reducing carbon emissions, achieving energy saving and emission reduction, and promoting green development. Based on this, this paper studies the energy-braking recovery method. The study focuses specifically on the recovery of energy during vehicle braking triggered by brake-signal activation, without addressing alternative deceleration strategies under braking conditions. The proposed energy-braking recovery scheme is evaluated primarily through simulation, with the analysis grounded in practical application scenarios and leveraging existing technologies. Firstly, the principle of energy-braking recovery is introduced, and the method of estimating the State on Charge (SOC) of the battery and controlling the motor speed is determined. Then, the simulation model of the energy brake recovery system is built with MATLAB R2023b (MathWorks, Natick, MA, USA), and the design ideas and specific structures of the three modules of the simulation model are introduced in detail. Finally, the results of the simulated motor speed and SOC value of the battery are analysed, and it is confirmed that they meet the requirements of the system and achieve close to the ideal effect.

Journal of Low Power Electronics and Applications doi: 10.3390/jlpea15030048

Authors: Yuqing Yang Song Xu Wei Jiang Seiji Hashimoto

Hybrid electric vehicles (HEVs) have gained significant attention for their superior energy efficiency and are becoming a predominant mode of urban transportation. The DC/DC converter plays a critical role in HEV energy management systems, especially in matching the voltage levels between the battery and DC bus. This paper proposes a novel high-gain DC/DC converter with a wide input voltage range based on coupled inductors. The innovation lies in the integration of a resonant cavity and the simultaneous realization of zero-voltage switching (ZVS) and zero-current switching (ZCS), effectively reducing both voltage/current stresses on the power switches and switching losses. Compared with conventional topologies, the proposed design achieves higher voltage gain without extreme duty cycles, improved conversion efficiency, and enhanced reliability. Detailed operating principles are analyzed, and design conditions for voltage stress reduction, gain extension, and soft switching are derived. The simulation model has been conducted in a PSIM environment, and a 300 W experimental prototype, implemented using a dsPIC33FJ64GS606 digital controller, has been established and demonstrates 93% peak efficiency at a 10 times voltage gain. The performance and practical feasibility of the proposed topology have been evaluated by both simulation and experiments.

Journal of Low Power Electronics and Applications doi: 10.3390/jlpea15030047

Authors: Geethu Remadevi Somanathan Ujarla Harshavardhan Reddy Ramesh Bhakthavatchalu

This paper presents a power-aware Reconfigurable Parameterizable Pseudorandom Pattern Generator (RP-PRPG) for a number of applications, including built in self-testing (BIST) and cryptography. Linear Feedback Shift Registers (LFSRs) are broadly utilized in pattern generation due to their efficiency and simplicity. However, the diversity of generated patterns, as well as their power consumption, improves through circuit modifications. This work explores enhancements to LFSR structures to achieve broader range of patterns with reduced power consumption for BIST-based applications. The proposed circuit constructed on the LFSR platform can be programmed to generate patterns with varying degrees of different LFSR configurations. Diverse set of patterns of any circuit arrangement can be created using any characteristic polynomial and by utilizing the reseeding capacity of the circuit. The circuit combines a double-tier linear feedback circuit with zero forcing methods, resulting in more than 70% transition reduction, thus significantly lowering power dissipation. The behaviour of the proposed circuit is assessed for characteristic polynomials with degrees ranging from 4 to 128 using various Linear Feedback Shift Register (LFSR) topologies. For reconfigurable HDL and ASIC synthesis, the power-aware RP-PRPG can be used to generate an efficient set of stream ciphers as well as applications involving the scan-for-test protocol.

Journal of Low Power Electronics and Applications doi: 10.3390/jlpea15030046

Authors: Lei Zhong Xuejiao Jiang Jialong Xu Kaihong Zheng Min Wu Lei Gao Chao Ma Dewen Zhu Yuan Ai

Privacy-sensitive electricity scene classification requires robust models under data localization constraints, making federated learning (FL) a suitable framework. Existing FL frameworks face two critical challenges in multi-label electricity scene classification: (1) Label correlations and their strengths significantly impact classification performance. (2) Electricity scene data and labels show distributional inconsistencies across regions. However, current FL frameworks lack explicit modeling of label correlation strengths, and locally trained regional models naturally capture these differences, leading to regional differences in their model parameters. In this scenario, the server’s standard single-stage aggregation often over-averages the global model’s parameters, reducing its discriminative ability. To address these issues, we propose FMMAN, a federated multi-stage attention neural network for multi-label electricity scene classification. The main contributions of this FMMAN lie in label correlation learning and the stepwise model aggregation. It splits the client–server interaction into multiple stages: (1) Clients train models locally to encode features and label correlation strengths after receiving the server’s initial model. (2) The server clusters these locally trained models into K groups to ensure that models within a group have more consistent parameters and generates K prototype models via intra-group aggregation to reduce over-averaging. The K models are then distributed back to the clients. (3) Clients refine their models using the K prototypes with contrastive group-specific consistency regularization to further mitigate over-averaging, and sends the refined model back to the server. (4) Finally, the server aggregates the models into a global model. Experiments on multi-label benchmarks verify that FMMAN outperforms baseline methods.

Journal of Low Power Electronics and Applications doi: 10.3390/jlpea15030045

Authors: Ziyuan Yang Shengquan Li Kaiwen Cao Donglei Chen Juan Li Wei Cao

Considering the challenges posed by traditional continuous control set model predictive control (CCS-MPC) calculations, this paper proposes an event-triggered-based model predictive control (ET-MPC). First, a novel tracking error state-space model is proposed to improve tracking performance. Second, a reduced-order extended state observer (RESO) is designed to estimate and compensate for the total disturbances, thereby effectively improving robustness against the variations of the load resistance and reference voltage. At the same time, RESO significantly reduces computational complexity and accelerates the convergence speed of state estimation. Subsequently, an event trigger mechanism is introduced to enhance the MPC with a threshold function for the converter status. Finally, the reduced-order extended state observer-based model predictive control (RESO-MPC) is compared with the proposed ET-MPC through experiments. The ripple voltage of ET-MPC is within 2%, and the computational burden is reduced by more than 57%, verifying the effectiveness of the proposed ET-MPC.

Journal of Low Power Electronics and Applications doi: 10.3390/jlpea15030044

Authors: Zhihao Xu Dan Zhang Rongkang Xuan Shenxiang Yang Na Wang

This study investigates the propagation characteristics and field distribution of photonic crystals composed of epsilon-near-zero (ENZ) materials and metal cylinders. The research reveals that the cutoff frequency of the photonic crystal formed by combining metal cylinders with an ENZ background is independent of the volume fraction of the metal cylinders and exhibits a stop-band profile within the measured frequency range. This unique behavior is attributed to the scattering of long-wavelength light when the wavelength approaches the effective wavelength range of the ENZ material. Taking advantage of this feature, the study selectively filters specific wavelength ranges from the mid-frequency band by varying the ratio of cylinder radius to lattice constant (R/a). Decreasing the R/a ratio enables the design of waveguide devices that operate over a broader guided wavelength range within the intermediate-frequency band. The findings emphasize the importance of the interaction between light and ENZ materials in shaping the transmission characteristics of photonic crystal structures.

Journal of Low Power Electronics and Applications doi: 10.3390/jlpea15030043

Authors: Yangfan Liu Qixiao Li Zhongxuan Wang

Bipolar power supply can effectively reduce line losses and optimize power transmission. This paper proposes a low-power bipolar DC–DC converter with voltage self-balancing, which not only achieves bipolar output but also automatically balances the inter-pole voltage under load imbalance conditions without requiring additional voltage balancing control. This paper first elaborates on the derivation process of the proposed converter, then analyzes its working principles and performance characteristics. A 400 W experimental prototype is built to validate the correctness of the theoretical analysis and the voltage self-balancing capability. Finally, loss analysis and conclusions are presented.

Journal of Low Power Electronics and Applications doi: 10.3390/jlpea15030042

Authors: Vadim Kuznetsov

XSPICE models for a generic transmission line, a microstrip line, and coupled microstrips are presented. The developed models extend general-purpose circuit simulation tools using RF circuits design features. The models could be used for circuit simulation in frequency, DC, and time domains for any active or passive RF or microwave schematic (including microwave monolithic integrated circuits—MMICs) involving transmission lines. The presented models could be used with any circuit simulation backend supporting XSPICE extensions and could be integrated without patching the core simulator code. The presented XSPICE models for microstrip lines take into account the frequency dependency of characteristic impedance and dispersion. The models were designed using open-source circuit simulation software. This study provides a practical example of the low-noise RF amplifier (LNA) design with Ngspice simulation backend using the proposed models.

Journal of Low Power Electronics and Applications doi: 10.3390/jlpea15030041

Authors: Rasoul Akbari Afshin Izadian

Split-shaft wind turbines decouple the turbine’s shaft from the generator’s shaft, enabling several modifications in the drivetrain. One of the significant achievements of a split-shaft drivetrain is the reduction in size of the excitation circuit. The grid-side converter is eliminated, and the rotor-side converter can safely reduce its size to a fraction of a full-size excitation. Therefore, this low-power-rated converter operates at low voltage and handles regular operations well. However, fault conditions may expose weaknesses in the converter and push it to its limits. This paper investigates the effects of the reduced-size rotor-side converter on the voltage ride-through capabilities required from all wind turbines. Four different protection circuits, including the active crowbar, active crowbar along a resistor–inductor circuit (C-RL), series dynamic resistor (SDR), and new-bridge fault current limiter (NBFCL), are employed, and their effects are investigated and compared. Wind turbine controllers are also utilized to reduce the impact of faults on the power electronic converters. One effective method is to store excess energy in the generator’s rotor. The proposed low-voltage ride-through strategies are simulated in MATLAB Simulink (2022b) to validate the results and demonstrate their effectiveness and functionality.

Journal of Low Power Electronics and Applications doi: 10.3390/jlpea15030040

Authors: Muhammet Arucu Teodor Iliev

This study presents a comprehensive performance evaluation of field-programmable gate array (FPGA), graphics processing unit (GPU), and central processing unit (CPU) platforms for implementing finite impulse response (FIR) filters in semiconductor-based digital signal processing (DSP) systems. Utilizing a standardized FIR filter designed with the Kaiser window method, we compare computational efficiency, latency, and energy consumption across the ZYNQ XC7Z020 FPGA, Tesla K80 GPU, and Arm-based CPU, achieving processing times of 0.004 s, 0.008 s, and 0.107 s, respectively, with FPGA power consumption of 1.431 W and comparable energy profiles for GPU and CPU. The FPGA is 27 times faster than the CPU and 2 times faster than the GPU, demonstrating its suitability for low-latency DSP tasks. A detailed analysis of resource utilization and scalability underscores the FPGA’s reconfigurability for optimized DSP implementations. This work provides novel insights into platform-specific optimizations, addressing the demand for energy-efficient solutions in edge computing and IoT applications, with implications for advancing sustainable DSP architectures.

Journal of Low Power Electronics and Applications doi: 10.3390/jlpea15030039

Authors: Zhengqiang Xiong Chang Han Xiaoliang Wang Li Gao

Coverage path planning solves the problem of moving an effector over all points within a specific region with effective routes. Most existing studies focus on geometric constraints, often overlooking robot-specific features, like the available energy, weight, maximum speed, sensor resolution, etc. This paper proposes a coverage path planning algorithm for Unmanned Aerial Vehicles (UAVs) that minimizes energy consumption while satisfying a set of other requirements, such as coverage and observation resolution. To deal with these issues, we propose a novel energy-optimal coverage path planning framework for monitoring tasks. Firstly, the 3D terrain’s spatial characteristics are digitized through a combination of parametric modeling and meshing techniques. To accurately estimate actual energy expenditure along a segmented trajectory, a power estimation module is introduced, which integrates dynamic feasibility constraints into the energy computation. Utilizing a Digital Surface Model (DSM), a global energy consumption map is generated by constructing a weighted directed graph over the terrain. Subsequently, an energy-optimal coverage path is derived by applying a Genetic Algorithm (GA) to traverse this map. Extensive simulation results validate the superiority of the proposed approach compared to existing methods.

Journal of Low Power Electronics and Applications doi: 10.3390/jlpea15030038

Authors: Longsheng Zhang Kaihong Wang Shilong Guo Binxin Zhu

The eGaN HEMT power devices face serious crosstalk problems when applied to high-frequency bridge circuits, thereby limiting the switching performance of these devices. To address this issue, a gate driver is proposed in this paper that can suppress both positive and negative crosstalk of eGaN HEMT power devices, offering the advantages of simple control and easy integration. The basic idea is to suppress positive crosstalk by constructing a negative voltage capacitor, and to suppress negative crosstalk by reducing the impedance of the gate loop. To verify the capability of the proposed gate driver, double-pulse and synchronous Buck test platforms are constructed. The experimental results clearly demonstrate that the proposed gate driver reduces the positive and negative crosstalk spikes by 2.03 V and 1.54 V, respectively, ensuring that the positive and negative crosstalk spikes fall within a safe operating range. Additionally, the turn-off speed of the device is enhanced, leading to a reduction in switching loss.

Journal of Low Power Electronics and Applications doi: 10.3390/jlpea15030037

Authors: Jennifer Hasler Praveen Raj Ayyappan

This article presents an energy-efficient IC architecture implementation of an analog image-processing ML system, where the primary issue is analog architecture development for existing energy-efficient analog computing devices. An architecture is developed for image classification, transforming a typical imager input into a classified result using a particular NN algorithm, a convolutional NN (ConvNN). These efforts show the need to continue to develop energy-efficient analog architectures alongside efficient analog circuits to fully exploit the opportunities of analog computing for system application.

Journal of Low Power Electronics and Applications doi: 10.3390/jlpea15020036

Authors: Fahad M. Alotaibi

Wireless Power Transfer (WPT) enables efficient, contactless charging for mobile devices by eliminating mechanical connectors and wiring, thereby enhancing user experience and device longevity. However, conventional WPT systems remain prone to performance issues such as coil misalignment, resonance instability, and thermal losses. Addressing these challenges involves designing coil geometries that operate at lower resonant frequencies to strengthen magnetic coupling and decrease resistance. This work introduces a WPT system with a performance-driven coil design aimed at maximizing magnetic coupling and mutual inductance between the transmitting (Tx) and receiving (Rx) coils in mobile devices. Due to the nonlinear behavior of magnetic flux and the high computational cost of simulations, exploring the full design space for coils using ANSYS Maxwell becomes impractical. To address this complexity, a machine learning (ML)-based optimization framework is developed to efficiently navigate the design space. The framework integrates a hybrid sequential neural network and multivariate regression model to optimize coil winding and ferrite core geometry. The optimized structure achieves a mutual inductance of 12.52 μH with a conventional core, outperforming many existing ML models. Finite element simulations and experimental results validate the robustness of the method, which offers a scalable solution for efficient wireless charging in compact, misalignment-prone environments.

Journal of Low Power Electronics and Applications doi: 10.3390/jlpea15020035

Authors: Juan Cuenca Benjamin Zambrano Esteban Garzón Luis Miguel Prócel Marco Lanuzza

Dynamic comparators play an important role in electronic systems, requiring high accuracy, low power consumption, and minimal offset voltage. This work proposes an accurate and low-complexity offset calibration design based on a capacitive load approach. It was designed using a 65 nm CMOS technology and comprehensively evaluated under Monte Carlo simulations and PVT variations. The proposed scheme was built using MIM capacitors and transistor-based capacitors, and it includes Verilog-based calibration algorithms. The proposed offset calibration is benchmarked, in terms of precision, calibration time, energy consumption, delay, and area, against prior calibration techniques: current injection via gate biasing by a charge pump circuit and current injection via parallel transistors. The evaluation of the offset calibration schemes relies on Analog/Mixed-Signal (AMS) simulations, ensuring accurate evaluation of digital and analog domains. The charge pump method achieved the best Energy-Delay Product (EDP) at the cost of lower long-term accuracy, mainly because of its capacitor leakage. The proposed scheme demonstrated superior performance in offset reduction, achieving a one-sigma offset of 0.223 mV while maintaining precise calibration. Among the calibration algorithms, the window algorithm performs better than the accelerated calibration. This is mainly because the window algorithm considers noise-induced output oscillations, ensuring consistent calibration across all designs. This work provides insights into the trade-offs between energy, precision, and area in dynamic comparator designs, offering strategies to enhance offset calibration.

Journal of Low Power Electronics and Applications doi: 10.3390/jlpea15020034

Authors: Nikolay Hinov Tsvetana Grigorova

As power electronics continue to advance, the demand for highly efficient and low-loss DC/DC converters has grown significantly. This article comprehensively analyses ZCS quasi-resonant switch cell losses and efficiency in buck L-type zero-current switching (ZCS) quasi-resonant DC/DC converters. The main part of the study includes a comparative analysis of conduction losses in semiconductor switches of conventional PWM buck converters and zero-current switching (ZCS) quasi-resonant buck converters (L-type), utilizing both specific and generalized design equations. Novel coefficients are introduced that enable the evaluation of static power losses in the classical buck converter compared to those in L-type ZCS buck quasi-resonant converters under identical conditions. The article also discusses design considerations aimed at minimizing static losses. An L-type half-mode zero-current switching (ZCS) buck quasi-resonant DC/DC converter (QRC) is implemented to verify the analytical results. Various simulations were conducted using PSpice in the Texas Instruments simulation environment, along with experimental studies at different switching frequencies and load conditions. The proposed methodology integrates both analytical and simulation approaches to analyze energy losses and key parameters influencing the converter’s efficiency. The obtained results show that the relative error between the analytical, simulation, and experimental results is below 5%.

Journal of Low Power Electronics and Applications doi: 10.3390/jlpea15020033

Authors: Manon Fourniol Rémy Vauché Guillaume Rao Eric Watelain Edith Kussener

In the context of aging populations, it has become necessary to develop new methods and devices for the daily home-based self-rehabilitation of elderly people. To this end, this paper proposes and evaluates the use of an easy-to-use single battery-powered device including a 3D accelerometer and a 3D gyroscope, where light algorithms, such as the complementary filter and the Kalman filter, are implemented to estimate the elbow joint angle. During experiments, a robotic arm and a human arm were used to obtain an error interval for each tested algorithm; the robotic arm allows for reproducible movements and reproducible results, which allows us to independently verify the impact of parameters such as the sensor’s movement speed on the algorithm precision. The experimental results show that the algorithm that uses only accelerometer data is one of the most relevant since it allows us to obtain a Root Mean Square Error between 1.83° and 5.52° at a sensor data rate of 100 Hz, which is similar to the results obtained using the data fusion algorithms tested. Nevertheless, it has a lower power consumption since it requires only 58 cycles when using an ARM Cortex-M4 processor (which is lower than that of the other data fusion algorithms tested by a factor of at least two), and it does not necessitate the additional sensor required by the other data fusion algorithms tested (such as a gyroscope or a magnetometer). The algorithm using only accelerometer data also seems to be the algorithm with the lowest power consumption and should be preferred. Moreover, its power consumption can be reduced by more than the increase in the error when reducing the rate of the data output by the sensor. In this work, a reduction in the data rate from 100 Hz to 10 Hz increased the RMSE by a factor of 1.8 but could reduce the power consumption associated with the sensor and the algorithm’s computation by a factor of 10. Finally, the experimental results show that the higher the speed of the sensor’s motion, the higher the error obtained using only accelerometer data. Nevertheless, the algorithm that uses only accelerometer data remains well suited to rehabilitation exercises or mobility evaluations since the speed of the sensor’s movement is also moderate.

Journal of Low Power Electronics and Applications doi: 10.3390/jlpea15020032

Authors: Jung-Jen Hsu Yao-Chian Lin Stephen J. H. Yang

This paper presents a 0.8 V low-power CMOS voltage-controlled oscillator (VCO) with a wide tuning range, fabricated using a TSMC 0.18 μm process. The proposed design incorporates body-biasing techniques and an optimized varactor structure to achieve a tuning range of 1124 MHz (5.829–4.705 GHz) and low phase noise of −117.6 dBc/Hz at a 1 MHz offset. Operating at an ultra-low supply voltage of 0.8 V, the VCO consumes only 3.4 mW, demonstrating excellent power efficiency. A buffer circuit is also employed to enhance output symmetry and suppress flicker noise without introducing additional control complexity. With a figure-of-merit (FOM) of −188.6 dBc/Hz and a wide tuning range of 22.2%, the proposed VCO is well-suited for modern low-power communication systems, including 802.11ac, 5G transceivers, satellite links, and compact IoT devices.

Journal of Low Power Electronics and Applications doi: 10.3390/jlpea15020031

Authors: Béatrice Guénégo Caroline Lelandais-Perrault Emilie Avignon-Meseldzija Gérard Sou Philippe Bénabès

The ST segment of an ECG signal is a feature that changes in the event of cardiac ischemia, a condition that is an early warning sign of myocardial infarction. Being able to monitor this feature in real time would be highly beneficial for preventing recurrent heart attacks. However, to be worn daily, such a monitoring device must be extremely miniaturized, down to the scale of a single integrated circuit. Currently, it is possible to integrate a heart rate detector, but, to our knowledge, no existing work presents a chip capable of detecting ST segment deviation. This is mainly because accurate ST segment measurement requires low-distortion signal processing, as specified in the International Electrotechnical Commission (IEC) standard. At the same time, the system is required to filter out baseline wander, whose frequency components may partially overlap with those of the ST segment. In this study, we relied on wavelet-based analysis and reconstruction to compare several wavelet types. We optimized their hyperparameters to minimize implementation complexity while satisfying the low-distortion constraints. We also propose an ASIC-oriented architecture and evaluate its post-layout performance in terms of area and power consumption. The post-layout results indicate that the Daubechies wavelet db3 offers the best trade-off among the evaluated configurations. It exhibits an area utilization of 1.18 mm2 and a post-layout power consumption of 4.89 μW, while preserving the ST segment in compliance with the IEC standard, thanks in particular to its effective baseline wandering filtering of 6.9 dB. These results demonstrate the feasibility of embedding automatic ST segment extraction on-chip.

Journal of Low Power Electronics and Applications doi: 10.3390/jlpea15020030

Authors: Hao Jiang Zenglong Zhao Nengxu Zhu Fanyi Meng

This paper presents an active phase shifter for phased array system applications, implemented using 0.18 μm SiGe BiCMOS technology. The phase shifter circuit consists of a wideband quadrature signal generator, a vector modulator, an input balun, and an output balun. To enhance the bandwidth, a polyphase filter is employed as the quadrature signal generator, and a two-stage RC-CR filter with a highly symmetrical miniaturized layout is cascaded to create multiple resonant points, thus extending the phase shifter’s bandwidth to cover the required range. The gain of the variable-gain amplifier within the vector modulator is adjustable by varying the tail current, thereby enlarging the range of selectable points, improving phase-shifting accuracy, and reducing gain fluctuations. The measurement results show that the proposed active phase shifter achieves an RMS phase error of less than 2° and a gain variation ranging from −1.2 dB to 0.1 dB across a 20 GHz to 30 GHz bandwidth at room temperature. The total chip area is 0.4 mm2, with a core area of 0.165 mm2, and consumes 19.5 mW of power from a 2.5 V supply.

Journal of Low Power Electronics and Applications doi: 10.3390/jlpea15020029

Authors: Xin Wang Zishuo Li Zhen Lin Fanyi Meng

This paper introduces a novel topology called the dual-path step-down converter with auxiliary switches to minimize voltage stress and enable wide voltage conversion ranges. The proposed dual-path step-down converter with auxiliary switches, which uses an inductor and flying capacitor as power conversion components, helps to reduce the voltage stress on the power switches. By adding auxiliary switches, the proposed topology achieves the same voltage conversion ratio range as that of a conventional buck converter. Additionally, soft-start technology is incorporated to reduce the initial inrush current. Furthermore, this paper introduces a system-level design procedure for DC-DC converters. Designed for low-power applications with lithium-ion (Li-ion) batteries, the proposed converter steps down the battery voltage to 1.2 V. With a 380 nH inductor and a 5 µF output capacitor, the converter attains a peak efficiency of 90% under the conditions of 2.7 V to 1.2 V conversion.

Journal of Low Power Electronics and Applications doi: 10.3390/jlpea15020028

Authors: Ibrahim L. Abdalla Fatma A. Matter Ahmed A. Afifi Mohamed I. Ibrahem Hesham F. A. Hamed Eslam S. El-Mokadem

This paper elaborates on the proposal of a new analytical model for a non-ballistic transport scenario for Schottky barrier carbon nanotube field effect transistors (SB-CNTFETs). The non-ballistic transport scenario depends on incorporating the effects of acoustic phonon (A-Ph) and optical phonon (O-Ph) electron scattering mechanisms. The analytical model is rooted in the solution of the Landauer integral equation, which is modified to account for non-ballistic transport through a set of approximations applied to the Wentzel–Kramers–Brillouin (WKB) transmission probability and the Fermi–Dirac distribution function. Our proposed model was simulated to evaluate the total current and transconductance, considering scenarios both with and without the electron–phonon scattering effect. The simulation results revealed a substantial decrease of approximately 78.6% in both total current and transconductance due to electron–phonon scattering. In addition, we investigated the impact of acoustic phonon (A-Ph) and optical phonon (O-Ph) scattering on the drain current under various conditions, including different temperatures, gate lengths, and nanotube chiralities. This comprehensive analysis helps in understanding how these parameters influence device performance. Compared with experimental data, the model’s simulation results demonstrate a high degree of agreement. Furthermore, our fully analytical model achieves a significantly faster runtime, clocking in at around 2.726 s. This validation underscores the model’s accuracy and reliability in predicting the behavior of SB-CNTFETs under non-ballistic conditions.

Journal of Low Power Electronics and Applications doi: 10.3390/jlpea15020027

Authors: Shahrin Akter Mohammad Rafiqul Haider

Inkjet-printed circuits on flexible substrates are rapidly emerging as a key technology in flexible electronics, driven by their minimal fabrication process, cost-effectiveness, and environmental sustainability. Recent advancements in inkjet-printed devices and circuits have broadened their applications in both sensing and computing. Building on this progress, this work has developed a nonlinear computational element coined as mTanh to serve as an activation function in neural networks. Activation functions are essential in neural networks as they introduce nonlinearity, enabling machine learning models to capture complex patterns. However, widely used functions such as Tanh and sigmoid often suffer from the vanishing gradient problem, limiting the depth of neural networks. To address this, alternative functions like ReLU and Leaky ReLU have been explored, yet these also introduce challenges such as the dying ReLU issue, bias shifting, and noise sensitivity. The proposed mTanh activation function effectively mitigates the vanishing gradient problem, allowing for the development of deeper neural network architectures without compromising training efficiency. This study demonstrates the feasibility of mTanh as an activation function by integrating it into an Echo State Network to predict the Mackey–Glass time series signal. The results show that mTanh performs comparably to Tanh, ReLU, and Leaky ReLU in this task. Additionally, the vanishing gradient resistance of the mTanh function was evaluated by implementing it in a deep multi-layer perceptron model for Fashion MNIST image classification. The study indicates that mTanh enables the addition of 3–5 extra layers compared to Tanh and sigmoid, while exhibiting vanishing gradient resistance similar to ReLU. These results highlight the potential of mTanh as a promising activation function for deep learning models, particularly in flexible electronics applications.

Journal of Low Power Electronics and Applications doi: 10.3390/jlpea15020026

Authors: Shiwei Sun Dinghao Ma Boxi Ye Guanshun Liu Nanting Luo Hao Huang

The lack of ultra-thin, controllable dielectric layers poses challenges for reducing power consumption in 2D FETs. In this study, plasma-enhanced atomic layer deposition was employed to fabricate a highly reliable, ultra-thin aluminum oxide (Al2O3) dielectric layer with a thickness of 4 nm. The Al2O3 film grown on highly conductive silicon substrates demonstrated a maximum breakdown field of 5.98 MV/cm and a leakage current density as low as 2.48 × 10−7 A/cm2 at 1 MV/cm. MoS2 FETs incorporating this Al2O3 gate dielectric exhibited high-performance n-type characteristics at a low operating voltage of 1 V, achieving a subthreshold swing (SS) of 65 mV/dec, a threshold voltage (Vth) of −0.96 V, a high carrier mobility (μ) of 34.85 cm2·V−1·s−1, and an on/off current ratio exceeding 106. These results highlight the potential of Al2O3 in enabling low-power 2D electronic devices for post-Moore applications.

Journal of Low Power Electronics and Applications doi: 10.3390/jlpea15020025

Authors: Xin Wang Qingsong Zhao Zenglong Zhao Fanyi Meng

This study presents a hard-switching full-bridge DC-DC converter with synchronous rectification based on Gallium Nitride (GaN) transistors to evaluate the advantages of GaN devices in power supplies. In comparison to traditional silicon-based devices, GaN transistors are utilized in both the primary and secondary stages of the converter, exploiting GaN’s lower on-resistance to enhance performance. The converter operates at a switching frequency of 300 kHz, with an input voltage range of 36 V to 75 V, delivering an output of 28 V/42 A. Experimental results show that the GaN-based converter achieves an output power of 1176 W within standard half-brick package dimensions. The measured peak efficiency is 97.1%, and the power density reaches 430 W/in3. These findings demonstrate that GaN-based converters offer superior efficiency and power density compared to conventional silicon-based designs, making them highly suitable for aerospace, automotive, and communication power supplies.

Journal of Low Power Electronics and Applications doi: 10.3390/jlpea15020024

Authors: Hector Daniel Rico-Aniles Anindita Paul Jaime Ramirez-Angulo Antonio Lopez-Martin Ramon G. Carvajal

A family of improved low-voltage switched-capacitor circuits is introduced. It is based on the utilization of multiple-output class AB/AB op-amp architectures that provide true sample and hold outputs that are not subject to a reset phase as with conventional switched-capacitor circuits. This feature essentially relaxes the op-amp slew rate requirements, allowing a higher speed and simple low-voltage operation. A power-efficient GB boosting technique based on resistive local common mode feedback is used to significantly improve the GB and internal/external slew rate of the op-amps with only a 36.5% additional power dissipation.

Journal of Low Power Electronics and Applications doi: 10.3390/jlpea15020023

Authors: Xinyuan Hu Yanfeng Jiang

MEMS resonators have attracted attention for their wide applications in highly accurate clock references, sensors, wireless communications, frequency control, etc. Most of the output frequencies of MEMS resonators require post-processing or calibration to be accurate enough. In this paper, a charge pump phase-locked loop-based frequency conditioning method for MEMS resonators is explored. An optimization scheme is proposed to enhance the frequency stability and signal quality of MEMS resonators. The experimental results show that the method significantly improves the resonator performance and achieves effective control of the resonant frequency. This research provides a new technical path for the design of high-performance MEMS oscillators, which has important theoretical significance and practical application value.

Journal of Low Power Electronics and Applications doi: 10.3390/jlpea15020022

Authors: Ondrej Kachman Peter Malík Marcel Baláž Libor Majer Gábor Gyepes

Low-power embedded devices are widely used in sensor networks, monitoring systems, and industrial applications. These devices typically rely on internal flash memory, where storage is constrained by bootloaders, communication stacks, and other software. Adding external memory increases cost and energy consumption, making efficient memory utilization essential. This article presents key design concepts for developing an efficient, lightweight, and reliable embedded filesystem. It introduces an improved version of the configurable flash filesystem (CFFS), designed to maximize memory utilization, minimize flash wear, and support portability across hardware platforms and operating systems. Reliability mechanisms integrated into CFFS are also discussed. We compare CFFS with widely used low-power embedded filesystems—LittleFS, SPIFFS, and FDS—highlighting its advantages in memory efficiency and reduced flash memory wear. Experimental results demonstrate that CFFS achieves up to 99% memory utilization while significantly reducing erase operations.

Journal of Low Power Electronics and Applications doi: 10.3390/jlpea15020021

Authors: Padmanabhan Balasubramanian Syed Mohammed Mosayeeb Al Hady Zaheen Douglas L. Maskell

Approximate computation has emerged as a promising alternative to accurate computation, particularly for applications that can tolerate some degree of error without significant degradation of the output quality. This work analyzes the application of approximate computing for machine learning, specifically focusing on k-means clustering, one of the more widely used unsupervised machine learning algorithms. The k-means algorithm partitions data into k clusters, where k also denotes the number of centroids, with each centroid representing the center of a cluster. The clustering process involves assigning each data point to the nearest centroid by minimizing the within-cluster sum of squares (WCSS), a key metric used to evaluate clustering quality. A lower WCSS value signifies better clustering. Conventionally, WCSS is computed with high precision using an accurate adder. In this paper, we investigate the impact of employing various approximate adders for WCSS computation and compare their results against those obtained with an accurate adder. Further, we propose a new approximate adder (NAA) in this paper. To assess its effectiveness, we utilize it for the k-means clustering of some publicly available artificial datasets with varying levels of complexity, and compare its performance with the accurate adder and many other approximate adders. The experimental results confirm the efficacy of NAA in clustering, as NAA yields WCSS values that closely match or are identical to those obtained using the accurate adder. We also implemented hardware designs of accurate and approximate adders using a 28 nm CMOS standard cell library. The design metrics estimated show that NAA achieves a 37% reduction in delay, a 22% reduction in area, and a 31% reduction in power compared to the accurate adder. In terms of the power-delay product that serves as a representative metric for energy efficiency, NAA reports a 57% reduction compared to the accurate adder. In terms of the area-delay product that serves as a representative metric for design efficiency, NAA reports a 51% reduction compared to the accurate adder. NAA also outperforms several existing approximate adders in terms of design metrics while preserving clustering effectiveness.

Journal of Low Power Electronics and Applications doi: 10.3390/jlpea15020020

Authors: Zhiyu Li Xueqian Shang Haigang Feng Xinpeng Xing

Continuous-time Sigma-Delta (CTSD) Analog-to-Digital Converter (ADC) is widely used in wireless receivers due to its built-in anti-aliasing and resistive input. In order to achieve a wide bandwidth while ensuring low power consumption, this paper proposes a CT 2-2 Multi-stAge Noise-sHaping (MASH) ADC for wireless communication. In order to reduce power consumption, the loop filter adopts a feedforward structure, and the operational amplifier uses complementary differential input pairs and feedforward compensation. The pseudo-random sequence injection and Least Mean Squares (LMS) algorithm are adopted to calibrate the digital noise cancelation filter to match the analog transfer function. The simulation results obtained in 40 nm CMOS show that the presented 2-2 CT MASH ADC achieves a 76.8 dB signal-to-noise-and-distortion ratio (SNDR) at a 50MHz bandwidth (BW) with a 1.6 GHz sampling rate and consumes 29.7 mW power under 1.2/0.9 V supply, corresponding to an excellent figure of merit (FoM) of 169.1 dB.

Journal of Low Power Electronics and Applications doi: 10.3390/jlpea15020019

Authors: Georgios Siamantas Dimitris Rountos Dionisis Kandris

Wireless sensor networks are at the center of scientific interest thanks to their ever-growing range of applications. The main weakness of wireless sensor networks is the restricted lifetime of their sensor nodes due to limited energy capacity. The extension of the lifespan of sensor nodes is pursued in various ways. One of them is the usage of protocols that achieve energy-efficient routing. LEACH is one of the pioneering protocols of this type and has numerous descendants. This research article focuses on energy-efficient routing protocols that are based on LEACH. Specifically, a study of LEACH along with many of its successors is provided. In addition, a novel protocol of this kind, named T-LEACHSAS is introduced. This protocol combines the threshold-based approach for selecting cluster heads that was first introduced in T-LEACH, which is a well-known protocol, along with a mechanism for sleep–awake scheduling. The performance of T-LEACHSAS is compared against that of both LEACH and T-LEACH via simulation tests that confirm that T-LEACHSAS indeed provides a promising choice for energy-efficient routing in WSNs.

Journal of Low Power Electronics and Applications doi: 10.3390/jlpea15020018

Authors: Zongrui He Kaijun Song Jia Yao Yedi Zhou

This paper proposes a miniaturized frequency-scanning antenna with high scanning rate. To overcome the OSB (open stopband) of traditional leaky wave antenna, CRLH-TL (Composite Right/Left-Handed-Transmission Line) is adopted. Furthermore, an antenna unit consisting of two symmetrically curved microstrip lines with two short branches is employed, whose second mode exhibits excellent transmission characteristics. The measurements demonstrate that the antenna can achieve scanning from −67.5° to 35.5° in the frequency band range of 5.65–6.5 GHz, with a scanning rate of 7.3. During scanning, the highest gain in the band is 12.3 dBi, the lowest is 10 dBi, and the gain fluctuation is within 2.3 dB, showing good scanning characteristics. Additionally, the length of the proposed antenna is approximately 3.84λ0 for a central frequency of 5.95 GHz.

Journal of Low Power Electronics and Applications doi: 10.3390/jlpea15020017

Authors: Ning Li Shubin Zhang Yanfeng Jiang

In a photovoltaic power enhancer system, when it is operated in current-control mode, significant nonuniform temperature distribution occurs in the converter due to thermal coupling effects, dissipative boundary conditions, and differences in device losses within the in-phase bridge. Accurate on-site estimation of the power device’s junction temperature is critical in the system design. To address this problem, a novel thermal behavior estimation model based on electro-thermal analysis is proposed in this paper, which can be used for asymmetric power MOSFETs in a photovoltaic power enhancer system. Thermal coupling effects and dissipative boundary conditions are, firstly, analyzed in a three-dimensional finite element model. A coupling impedance matrix is constructed through step power response extraction to describe the significant thermal coupling effects among devices. The complete heat sink is decoupled into several sub-parts representing different dissipative boundary conditions. A compact RC network model for estimating junction temperature is established based on the combination of the coupling impedance and the sub-heat-sink impedance. The proposed model is verified by finite element simulation and experimental measurement.

Journal of Low Power Electronics and Applications doi: 10.3390/jlpea15020016

Authors: Douglas Z. Plummer Emily D’Alessandro Aidan Burrowes Joshua Fleischer Alexander M. Heard Yingying Wu

The demand for computing power has been growing exponentially with the rise of artificial intelligence (AI), machine learning, and the Internet of Things (IoT). This growth requires unconventional computing primitives that prioritize energy efficiency, while also addressing the critical need for scalability. Neuromorphic computing, inspired by the biological brain, offers a transformative paradigm for addressing these challenges. This review paper provides an overview of advancements in 2D spintronics and device architectures designed for neuromorphic applications, with a focus on techniques such as spin-orbit torque, magnetic tunnel junctions, and skyrmions. Emerging van der Waals materials like CrI3, Fe3GaTe2, and graphene-based heterostructures have demonstrated unparalleled potential for integrating memory and logic at the atomic scale. This work highlights technologies with ultra-low energy consumption (0.14 fJ/operation), high switching speeds (sub-nanosecond), and scalability to sub-20 nm footprints. It covers key material innovations and the role of spintronic effects in enabling compact, energy-efficient neuromorphic systems, providing a foundation for advancing scalable, next-generation computing architectures.

Journal of Low Power Electronics and Applications doi: 10.3390/jlpea15010015

Authors: Yicheng Zhang Bojian Yin Manil Dev Gomony Henk Corporaal Carsten Trinitis Federico Corradi

Edge devices execute pre-trained Artificial Intelligence (AI) models optimized on large Graphical Processing Units (GPUs); however, they frequently require fine-tuning when deployed in the real world. This fine-tuning, referred to as edge learning, is essential for personalized tasks such as speech and gesture recognition, which often necessitate the use of recurrent neural networks (RNNs). However, training RNNs on edge devices presents major challenges due to limited memory and computing resources. In this study, we propose a system for RNN training through sequence partitioning using the Forward Propagation Through Time (FPTT) training method, thereby enabling edge learning. Our optimized hardware/software co-design for FPTT represents a novel contribution in this domain. This research demonstrates the viability of FPTT for fine-tuning real-world applications by implementing a complete computational framework for training Long Short-Term Memory (LSTM) networks utilizing FPTT. Moreover, this work incorporates the optimization and exploration of a scalable digital hardware architecture using an open-source hardware-design framework, named Chipyard and its implementation on a Field-Programmable Gate Array (FPGA) for cycle-accurate verification. The empirical results demonstrate that partitioned training on the proposed architecture enables an 8.2-fold reduction in memory usage with only a 0.2× increase in latency for small-batch sequential MNIST (S-MNIST) compared to traditional non-partitioned training.

Journal of Low Power Electronics and Applications doi: 10.3390/jlpea15010014

Authors: Antonio Manno Giuseppe Scotti Gaetano Palumbo

In this paper, a NOR2 standard-cell-based dynamic comparator providing rail-to-rail input common mode range (ICMR) is presented, together with a novel standard-cell oriented design methodology. The proposed topology provides better speed performance and lower power-delay-product than the previously presented standard-cell-based dynamic comparators with rail-to-rail ICMR features. The NOR2 topology, which is also better than the complementary NAND2-based topology previously presented by the authors, is even able to guarantee improvements in the order of 8× –16× higher speed and 7× lower PDP, with respect to the other rail-to-rail ICMR standard-cell-based topologies in the literature. Concerning the standard-cell oriented design methodology, it is focused on the impact of the cell’s strength, which is the only free parameter, on delay, power consumption, ICMR and offset. The circuit performances are demonstrated for supply voltages equal to 600 mV, 300 mV and 150 mV, considering a 45 nm CMOS technology.

Journal of Low Power Electronics and Applications doi: 10.3390/jlpea15010013

Authors: Julia Nako Costas Psychalinos Shahram Minaei

Simple designs of current-mode quadrature oscillators are presented in this work. The main achievement, with regards to the literature, is the minimization of the required transistor count accomplished by the utilization of a suitable lossless integration stage. The derived post-layout simulation results confirm the validity of the presented concept and show that the resulting structure has attractive characteristics in both frequency and time-domain.

Journal of Low Power Electronics and Applications doi: 10.3390/jlpea15010012

Authors: Pooja Srivastava Aditi Upadhyaya Shekhar Yadav Chandra Mohan Singh Negi Arvind Kumar Singh

In this work, a cylindrical gate-all-around junctionless field effect transistor (JLFET) was investigated. Junctions and doping concentration gradients are unavailable in JLFET. According to the results, the suggested device has a novel architecture that significantly enhances transistor performance while exhibiting a decreased vulnerability to short-channel effects (SCEs). The Atlas 3D device simulator has been used to analyze the proposed JLFET’s performance, especially for low-power applications for different channel lengths ranging from 10 nm to 60 nm with Al0.30Ga0.60As as III-V materials. The comparative simulated study has been based on various performance parameters, including subthreshold slope (SS), drain-induced barrier lowering (DIBL), transconductance, threshold voltage, and ION to IOFF ratio. The results of the simulations demonstrated that the III-V JLFET exhibited a favorable SS and decreased DIBL compared to other circuit topologies. In the suggested study, gallium arsenide (GaAs) and its compound materials have demonstrated a strong correlation between the SS and DIBL values. The SS is approximately 63 mV/dec, extremely near the ideal 60 mV/dec value. Gallium arsenide (GaAs) and aluminum gallium arsenide (AlGaAs) exhibit DIBL of approximately 30 mV/V and an SS value of around 64 mV/dec.

Journal of Low Power Electronics and Applications doi: 10.3390/jlpea15010011

Authors: Ashaduzzaman James M. Mangum Syed M. Rahman Tamzeed B. Amin Md R. Kabir Hung Do Gordy Carichner David Blaauw Paul M. Thibado

Powering modern nanowatt sensors from omnipresent low-level kinetic energy: This study investigates the power levels produced by a varying-capacitance kinetic energy harvesting system. A model system consisting of a uniformly driven rotating capacitor was built to develop an accurate output power performance model. We found a quantitative linear relationship between the rectified output current and the input applied bias voltage, driving frequency, and capacitance variation. We also demonstrate that our variable capacitor system is equivalent to a fixed capacitor driven with an alternating current power source. Both the fixed-capacitance and varying-capacitance energy harvesting systems recharge a three-volt battery, which in turn powers a custom ultralow-power-consuming temperature sensor system.

Journal of Low Power Electronics and Applications doi: 10.3390/jlpea15010010

Authors: Giacomo Madella Federico Tesser Lluis Alonso Julita Corbalan Daniele Cesarini Andrea Bartolini

Large-scale computing clusters have been the basis of scientific progress for several decades and have now become a commodity fuelling the AI revolution. Dark Silicon, energy efficiency, power consumption, and hot spots are no longer looming threats of an Information and Communication Technologies (ICT) niche but are today the limiting factor of the capability of the entire human society and a contributor to global carbon emissions. However, from the end user, system administrators, and system integrator perspective, handling and optimising the system for these constraints is not straightforward due to the elevated degree of fragmentation in the software tools and interfaces which handles the power management in high-performance computing (HPC) clusters. In this paper, we present the REGALE Library. It is the result of a collaborative effort in the EU EuroHPC JU REGALE project, which aims to effectively materialize the HPC PowerStack initiative, providing a single layer of communication among different power management tools, libraries, and software. The proposed framework is based on the data distribution service (DDS) and real-time publish–subscribe (RTPS) protocols and FastDDS as their implementation. This enables the various actors in the ecosystem to communicate and exchange messages without any further modification inside their implementation. In this paper, we present the blueprint, functionality tests, and performance and scalability evaluation of the DDS implementation currently used in the REGALE Library in the HPC context.

Journal of Low Power Electronics and Applications doi: 10.3390/jlpea15010009

Authors: Xian Yang Lim Boon Chiat Terence Teo Venkadasamy Navaneethan Wu Cong Lim Liter Siek

This article introduces a novel digital-to-analog converter (DAC), which addresses a few weaknesses that a traditional capacitive DAC (CDAC) has, such as matching and parasitic capacitance-induced code dependency and a challenging bridge capacitor design. Our novel idea is a hybrid DAC of a CDAC and a current-steering DAC (CSDAC) and is named the CSCDAC. In this paper, a 12-bit CSCDAC is designed, and the post-layout simulation is provided. The Nyquist 12-bit CSCDAC exhibits a spurious free dynamic range (SFDR) of 67.62 dB under an operating frequency of 2 GS/s, with an expected average power of 54 mW. The 12-bit CSCDAC occupies a 0.154 mm2 die area, whereas the core area is 0.044 mm2.

Journal of Low Power Electronics and Applications doi: 10.3390/jlpea15010008

Authors: Alberto Dequino Luca Bompani Luca Benini Francesco Conti

Transformers have emerged as the central backbone architecture for modern generative AI. However, most ML applications targeting low-power, low-cost SoCs (TinyML apps) do not employ Transformers as these models are thought to be challenging to quantize and deploy on small devices. This work proposes a methodology to reduce Transformer dimensions with an extensive pruning search. We exploit the intrinsic redundancy of these models to fit them on resource-constrained devices with a well-controlled accuracy tradeoff. We then propose an optimized library to deploy the reduced models using BFLoat16 with no accuracy loss on Commercial Off-The-Shelf (COTS) RISC-V multi-core micro-controllers, enabling the execution of these models at the extreme edge, without the need for complex and accuracy-critical quantization schemes. Our solution achieves up to 220× speedup with respect to a naïve C port of the Multi-Head Self Attention PyTorch kernel: we reduced MobileBert and TinyViT memory footprint up to ∼94% and ∼57%, respectively, and we deployed a tinyLLAMA SLM on microcontroller, achieving a throughput of 1219 tokens/s with an average power of just 57 mW.

Journal of Low Power Electronics and Applications doi: 10.3390/jlpea15010007

Authors: Riccardo Olivieri Davide Colaiuda Gianluca Barile Vincenzo Stornelli Giuseppe Ferri

This paper presents a novel transistor-level design of a modified second-generation voltage conveyor (VCII), which incorporates two differential current inputs (Y+ and Y−) and gives a voltage output at terminal X that mirrors the sum of these currents. The circuit operation is based on current mirrors that maintain the X terminal in a stable “quiescent” state when no differential current is applied at Y+ and Y−. When a current flows into one of the two inputs, the sum is mirrored into X, providing a summed current measurement. This design, developed in a standard 0.35 μm CMOS transistors technology, ensures circuit high accuracy and robustness. The low power consumption of 24.6 μW makes it well-suited for portable biomedical applications as in environmental fields.

Journal of Low Power Electronics and Applications doi: 10.3390/jlpea15010006

Authors: Martin Kenyeres Jozef Kenyeres Sepideh Hassankhani Dolatabadi

Incorrect sensor readings can cause serious problems in Wireless Sensor Networks (WSNs), potentially disrupting the operation of the entire system. As shown in the literature, they can arise from various reasons; therefore, addressing this issue has been a significant challenge for the scientific community over the past few decades. In this paper, we examine the applicability of seven distributed consensus gossip-based algorithms for sensor fusion (namely, the Randomized Gossip algorithm, the Geographic Gossip algorithm, three initial configurations of the Broadcast Gossip algorithm, the Push-Sum protocol, and the Push-Pull protocol) to compensate for incorrect data in WSNs. More specifically, we consider a scenario where the sensor-measured data (measured by a set of independent sensor nodes) are skewed due to Gaussian noise with a various standard deviation σ, resulting in discrepancies between the measured values and the true value of observed physical quantities. Subsequently, the aforementioned algorithms are employed to mitigate this skewness in order to improve the accuracy of the measured data. In this paper, WSNs are modeled as random geometric graphs with various connectivity, and the performance of the algorithms is evaluated using two metrics (specifically, the mean square error (MSE) and the number of sent messages required for an algorithm to be completed). Based on the presented results, it is identified that all the examined algorithms can significantly suppress incorrect sensor readings (MSE without sensor fusion = −0.42 dB if σ = 1, and MSE without sensor fusion = 14.05 dB if σ = 5), and the best performance is achieved by PS in dense graphs and by GG in sparse graphs (both algorithms achieve the maximum precision MSE = −24.87 dB if σ = 1 and MSE = −21.02 dB if σ = 5). Additionally, the performance of the analyzed distributed consensus gossip algorithms is compared to the best deterministic consensus algorithm applied for the same purpose.

Journal of Low Power Electronics and Applications doi: 10.3390/jlpea15010005

Authors: James S. Plank Charles P. Rizzo Chris A. White Catherine D. Schuman

The cart-pole application is a well-known control application that is often used to illustrate reinforcement learning algorithms with conventional neural networks. An implementation of the application from OpenAI Gym is ubiquitous and popular. Spiking neural networks are the basis of brain-based, or neuromorphic computing. They are attractive, especially as agents for control applications, because of their very low size, weight and power requirements. We are motivated to help researchers in neuromorphic computing to be able to compare their work with common benchmarks, and in this paper we explore using the cart-pole application as a benchmark for spiking neural networks. We propose four parameter settings that scale the application in difficulty, in particular beyond the default parameter settings which do not pose a difficult test for AI agents. We propose achievement levels for AI agents that are trained with these settings. Next, we perform an experiment that employs the benchmark and its difficulty levels to evaluate the effectiveness of eight neuroprocessor settings on success with the application. Finally, we perform a detailed examination of eight example networks from this experiment, that achieve our goals on the difficulty levels, and comment on features that enable them to be successful. Our goal is to help researchers in neuromorphic computing to utilize the cart-pole application as an effective benchmark.

Journal of Low Power Electronics and Applications doi: 10.3390/jlpea15010004

Authors: Oscar I. Alvarez-Canchila Andres Espinal Alberto Patiño-Saucedo Horacio Rostro-Gonzalez

In this paper, we propose an optimization approach using Particle Swarm Optimization (PSO) to enhance reservoir separability in Liquid State Machines (LSMs) for spatio-temporal classification in neuromorphic systems. By leveraging PSO, our method fine-tunes reservoir parameters, neuron dynamics, and connectivity patterns, maximizing separability while aligning with the resource constraints typical of neuromorphic hardware. This approach was validated in both software (NEST) and on neuromorphic hardware (SpiNNaker), demonstrating notable results in terms of accuracy and low energy consumption when using SpiNNaker. Specifically, our approach addresses two problems: Frequency Recognition (FR) with five classes and Pattern Recognition (PR) with four, eight, and twelve classes. For instance, in the Mono-objective approach running in NEST, accuracies ranged from 81.09% to 95.52% across the benchmarks under study. The Multi-objective approach outperformed the Mono-objective approach, delivering accuracies ranging from 90.23% to 98.77%, demonstrating its superior scalability for LSM implementations. On the SpiNNaker platform, the mono-objective approach achieved accuracies ranging from 86.20% to 97.70% across the same benchmarks, with the Multi-objective approach further improving accuracies, ranging from 94.42% to 99.52%. These results show that, in addition to slight accuracy improvements, hardware-based implementations offer superior energy efficiency with a lower execution time. For example, SpiNNaker operates at around 1–5 watts per chip, while traditional systems can require 50–100 watts for similar tasks, highlighting the significant energy savings of neuromorphic hardware. These results underscore the scalability and effectiveness of PSO-optimized LSMs on resource-limited neuromorphic platforms, showcasing both improved classification performance and the advantages of energy-efficient processing.

Journal of Low Power Electronics and Applications doi: 10.3390/jlpea15010003

Authors: Shanthala Lakshminarayana Revathy Perumalsamy Chenyun Pan Sungyong Jung Hoon-Ju Chung Hyusim Park

This work presents a potentiometric readout circuit for a pH-sensing system in an oral healthcare device. For in vivo applications, noise, area, and power consumption of the readout electronics play critical roles. While CMOS amplifiers are commonly used in readout circuits for these applications, their applicability is limited due to non-deterministic noises such as flicker and thermal noise. To address these challenges, the Correlated Double Sampler (CDS) topology is widely employed as a sampled-data circuit for potentiometric readout, effectively eliminating DC offset and drift, thereby reducing overall noise. Therefore, this work introduces a novel potentiometric readout circuit realized with CDS and a switched-capacitor-based low-pass filter (SC-LPF) to enhance the noise characteristic of overall circuit. The proposed readout circuit is implemented in an integrated circuit using 0.18 µm CMOS process, which occupies an area of 990 µm × 216 µm. To validate the circuit performances, simulations were conducted with a 5 pF load and a 1 MHz input clock. The readout circuit operates with a supply voltage range ±1.65 V and linearly reproduces the pH sensor output of ±1.5 V. Noise measured with a 1 MHz sampling clock shows 0.683 µVrms, with a power consumption of 124.1 µW.