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6 Results Found

  • Article
  • Open Access
1,963 Views
22 Pages

23 February 2025

The digital integrated circuit (IC) design industry is continuously evolving. However, the rapid advancements in technology are accompanied by major reliability concerns. Conventional clock-based synchronous designs become exceedingly susceptible to...

(This article belongs to the Section Circuit and Signal Processing)
  • Article
  • Open Access
4 Citations
4,219 Views
24 Pages

The increasing demand for high-speed, energy-efficient, and miniaturized electronics has led to significant challenges and compromises in the domain of conventional clock-based digital designs, most notably reduced circuit reliability, particularly i...

  • Article
  • Open Access
3 Citations
7,819 Views
8 Pages

A 50.5 ns Wake-Up-Latency 11.2 pJ/Inst Asynchronous Wake-Up Controller in FDSOI 28 nm

  • Jean-Frédéric Christmann,
  • Florent Berthier,
  • David Coriat,
  • Ivan Miro-Panades and ,
  • Eric Guthmuller,
  • Sébastien Thuries,
  • Yvain Thonnart,
  • Adam Makosiej,
  • Olivier Debicki and
  • Edith Beigné
  • + 8 authors+ 3 authors

Due to low activity in Internet of Things (IoT) applications, systems tend to leverage low power modes in order to reduce their power consumption. Normally-off computing thus arose, consisting in having turned off most part of a system’s power...

  • Article
  • Open Access
1 Citations
2,164 Views
22 Pages

Monotonic Asynchronous Two-Bit Full Adder

  • Padmanabhan Balasubramanian and
  • Douglas L. Maskell

Monotonic circuits are a class of input–output mode (IOM) asynchronous circuits that are relaxed compared to quasi-delay-insensitive (QDI) IOM asynchronous circuits in terms of signaling the completion of internal processing. Some recent works...

(This article belongs to the Special Issue Design of Mixed Analog/Digital Circuits, Volume 2)
  • Article
  • Open Access
4 Citations
3,966 Views
25 Pages

Quasi Delay Insensitive Majority Voters for Triple Modular Redundancy Applications

  • Padmanabhan Balasubramanian,
  • Douglas L. Maskell and
  • Nikos E. Mastorakis

10 December 2019

Mission- and safety-critical applications tend to incorporate triple modular redundancy (TMR) in their hardware implementation to reliably withstand the fault or failure of any one of the function modules during normal operation, and the function mod...

(This article belongs to the Section Electrical, Electronics and Communications Engineering)
  • Article
  • Open Access

13 November 2026

This paper presents a multi-core asynchronous AES-128 encryption architecture designed for ultra-high-throughput applications. The proposed design uses quasi-delay-insensitive (QDI) dual-rail logic and a four-phase return-to-zero handshake protocol,...

(This article belongs to the Special Issue New Research in Microelectronics and Electronics)