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Fabrication, Reliability, Simulation, and Protection of Advanced Semiconductor Devices and Integrated Circuits: Enabled by Emerging Semiconductor Materials

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A special issue of Micromachines (ISSN 2072-666X). This special issue belongs to the section "D1: Semiconductor Devices".

Deadline for manuscript submissions: 30 September 2026 | Viewed by 2378

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Dr. Xiyuan Feng

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Guest Editor

School of Microelectronics, Northwestern Polytechnical University, Xi'an 710071, China
Interests: synergy between semiconductor device innovation; on-chip ESD protection techniques; TCAD-assisted device simulation; advanced ADC circuit design
Special Issues, Collections and Topics in MDPI journals

Dr. Yunlei Zhong

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Guest Editor

Key Laboratory of Multifunctional Nanomaterials and Smart Systems, Division of Advanced Materials, Suzhou Institute of Nano-Tech and Nano-Bionics, Chinese Academy of Sciences, Suzhou 215123, China
Interests: novel condensed matter properties of low dimensional materials; optoelectronic devices; catalysis; energy storage
Special Issues, Collections and Topics in MDPI journals

Special Issue Information

Dear Colleagues,

This Special Issue addresses the critical intersection of emerging semiconductor materials with the full lifecycle of advanced semiconductor devices and integrated circuits (ICs)—from fabrication to long-term operational robustness. As Moore’s Law confronts physical scaling limits, materials like gallium nitride (GaN), silicon carbide (SiC) and two-dimensional (2D) materials (e.g., MoS₂, graphene) have emerged as game-changers, enabling higher efficiency, faster switching and novel functionalities. However, their integration introduces unprecedented challenges: non-ideal interfaces during fabrication, defect-mediated degradation under stress and complex multi-physics couplings that defy conventional reliability models.

We focus on bridging material innovation to practical deployment by exploring (1) advanced fabrication techniques tailored to emerging materials; (2) physics-based simulation tools to predict device lifetime and failure modes; and (3) protective strategies (e.g., passivation, thermal management) to mitigate material-specific vulnerabilities. Contributions span experimental characterization, computational modeling and case studies on power electronics, neuromorphic systems and beyond. This issue aims to foster cross-disciplinary collaboration, establishing a framework for ensuring trustworthiness in next-generation semiconductors and accelerating their industrial adoption.

Dr. Xiyuan Feng
Dr. Yunlei Zhong
Guest Editors

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Keywords

emerging semiconductor materials
advanced semiconductor devices
integrated circuits (ICs)
fabrication processes
reliability engineering
multi-physics simulation
device protection strategies
wide-bandgap semiconductors (WBG)
two-dimensional materials

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Published Papers (7 papers)

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Research

12 pages, 2055 KB

Open AccessArticle

A Low-Stray-Inductance 1200 V/500 A SiC Power Module Based on Multilayer Insulated Metal Substrate

by Youyuan Yue, Liming Che, Cancan Li and Guangyin Lei

Micromachines 2026, 17(5), 602; https://doi.org/10.3390/mi17050602 (registering DOI) - 14 May 2026

Abstract

With the growing need for high-power density, high-efficiency power electronics, wide band gap (WBG) semiconductors, such as silicon carbide (SiC) and gallium nitride (GaN), have been widely used in recent years. With high switching speed, stray inductance induced by packaging would cause voltage overshooting and oscillation during the switching transient, which should be mitigated at all costs. In this paper, a power module design based on a multilayer insulated metal substrate (MIMS) structure was proposed to effectively address the stray inductance concern based on the mutual-inductance cancelling effect. Fabrication process flow with high feasibility was also designed. Electrical and thermal simulations were conducted based on a power module with a nominal rating of 1200 V and 500 A. Compared to the planar module, the proposed design possessed much lower stray inductance (3.47 nH vs. 14.85 nH). In the transient thermal simulation, the proposed module exhibited a time constant 141.7% higher than that of the hybrid module with a ceramic substrate on the bottom but MIMS on the top, making it suitable for applications with high-constant power output requirements. Full article

(This article belongs to the Special Issue Fabrication, Reliability, Simulation, and Protection of Advanced Semiconductor Devices and Integrated Circuits: Enabled by Emerging Semiconductor Materials)

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15 pages, 10796 KB

Open AccessArticle

Ni-Doped SnO₂ Gas Sensor Array Enabled High-Randomness PUF for Hardware Security Applications

by Zexin Ji, Xiaowei Zhang, Zhanbo Chen, Shanshan Wang, Wenbo Zhang, Hao Ye and Xiangyu Li

Micromachines 2026, 17(5), 597; https://doi.org/10.3390/mi17050597 (registering DOI) - 14 May 2026

Abstract

With the growing security requirements of sensor nodes in Internet of Things (IoT) systems, conventional silicon-circuit-based physical unclonable functions (PUFs) still face limitations in circuit overhead, design complexity, and system integration. To address these challenges, this paper proposes a lightweight gas sensor PUF (GS-PUF) design based on a Ni-doped SnO₂ nanoscale gas sensor array. The proposed method exploits both the unavoidable process randomness introduced during sensor fabrication and the device-to-device electrical response variations induced by gas–material interactions as entropy sources, thereby enabling high-quality PUF response generation. At the device level, Ni-SnO₂ nanomaterials are prepared by electrostatic spray deposition (ESD), and an indirectly heated gas sensor array is constructed to enhance the sensitivity and stability of the sensing response. At the algorithmic level, a random resistance balancing algorithm based on multi-sensor combinational comparison is proposed. By randomly comparing the summed resistances of multiple sensor clusters, a 128-bit multi-bit PUF response is generated, while the uniformity and independence of the output bits are effectively improved. Experimental results demonstrate that the proposed GS-PUF exhibits excellent randomness, uniqueness, and reliability: the information entropy of the PUF responses is greater than 0.99, approaching the ideal value; the probabilities of output bits “1” and “0” are 0.4988 and 0.5012, respectively, indicating a well-balanced distribution; the inter-device uniqueness reaches 49.8%, close to the ideal value of 50%; all items in the NIST randomness test suite are passed, with all p-values exceeding 0.01 and the minimum p-value being 0.0368, confirming a high level of statistical randomness confidence. In addition, long-term measurements under fixed laboratory conditions show that the PUF response reliability remains above 96%. Compared with other sensor-based PUFs, the proposed method provides a lightweight sensing-security integration approach for IoT sensor nodes by reusing intrinsic gas-sensor response variations and avoiding an additional dedicated silicon PUF circuit. Full article

(This article belongs to the Special Issue Fabrication, Reliability, Simulation, and Protection of Advanced Semiconductor Devices and Integrated Circuits: Enabled by Emerging Semiconductor Materials)

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11 pages, 3347 KB

Open AccessArticle

Rational Confinement of NiMo₆ Polyoxometalates in a Single-Walled Carbon Nanotube: A High-Filling-Ratio Strategy for Enhanced Electrochemical Activity

by Kai Zhang, Zeling Yang, Chengxu Zhou, Xinwang Cao and Xiyuan Feng

Micromachines 2026, 17(5), 583; https://doi.org/10.3390/mi17050583 - 7 May 2026

Viewed by 235

Abstract

This study successfully developed an efficient one-dimensional confinement strategy to encapsulate polyoxometalate NiMo₆ clusters densely and uniformly within the cavities of a single-walled carbon nanotube (SWCNT), constructing a unique core–shell NiMo₆@SWCNT composite electrocatalyst. Comprehensive characterization including high-resolution transmission electron microscopy (HRTEM), energy-dispersive X-ray spectroscopy (EDS), X-ray diffraction (XRD), X-ray photoelectron spectroscopy (XPS), Raman spectroscopy, Fourier transform infrared spectroscopy (FTIR), and ultraviolet-visible absorption spectroscopy (UV-Vis) systematically confirmed the uniform dispersion and structural integrity of NiMo₆ within the SWCNT channels. Key evidence encompasses: (1) EDS elemental mapping revealing high co-localization of Ni/Mo signals inside the lumens; (2) transmission electron microscopy (TEM) images confirming the effectiveness of the filling process. The composite achieved an exceptionally low overpotential of 308 mV to drive a current density of 10 mA cm⁻² (significantly outperforming pure NiMo₆ at 365 mV and pristine SWCNT at 519 mV), exhibited a remarkably low Tafel slope of 96.64 mV dec⁻¹, possessed a high electrochemical active surface area (10.75 mF cm⁻²), and very low charge transfer resistance. Critically, it showed negligible current density decay during prolonged chronoamperometric operation over 35,000 s (>9.7 h). This work not only validates the confined encapsulation as a viable strategy for fabricating highly active polyoxometalate/carbon composites, but also elucidates that the performance enhancement stems from a “triple synergy”: the intrinsic catalytic activity of NiMo₆, the highly conductive/mass-transport network provided by SWCNT, and the synergistic effects arising from the confined interface—namely stress regulation and electronic coupling. This insight provides a novel perspective for designing high-performance non-precious metal electrocatalysts. Full article

(This article belongs to the Special Issue Fabrication, Reliability, Simulation, and Protection of Advanced Semiconductor Devices and Integrated Circuits: Enabled by Emerging Semiconductor Materials)

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18 pages, 8134 KB

Open AccessArticle

Numerical Investigation of Short-Channel Effects and RF Performance in Top-Gate In₂O₃ Thin-Film Transistors

by Hanbo Xu, Mingyang Zhu, Zeen Fang and Lei Zhang

Micromachines 2026, 17(5), 567; https://doi.org/10.3390/mi17050567 - 2 May 2026

Viewed by 403

Abstract

Indium oxide (In₂O₃) has recently emerged as a promising semiconductor for advanced electronics due to its high electron mobility and wide bandgap. In this article, the lateral scaling characteristics of top-gate In₂O₃ thin-film transistors (TFTs) featuring a 1.5 nm thick channel and a 7 nm thick HfO₂ gate dielectric are investigated by two-dimensional device simulation. The analysis covers short-channel effects, DC characteristics, transconductance behavior, and small-signal radio frequency (RF) metrics across a gate-length (L_G) range of 20 nm to 700 nm. Simulation results identify a critical gate length near 100 nm for the transition from long-channel to short-channel behavior. For L_G ≤ 100 nm, pronounced short-channel effects emerge, featuring a significant negative V_TH shift and a drain-induced barrier lowering (DIBL) coefficient up to ~130 mV/V. A non-classical gm scaling behavior is observed, where g_m_{_max} initially increases with L_G, then remains within a narrow range and eventually evolves toward the conventional long-channel trend. Further analysis of the lateral electric field distribution, field-dependent mobility, and transconductance efficiency indicates that this behavior originates from a crossover between short-channel field-assisted transport and gate-controlled channel modulation. The devices show strong RF potential, with f_T and f_max reaching 124.32 GHz and 157.64 GHz, respectively, at L_G = 20 nm. The high-mobility In₂O₃ channel leads to a less distinct f_T scaling transition from the classical 1/L²_G dependence to the short-channel 1/L_G dependence, while f_max scaling evolves through different regimes governed by capacitance-related limitations, intrinsic transport enhancement, and short-channel non-idealities. This work provides physical insight into the lateral scaling behavior of ultrathin top-gate In₂O₃ TFTs and highlights their potential for high-frequency and power-dense applications. Full article

(This article belongs to the Special Issue Fabrication, Reliability, Simulation, and Protection of Advanced Semiconductor Devices and Integrated Circuits: Enabled by Emerging Semiconductor Materials)

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26 pages, 9499 KB

Open AccessArticle

SpChipADF: An Architecture Design Framework for Radar Signal Processing Hardware Accelerators

by Huan Wang, Shu Yang, Zhen Chen, Haoyu Sun, Yang Shen, Hang Li, Zhiyu Jiang, Yanlei Li and Xingdong Liang

Micromachines 2026, 17(5), 535; https://doi.org/10.3390/mi17050535 - 27 Apr 2026

Viewed by 220

Abstract

Lightweight Unmanned Aerial Vehicles (UAVs) have limited space, low payload capacity, and constrained power supply capabilities. Therefore, their payloads are constrained by size, weight, and power (SWaP). Thus, designing edge-side signal processing architectures for the payloads of UAVs faces severe challenges. Traditional ASIC design based on manual optimization struggles to meet the demands of low latency and low resource occupancy in edge-side applications. To address this challenge, this paper proposes a signal processing hardware accelerator architecture design framework with algorithm-hardware co-design. The framework employs a cross-level dataflow graph representation to formally capture task characteristics. Reconfigurable dataflow templates and reusable operator IP components are systematically constructed based on this representation. Through multi-objective design space exploration, the framework achieves Pareto-optimal mapping from algorithmic specifications to hardware implementations. Finally, automatic generation of top-level hardware descriptions enables rapid FPGA-based prototyping and functional validation. Taking synthetic aperture radar (SAR) imaging as a study example, compared with non-reconfigurable architectures, this scheme reduces the equivalent gate count by 51.4% without increasing processing latency. Compared with a conventional reconfigurable dataflow architecture, the design improves energy efficiency from 12.8 MS/J to 16.0 MS/J, representing a 25.4% enhancement, while also scaling the supported data processing size by a factor of 4×. It provides a high-performance and scalable hardware acceleration solution for lightweight edge-side computing platforms. Full article

(This article belongs to the Special Issue Fabrication, Reliability, Simulation, and Protection of Advanced Semiconductor Devices and Integrated Circuits: Enabled by Emerging Semiconductor Materials)

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24 pages, 4307 KB

Open AccessArticle

Stochastic Neuromorphic Computing Architecture Based on Voltage-Controlled Probabilistic Switching Magnetic Tunnel Junction (MTJ) Devices

by Liang Gao, Chenxi Wang and Yanfeng Jiang

Micromachines 2026, 17(2), 216; https://doi.org/10.3390/mi17020216 - 5 Feb 2026

Viewed by 694

Abstract

As integrated circuits face increasingly stringent demands regarding power consumption, area, and stability, integrating novel spintronic devices with computing architectures has become a crucial direction for breaking through traditional computing paradigms. In the paper, switching mechanism of Magnetic Tunnel Junctions (MTJs) under the synergistic effect of Voltage-Controlled Magnetic Anisotropy (VCMA) and the Spin Hall Effect (SHE) is investigated. VCMA-assisted switching SHE-MTJ device is adopted, and a macrospin approximation model is established based on the Landau-Lifshitz-Gilbert (LLG) equation to systematically analyze its dynamic characteristics. The research demonstrates that applying VCMA voltage pulses with appropriate amplitude and width can significantly reduce the required spin Hall current density and pulse width for switching, thereby effectively minimizing ohmic losses and Joule heating. Furthermore, by incorporating a thermal fluctuation field, voltage-controlled SHE-MTJ device with stochastic switching behavior can be constructed, obtaining an approximately sigmoidal voltage-probability response curve. This provides an ideal physical foundation for stochastic computing and neuromorphic computing. Based on the above established fundamental discovery, an in-memory computing architecture supporting binarized Convolutional Neural Networks (CNNs) is proposed and designed in the paper. Combined with the lightweight network SqueezeNet, this architecture achieves a Top-1 recognition accuracy of 72.49% on the CIFAR-10 dataset, with a parameter count of only 1.25 × 10⁶. This work offers a feasible spintronic implementation scheme for low-power, high-energy-efficiency edge-side intelligent chips. Full article

(This article belongs to the Special Issue Fabrication, Reliability, Simulation, and Protection of Advanced Semiconductor Devices and Integrated Circuits: Enabled by Emerging Semiconductor Materials)

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12 pages, 1833 KB

Open AccessArticle

Radiation-Induced Degradation of a Cold-Redundant DC/DC Converter Under Total Ionizing Dose Stress

by Xiaojin Lu, Zhujun Xi, Qifeng He, Ziyu Zhou, Mengyao Li, Liangyu Xia and Gang Dong

Micromachines 2026, 17(2), 197; https://doi.org/10.3390/mi17020197 - 31 Jan 2026

Viewed by 415

Abstract

This paper investigates the degradation characteristics of a DC/DC converter operating under cold redundancy conditions when subjected to total ionizing dose (TID) effects. An optimized RCC isolated auxiliary power supply circuit was evaluated through ⁶⁰Co γ-ray irradiation up to 100 krad(Si) at dose rates of 3.89, 8.89, and 13.89 rad (Si)/s, with electrical characterizations performed at both the system level and the device level, focusing on the critical VDMOS transistors. The results indicate that the main output voltage and conversion efficiency remain essentially stable after irradiation, whereas the auxiliary supply voltage and efficiency degrade significantly, leading to a pronounced reduction in the controller supply margin. Device-level measurements reveal a negative threshold voltage shift of approximately 0.5–1.0 V with clear dose-rate dependence, while the subthreshold swing shows no obvious variation, suggesting that the degradation is primarily dominated by oxide-trapped charge effects. In addition, a substantial increase in drain current at low gate voltages is observed, which may further exacerbate restart risks under cold redundancy conditions. These findings demonstrate that the auxiliary power supply and startup margin constitute critical vulnerability points of cold-redundant DC/DC converters under TID stress and should therefore be primary targets for radiation-hardened design. Full article

(This article belongs to the Special Issue Fabrication, Reliability, Simulation, and Protection of Advanced Semiconductor Devices and Integrated Circuits: Enabled by Emerging Semiconductor Materials)

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