Chips

Sorting networks are of prime importance as circuits, with applications in sorting small data chunks, big data analytics, permuting packets, and system interconnects. Finding optimal sorting networks is a highly complex problem, and knowledge on optimal sorting networks is limited. When optimising the network depth or the number of comparators, one of the most expensive tasks is considered to be verification, that is, to verify that the candidate compare-and-swap network actually sorts the data. This grows exponentially with the size of the sorting network. However, FPGAs allow vast amounts of internal parallelism, and our presented work exploits this flexibility using dataflow techniques to achieve unparalleled amounts of speedup for sorting network verification. This work can be used in a modular way to accelerate the search for optimal sorting networks with a high number of inputs, as well for similar verification problems. Full article

Power converters based on gallium nitride (GaN) are progressing swiftly owing to their exceptional efficiency and tiny dimensions, boosted by high power density and fast switching capabilities. Nevertheless, these benefits are accompanied by considerable thermal management issues that impact reliability, performance, and operational lifespan. This review examines advanced thermal management approaches for high-power-density GaN power converters, including active and passive cooling technologies, sophisticated packaging designs, and the use of novel materials like graphene and diamond to improve heat dissipation. The impacts of thermal boundary resistance, self-heating phenomena, and substrate selection on thermal performance are thoroughly analyzed. Strategies for enhancing printed circuit board (PCB) layouts, thermal vias, and the use of thermal interface materials (TIMs) are also emphasized. The study highlights co-design approaches that optimize thermal resistance and layout efficiency, supporting GaN operation under high-frequency conditions. This thorough investigation offers insights into addressing the thermal challenges linked to GaN technology, promoting its adoption in forthcoming power devices. Full article

Neuromorphic computing, an interdisciplinary field combining neuroscience and computer science, aims to create efficient, bio-inspired systems. Different from von Neumann architectures, neuromorphic systems integrate memory and processing units to enable parallel, event-driven computation. By simulating the behavior of biological neurons and networks, these systems excel in tasks like pattern recognition, perception, and decision-making. Neuromorphic computing chips, which operate similarly to the human brain, offer significant potential for enhancing the performance and energy efficiency of bio-inspired algorithms. This review introduces a novel five-dimensional comparative framework—process technology, scale, power consumption, neuronal models, and architectural features—that systematically categorizes and contrasts neuromorphic implementations beyond existing surveys. We analyze notable neuromorphic chips, such as BrainScaleS, SpiNNaker, TrueNorth, and Loihi, comparing their scale, power consumption, and computational models. The paper also explores the applications of neuromorphic computing chips in artificial intelligence (AI), robotics, neuroscience, and adaptive control systems, while facing challenges related to hardware limitations, algorithms, and system scalability and integration. Full article

Semiconductor technologies are susceptible to radiation effects. The particle incidence in susceptible areas of an integrated circuit (IC) can generate physical interactions capable of producing errors. This paper predicts the IC cross sections for Single Event Effects. The cross section is a metric that provides an IC’s susceptibility to radiation. It deals with particle source interaction and physical design volumes. This work evaluates the IC cross section, exploring the physical design characteristics of susceptible regions in logic gates. It explores particles with low LET, identifying the charge collection areas. Also, the heavy ions are used to evaluate the critical cross section range. Distinct benchmark circuits were simulated to characterize sensitivity trends. The influence of circuit input conditions along with cells’ susceptibility reveals significant findings. The results indicate a difference up to ten times between low- and high-energy particles. Consequently, predicting the IC cross section at an early stage of the design flow is essential, especially for electronics devices used in radiation environments. Full article

This work presents an advanced electro-physical model for hydrogenated amorphous silicon (a-Si:H) Junction Field Effect Transistors (JFETs) to enable the design of devices with energy-efficient analog interface building blocks for Lab-on-Chip (LoC) systems. The presence of this device can support monolithic integration with thin-film sensors and circuit-level design through a validated compact formulation. The model accurately describes the behavior of a-Si:H JFETs addressing key physical phenomena, such as the channel thickness dependence on the gate-source voltage when the channel approaches full depletion. A comprehensive framework was developed, integrating experimental data and mathematical refinements to ensure robust predictions of JFET performance across operating regimes, including the transition toward full depletion and the associated current-limiting behavior. The model was validated through a broad set of fabricated devices, demonstrating excellent agreement with experimental data in both the linear and saturation regions. Specifically, the validation was carried out at 25 °C on 15 fabricated JFET configurations (12 nominally identical devices per configuration), using the mean characteristics of 9 devices with standard-deviation error bars. In the investigated bias range, the devices operate in a sub-µA regime (up to several hundred nA), which naturally supports µW-level dissipation for low-power interfaces. This work provides a compact, experimentally validated modeling basis for the design and optimization of a-Si:H JFET-based LoC front-end/readout circuits within technology-constrained and energy-efficient operating conditions. Full article

In this study, we present the design and analysis of a stacked inverter-based millimeter-wave (mmWave) power amplifier (PA) in 90 nm CMOS-targeting wideband Q-band operation. The PA employs two PMOS and two NMOS devices in a fully stacked inverter topology to distribute device stress, remove the need for an RF choke, and increase effective transconductance while preserving compact layout. A resistor ladder biases the stack near $V_{\mathrm{DD}}/4$ per device, and capacitive division steers intermediate-node swings to enable class-E-like voltage shaping at the output. Closed-form models are developed for gain, output power, drain efficiency/PAE, and linearity, alongside a small-signal stacked-ladder formulation that quantifies stress sharing and the impedance presented to the matching networks; L/T network synthesis relations are provided to co-optimize bandwidth and insertion loss. Post-layout simulation in 90 nm CMOS shows $|S_{21}|$ = 10 dB at 39.84 GHz with 3 dB bandwidth from 36.8 to 42.4 GHz, peak PAE of 18.38% near 41 GHz, and saturated output power $P_{\mathrm{sat}}=8.67$ dBm at $V_{\mathrm{DD}}=4$ V, with $S_{11}<-15$ dB and reverse isolation $\approx -16$ dB. The layout occupies $1.6\times 1.6$ mm² and draws 31.08 mW. Robustness is validated via a 200-run Monte Carlo showing tight clustering of $P_{\mathrm{sat}}$ and PAE, sensitivity sweeps identifying sizing/tolerance trade-offs ($\pm 10\%$ devices/passives), and EM co-simulation of on-chip passives indicating only minor loss/shift relative to schematic while preserving the target bandwidth and efficiency. The results demonstrate a balanced gain–efficiency–power trade-off with layout-aware resilience, positioning stacked-inverter CMOS PAs as a power- and area-efficient solution for mmWave front-ends. Full article

Test time per chip plays an essential role in manufacturing tests. Keeping a low number of test patterns becomes one of the prime objectives in concurrence with achieving the desired fault coverage. Unfortunately, finding an optimum set is an NP-hard problem. Today’s commercial ATPG tools have significantly reduced the number of test patterns to achieve a high fault coverage. However, there is still a huge gap for reducing the total pattern count, equivalent to minimizing test costs in the production phase. In this paper, we propose two novel methods to lower the test pattern count to detect all stuck-at faults in a circuit with the same or higher fault coverage as in the commercial ATPG tool, e.g., TetraMAX II. The first approach begins by applying a small set of random patterns to solve easy-to-detect faults. The remaining faults are detected by the SAT-based attack on logic locking with converting all the remaining faults into one locked circuit. Each stuck-at fault is modeled with its equivalent key gate. The second approach selects the first few patterns generated by the ATPG tool and applies the SAT attack of logic locking to determine the test patterns for detecting the undetected faults. By exploiting the overall linear iteration complexity and the exponential removal of incorrect key combinations per each SAT attack iteration, it is feasible to significantly reduce the total pattern count while maintaining the same or higher fault coverage as the ATPG counterpart. We demonstrate the effectiveness of both approaches and show that we are able to achieve a more compact test pattern set compared to a commercial ATPG tool. Full article

This paper presents the design of a 140 GHz vector-sum phase shifter in a 28 nm CMOS process. Two variable-gain amplifiers—Gilbert cell and current-steering amplifiers—are investigated and compared. The Gilbert cell-based phase shifter controls the tail current source in a common-source amplifier. However, this configuration exhibits insufficient gain at D-band frequencies. To address this issue, we designed a current-steering variable-gain amplifier in cascode form to improve the gain performance. I/Q signals are generated by Marchand baluns and Lange couplers, and a 13-bit digital-to-analog converter enables fine bias control. Simulation results show that the current-steering phase shifter achieves up to a 4.4 dB higher gain than the Gilbert cell-based phase shifter, with an RMS gain error below 1.3 dB and an RMS phase error below 4.8° across 129–144 GHz. Full article

This paper proposes a novel fault-tolerant routing method without creating faulty regions for 3D mesh Network-on-Chips (NoCs). Most conventional methods create faulty regions containing faulty nodes and route packets around them to reach the destinations. However, the creation of faulty regions results in low communication performance and low node utilization. To overcome the two problems, the proposed method does not create faulty regions based on the idea of predefining paths in the absence of shortest paths while allowing the passage of faulty nodes. Simulation results show that, compared with conventional methods, the proposed method reduces average latency by about 44.5% and improves node utilization rate by about 41.2% for 3D mesh NoCs of $5\times 5\times 5$ nodes. Full article

Silicon-Based Physical Unclonable Functions (PUFs) exploit inherent manufacturing variations to produce a unique, random, and ideally unclonable secret key. As electronic devices are decommissioned and sent for End of Life (EOL) recycling, the encrypted critical program information remains within the device. However, conventional PUFs remain vulnerable to invasive attacks and reverse engineering that with sufficient time, resources, and effort can enable an adversary to bypass the security enclave of the system and extract this secret data. Recent research has started to explore techniques to respond to tamper attempts using electromigration (EM) and time-dependent dielectric breakdown (TDDB) to the PUF entropy source, preventing future authentication attempts with well-known semiconductor reliability failure mechanisms. This work presents a Pre-Amplifier Physical Unclonable Function (Pre-Amp PUF) with a self-corruption function designed and manufactured in a 3 nm FinFET technology. This PUF can perform a destructive read operation as an EOL anti-counterfeit measure against recycled and reused electronics. The destructive read utilizes an accelerated aging technique that exploits both Hot Carrier Injection (HCI) and Bias Temperature Instability (BTI) degradations directly at the PUF entropy source bitcell data. This work demonstrates a silicon proven ability to irreversibly corrupt the encryption key, invalidating the PUF key, and blocking future authentication attempts. By utilizing HCI and BTI aging effects rather than physical damage a PUF that can self-corrupt its own key without being detectable with imaging techniques is demonstrated for the first time. A feedback loop enables corruption of up to ~30% of the PUF entropy source, which is approximately 3× more data corruption than the prior state of the art self-corrupting PUF. Our technique reuses on-chip stable (repeatable) PUF bitcells identifying circuitry and thereby minimizes the area overhead to support this differentiated feature. Full article

Cyber physical systems (CPSs) increasingly depend on complex hardware IP cores to perform critical functions. However, triggered hardware Trojans’ stealthy, malicious modifications activated under rare conditions pose significant threats to the safety and reliability of these systems. This research paper introduces a novel detection framework that integrates multi-modal side-channel analysis with trigger-aware machine learning to identify Trojans embedded within IP cores. A lightweight runtime monitoring mechanism enables real-time Trojan detection while adhering to the stringent safety constraints of CPSs. To further strengthen resilience, cryptographic integrity verification and dynamic mitigation through partial reconfiguration are incorporated. Experimental validation on two representative IP cores, AES-128 and RS232, demonstrates the framework’s effectiveness by achieving high detection accuracy (over 96%) with minimal hardware overhead (<3% LUT utilization) and latency increase of 4.95%. It can also be seen that our trigger-aware methodology more than doubles the toggling probability of rare Trojan trigger nets compared to conventional approaches. Furthermore, results from FPGA prototypes and standard Trojan benchmarks confirm the effectiveness of the proposed framework, and the proposed approach achieves high detection accuracy with minimal resource and performance penalties. This work advances the state of the art in securing CPS hardware against Trojan-based attacks. Full article

This work presents a wideband variable gain low-noise amplifier (VGA-LNA) specifically engineered for medical systems operating in the C frequency band, which require the substantial amplification of low-intensity signals. The proposed design integrates a low-noise attenuator with a low-noise amplifier (LNA), fabricated using 90 nm CMOS technology and leveraging a combined common-source and common-gate topology. The integrated LNA achieved a notable power gain of 29 dB across a broad bandwidth of 2 GHz (6.4–8.4 GHz), maintaining an average noise figure (NF) below 3.14 dB. The design ensures superior impedance matching, demonstrated by reflection coefficients of S11 < −18.14 dB and S22 < −20.23 dB. Additionally, the amplifier exhibits a third-order input intercept point (IIP3) of 21.15 dBm while consuming only 83 mW from a 1.2 V supply voltage. A low-noise attenuator was incorporated at the input side to enable effective gain control through a digitally controlled variable gain, with step sizes ranging from 0.4 to 3.3 dB. This configuration enables a dynamic range of the transmission coefficient (|S₂₁|) from 16 dB to 23 dB, adjustable by 0.4 dB to 3.3 dB with a trade-off in an NF maintained at 6 dB. The VGA-LNA demonstrates exceptional potential for integration into wireless body area networks (WBANs), balancing flexible gain control with stringent performance metrics. Full article

Schmitt Triggers are essential building blocks in noise-resilient systems and are useful in managing switching behavior in low-power designs. Yet, as CMOS technologies scale down, their designs become increasingly challenging. This paper presents a comprehensive investigation into the performance and reliability of multiple Schmitt Trigger topologies across two CMOS technology nodes (180 nm and 45 nm), with a particular focus on transistor sizing and layout optimization through multi-finger transistor structures. A series of pre-layout and post-layout simulations reveal that fingered implementations significantly enhance hysteresis robustness, switching speed, and delay consistency in PVT variations. Notably, post-layout results in 45 nm technology demonstrate remarkable improvements in both speed and power efficiency. This highlights the inadequacy of schematic-level models to predict the true behavior of fingered transistor configurations. Additionally, we explored the implications of finger designs on reliability concerns including electromigration and IR drop to determine the tradeoff between interconnect reliability optimization and internal routing. The findings establish practical design guidelines for optimizing number of fingers based on device width and technology node, offering new insights into layout-aware Schmitt Trigger design for high-performance and area-constrained applications. Full article

Every element of our contemporary lives has changed as a result of the widespread use of computing infrastructure and information technology in daily life. Less focus has been placed on the hardware components that underpin the computing revolution, despite the fact that its effects on software applications have been the most obvious. The computer chip is the most basic component of computer hardware and powers all digital devices. Every gadget, including mainframes, laptops, cellphones, tablets, desktop PCs, and supercomputers, is powered by different computer chips. Although there are many different types of these chips, the biggest producers in this field are AMD (Advanced Micro Devices), Intel, and ARM (Advanced RISC Machines). These companies make processors for both consumer and business markets. Users have compared their products based on a number of factors, including pricing, cache and memory, approaches, etc. This paper provides a comprehensive comparative analysis of Intel, AMD, and ARM processors, focusing on their architectural characteristics and performance within the context of burgeoning artificial intelligence applications. The detailed architectural features, performance evaluation for AI workloads, a comparison of power efficiency and cost, and analysis for current market trends are presented. By thoroughly examining core architectural elements and key performance factors, this work provides valuable insights for users and developers to seek optimal processor choices to maximize AI tool utilization in the contemporary era. Full article

Quantum-dot Cellular Automata (QCA) technology has emerged as a promising approach for constructing nanoscale digital circuits, offering notable advantages such as minimal power consumption, rapid processing speeds, and highly compact layouts. Traditional CMOS technology faces significant challenges at the nanoscale, including reduced gate control and increased current leakage. QCA, on the other hand, provides a robust platform for building next-generation digital systems. In this study, a unique single-layer QCA-based Full-Adder (QCAFA) and Carry-Save Adder (CSA) architecture is developed to enhance key performance factors such as delay, space, cost, and cell block count. The outlined designs demonstrate superior efficiency compared to state-of-the-art single-layer and multilayer QCA designs. Simulation results conducted with QCADesigner 2.0.3 and QCADesigner-E reveal that the proposed architecture achieves a substantial 34.29% diminution in total cells compared with the recent design, utilising only 46 QCA cells. Similarly, for the CSA, the proposed design attains an 18.62% reduction in cell count compared with its best counterpart, utilising only 424 QCA cell blocks. To enhance design credibility and hardware relevance, this research additionally models and validates the architecture using the Verilog hardware description language (HDL Version 12.0), thereby bridging the gap between nano-architecture and HDL-based prototyping. Simulation results obtained through QCADesigner confirm the correctness and stability of the QCA layout, while HDL simulation verifies functional equivalence at the behavioural and structural levels. The proposed designs not only enhance speed and reduce energy consumption but also offer better manufacturability. The findings of this study highlight the potential of QCA technology as a feasible substitute for CMOS for high-performance digital arithmetic circuits at the nanoscale. Full article

This position paper extends the author’s keynote address from the 2024 IEEE European Solid-State Electronics Research Conference, offering a perspective on effective strategies for the advancement of analog and mixed-signal (AMS) integrated circuit (IC) design. It is argued that traditional methodologies, characterized by their focus on transistor-level optimization within individual sub-blocks, are insufficient for satisfying the stringent performance and power consumption demands of contemporary information and communication technologies (ICT), especially in the context of expanding AI applications. Consequently, a paradigm shift is necessary, emphasizing “full-stack” solutions that prioritize comprehensive system-level analysis and aim to minimize physical resources and reduce complexity by innovating across the established boundaries of design abstraction levels. Building on prior work, this manuscript offers a more thorough justification for the proposed full-stack analog design methodology, supported by broader evidence and more comprehensive discussion. It also identifies key considerations regarding EDA and workforce development as topics for future work. Full article

Microwave-driven quantum logic gates in trapped-ion systems offer a scalable and laser-free alternative to optical control, with the potential for robust integration into surface-electrode trap architectures. In this work, we present a systematic design guideline for planar ion traps optimized for fast two-qubit microwave gates using chip-integrated conductors. We investigate two electrode configurations, one employing a single microwave line for driving $\sigma$ transitions, and another with two symmetric lines for $\pi$ transitions. Through finite-element simulations, we analyze ion height, magnetic field gradients, heating effects, and gate durations under realistic cryogenic conditions. Our results show that both configurations can achieve two-qubit gate times in the order of 10 μs for ${}^9\mathrm{Be}^{\mathrm{+}}$ and ${}^{40}\mathrm{Ca}^{\mathrm{+}}$ ions. Full article

This work presents the design and simulation of a time-interleaved successive approximation register (SAR) analog-to-digital converter (ADC) implemented in GlobalFoundries’ 22 nm Fully Depleted Silicon-on-Insulator (FD-SOI) CMOS process. Motivated by the increasing demand for high-speed electrical links in data center and AI/ML applications, the proposed ADC architecture targets medium-resolution, high-throughput conversion with optimized power and area efficiency. The design leverages asynchronous SAR operation, bootstrapped sampling switches, and a hybrid binary/non-binary capacitive digital-to-analog converter (DAC) to achieve robust performance across process, voltage, and temperature (PVT) variations. System-level modeling using channel operating margin (COM) methodology guided the specification of key circuit blocks, enabling efficient trade-offs between resolution, speed, and power. Post-layout simulations demonstrated effective number of bits (ENOB) performance consistent with system requirements, while Monte Carlo analysis confirmed the statistical yield. The converter achieved competitive figures of merit compared to state-of-the-art designs, as benchmarked against the Murmann ADC survey. This work highlights critical design considerations for scalable mixed-signal architectures in advanced CMOS nodes and lays the foundation for future integration in high-speed SerDes systems. Full article

Single Event Transients (SETs) in clock-distribution networks are a major source of soft errors in synchronous systems. We present a practical framework that assesses SET risk early in the design cycle, before layout and parasitics, using a Vulnerability Function (VF) derived from Verilog fault injection. This framework guides targeted Engineering Change Orders (ECOs), such as clock-net remapping, re-routing, and the selective insertion of SET filters, within a reproducible open-source flow (Yosys, OpenROAD, OpenSTA). A new analytical Soft Error Rate (SER) model for clock trees is also proposed, which decomposes contributions from the root, intermediate levels, and leaves, and is calibrated by SPICE-measured propagation probabilities, area, and particle flux. When coupled with throughput, this model yields a frequency-aware system-level Bit Error Rate (${BER}_{sys}$). The methodology was validated on a First-In First-Out (FIFO) memory, demonstrating a significant vulnerability reduction of approximately 3.35× in READ mode and 2.67× in WRITE mode. Frequency sweeps show monotonic decreases in both clock-tree vulnerability and ${BER}_{sys}$ at higher clock frequencies, a trend attributed to temporal masking and throughput effects. Cross-node SPICE characterization between 65 nm and 28 nm reveals a technology-dependent effect: for the same injected charge, the 28 nm process produces a shorter root-level pulse, which lowers the propagation probability relative to 65 nm and shifts the optimal clock-tree partition. These findings underscore the framework’s key innovations: a technology-independent, early-stage VF for ranking critical clock nets; a clock-tree SER model calibrated by measured propagation probabilities; an ECO loop that converts VF insights into concrete hardening actions; and a fully reproducible open-source implementation. The paper’s scope is architectural and pre-layout, with extensions to broader circuit classes and a full electrical analysis outlined for future work. Full article