Search for Articles:
Title / Keyword
Author / Affiliation / Email
Journal
Article Type
 
 
Advanced Search
 
Section
Special Issue
Volume
Issue
Number
Page
 
5.3
2.6
Journals
Electronics
Special Issues
Advanced Application of FPGA in Embedded Systems
share announcement

Advanced Application of FPGA in Embedded Systems

A special issue of Electronics (ISSN 2079-9292). This special issue belongs to the section "Computer Science & Engineering".

Deadline for manuscript submissions: closed (15 October 2022) | Viewed by 12538

Special Issue Editors

Dr. Bruno Da Silva

E-Mail Website
Guest Editor
Department of Electronics and Informatics (ETRO), Vrije Universiteit Brussel (VUB), 1050 Brussels, Belgium
Interests: reconfigurable computing; FPGA; biomedical devices; beamforming; microphone array; high-level synthesis; embedded medical systems; PPG signal processing
Special Issues, Collections and Topics in MDPI journals
Dr. Jo Vliegen

E-Mail Website
Guest Editor
imec-COSIC/ES&S, ESAT, KU Leuven, Belgium
Interests: FPGA; Partial Reconfiguration; Network intrusion detection; SOC

Special Issue Information

Dear Colleagues,

Field-programmable technology is widely applied in embedded and low-power platforms. A wide typology of FPGAs exists to address the computational demands of intensive applications while providing power efficiency required for battery-powered devices. This large variety of field-programmable devices, from system-on-chip FPGAs to low-power flash-based FPGAs, are adopted because of promising software-like flexibility with the performance of hardware. This Special Issue entitled “Advanced Application of FPGA in Embedded Systems” is intended to present the latest advances in applications benefiting from new FPGA architectures and features and to illustrate the wide range of applications where FPGAs can offer a competitive, if not the best, design option.

Topics of interest include but are not limited to:

  • Novel architectures to exploit field-programmable technology;
  • Use of FPGAs as embedded hardware accelerators;
  • New approaches for energy efficiency on reconfigurable computing;
  • Advances in hardware/software co-design for system-on-chip FPGAs;
  • Applications of field-programmable technology, including accelerators for machine learning, real-time systems, cryptography, machine vision, sensor arrays, biomedical or embedded applications in general, among others.

Dr. Bruno Da Silva
Dr. Jo Vliegen
Guest Editors

Manuscript Submission Information

Manuscripts should be submitted online at www.mdpi.com by registering and logging in to this website. Once you are registered, click here to go to the submission form. Manuscripts can be submitted until the deadline. All submissions that pass pre-check are peer-reviewed. Accepted papers will be published continuously in the journal (as soon as accepted) and will be listed together on the special issue website. Research articles, review articles as well as short communications are invited. For planned papers, a title and short abstract (about 100 words) can be sent to the Editorial Office for announcement on this website.

Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Electronics is an international peer-reviewed open access semimonthly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 2400 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

Keywords

  • FPGAs
  • Reconfigurable computing
  • Embedded systems
  • Power efficiency
  • System-on-chip

Benefits of Publishing in a Special Issue

  • Ease of navigation: Grouping papers by topic helps scholars navigate broad scope journals more efficiently.
  • Greater discoverability: Special Issues support the reach and impact of scientific research. Articles in Special Issues are more discoverable and cited more frequently.
  • Expansion of research network: Special Issues facilitate connections among authors, fostering scientific collaborations.
  • External promotion: Articles in Special Issues are often promoted through the journal's social media, increasing their visibility.
  • e-Book format: Special Issues with more than 10 articles can be published as dedicated e-books, ensuring wide and rapid dissemination.

Further information on MDPI's Special Issue policies can be found here.

Published Papers (3 papers)

Download All Papers
Order results
Result details
Show export options expand_more Show export options expand_less
Select all
Export citation of selected articles as:

Research

11 pages, 761 KiB  
Article
Hybrid CNN-SVM Inference Accelerator on FPGA Using HLS
by Bing Liu, Yanzhen Zhou, Lei Feng, Hongshuo Fu and Ping Fu
Electronics 2022, 11(14), 2208; https://doi.org/10.3390/electronics11142208 - 14 Jul 2022
Cited by 8 | Viewed by 3105
Abstract
Convolution neural networks (CNN), support vector machine (SVM) and hybrid CNN-SVM algorithms are widely applied in many fields, including image processing and fault diagnosis. Although many dedicated FPGA accelerators have been proposed for specific networks, such as CNN or SVM, few of them [...] Read more.
Convolution neural networks (CNN), support vector machine (SVM) and hybrid CNN-SVM algorithms are widely applied in many fields, including image processing and fault diagnosis. Although many dedicated FPGA accelerators have been proposed for specific networks, such as CNN or SVM, few of them have focused on CNN-SVM. Furthermore, the existing accelerators do not support CNN-SVM, which limits their application scenarios. In this work, we propose a hybrid CNN-SVM accelerator on FPGA. This accelerator utilizes a novel hardware-reuse architecture and unique computation mapping strategy to implement different calculation modes in CNN-SVM so that it can realize resource-efficient acceleration of the hybrid algorithm. In addition, we propose a universal deployment methodology to automatically select accelerator design parameters according to the target platform and algorithm. The experimental results on ZYNQ-7020 show that our implementation can efficiently map CNN-SVM onto FPGA, and the performance is competitive with other state-of-the-art works. Full article
(This article belongs to the Special Issue Advanced Application of FPGA in Embedded Systems)
►▼ Show Figures

Figure 1

28 pages, 1941 KiB  
Article
Two-Layer Bus-Independent Instruction Set Architecture for Securing Long Protocol Data Units in Automotive Open System Architecture-Based Automotive Electronic Control Units
by Ahmed Hamed, M. Watheq El-Kharashi, Ashraf Salem and Mona Safar
Electronics 2022, 11(6), 952; https://doi.org/10.3390/electronics11060952 - 18 Mar 2022
Cited by 7 | Viewed by 3624
Abstract
In this paper, we propose a bus-independent hardware (HW)-based approach to secure long protocol data units (PDUs) in Automotive Open System Architecture (AUTOSAR)-based automotive electronic control units (ECUs). Our approach is based on extending previous works that implemented two AUTOSAR communication (COM) application-specific [...] Read more.
In this paper, we propose a bus-independent hardware (HW)-based approach to secure long protocol data units (PDUs) in Automotive Open System Architecture (AUTOSAR)-based automotive electronic control units (ECUs). Our approach is based on extending previous works that implemented two AUTOSAR communication (COM) application-specific instruction set processors (ASIPs). COM ASIP V1 introduced two instructions to handle the transmission and reception of PDUs no larger than 8 bytes and signals no larger than 32 bits individually through send signal and receive signal instructions. COM ASIP V2 introduced two extra instructions to handle long signals and PDUs of arbitrary lengths. We extended the instruction set architecture (ISA) of our previous ASIPs by introducing six new instructions, in COM ASIP V3, to hash PDUs that contain these signals to authenticate transmission and reception of such PDUs. The experimental results show that COM ASIP V3 can handle (i.e., transmit, receive, calculate hash, or verify hash) a 64-byte controller area network flexible data-rate (CAN FD) frame in 1.575 μs and a 254-byte FlexRay frame in 6.301 μs. These measurements indicate that the throughput of our new COM ASIP is much higher, 42× to 75×, than the throughput required by these communication buses. Full article
(This article belongs to the Special Issue Advanced Application of FPGA in Embedded Systems)
►▼ Show Figures

Figure 1

31 pages, 3640 KiB  
Article
Environmental Sound Recognition on Embedded Systems: From FPGAs to TPUs
by Jurgen Vandendriessche, Nick Wouters, Bruno da Silva, Mimoun Lamrini, Mohamed Yassin Chkouri and Abdellah Touhafi
Electronics 2021, 10(21), 2622; https://doi.org/10.3390/electronics10212622 - 27 Oct 2021
Cited by 20 | Viewed by 4540
Abstract
In recent years, Environmental Sound Recognition (ESR) has become a relevant capability for urban monitoring applications. The techniques for automated sound recognition often rely on machine learning approaches, which have increased in complexity in order to achieve higher accuracy. Nonetheless, such machine learning [...] Read more.
In recent years, Environmental Sound Recognition (ESR) has become a relevant capability for urban monitoring applications. The techniques for automated sound recognition often rely on machine learning approaches, which have increased in complexity in order to achieve higher accuracy. Nonetheless, such machine learning techniques often have to be deployed on resource and power-constrained embedded devices, which has become a challenge with the adoption of deep learning approaches based on Convolutional Neural Networks (CNNs). Field-Programmable Gate Arrays (FPGAs) are power efficient and highly suitable for computationally intensive algorithms like CNNs. By fully exploiting their parallel nature, they have the potential to accelerate the inference time as compared to other embedded devices. Similarly, dedicated architectures to accelerate Artificial Intelligence (AI) such as Tensor Processing Units (TPUs) promise to deliver high accuracy while achieving high performance. In this work, we evaluate existing tool flows to deploy CNN models on FPGAs as well as on TPU platforms. We propose and adjust several CNN-based sound classifiers to be embedded on such hardware accelerators. The results demonstrate the maturity of the existing tools and how FPGAs can be exploited to outperform TPUs. Full article
(This article belongs to the Special Issue Advanced Application of FPGA in Embedded Systems)
►▼ Show Figures

Figure 1

Show export options expand_more Show export options expand_less
Select all
Export citation of selected articles as:
 
Displaying articles 1-3
Back to TopTop