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18 Results Found

  • Article
  • Open Access
3 Citations
3,821 Views
35 Pages

The increasing complexity of algorithms in embedded applications has amplified the demand for high-performance computing. Heterogeneous embedded systems, particularly FPGA-based systems-on-chip (SoCs), enhance execution speed by integrating hardware...

  • Article
  • Open Access
4 Citations
3,047 Views
14 Pages

Hardware Acceleration of Digital Pulse Shape Analysis Using FPGAs

  • César González,
  • Mariano Ruiz,
  • Antonio Carpeño,
  • Alejandro Piñas,
  • Daniel Cano-Ott,
  • Julio Plaza,
  • Trino Martinez and
  • David Villamarin

25 April 2024

The BC501A sensor is a liquid scintillator frequently used in nuclear physics for detecting fast neutrons. This paper describes a hardware implementation of digital pulse shape analysis (DPSA) for real-time analysis. DPSA is an algorithm that extract...

  • Article
  • Open Access
1,531 Views
21 Pages

FPGA-based convolutional accelerators have been widely used in image recognition scenarios. Many convolutional accelerators utilize the systolic array structure to enhance parallelism. Developing a method to efficiently estimate the utilized hardware...

  • Feature Paper
  • Article
  • Open Access
10 Citations
4,796 Views
17 Pages

High-Level Synthesis of Multiclass SVM Using Code Refactoring to Classify Brain Cancer from Hyperspectral Images

  • Abelardo Baez,
  • Himar Fabelo,
  • Samuel Ortega,
  • Giordana Florimbi,
  • Emanuele Torti,
  • Abian Hernandez,
  • Francesco Leporati,
  • Giovanni Danese,
  • Gustavo M. Callico and
  • Roberto Sarmiento

6 December 2019

Currently, high-level synthesis (HLS) methods and tools are a highly relevant area in the strategy of several leading companies in the field of system-on-chips (SoCs) and field programmable gate arrays (FPGAs). HLS facilitates the work of system deve...

  • Article
  • Open Access
3 Citations
3,423 Views
15 Pages

Tiny machine learning (TinyML) demands the development of edge solutions that are both low-latency and power-efficient. To achieve these on System-on-Chip (SoC) FPGAs, co-design methodologies, such as hls4ml, have emerged aiming to speed up the desig...

  • Article
  • Open Access
10 Citations
3,303 Views
16 Pages

A Highly Configurable High-Level Synthesis Functional Pattern Library

  • Lan Huang,
  • Teng Gao,
  • Dalin Li,
  • Zihao Wang and
  • Kangping Wang

25 February 2021

FPGA has recently played an increasingly important role in heterogeneous computing, but Register Transfer Level design flows are not only inefficient in design, but also require designers to be familiar with the circuit architecture. High-level synth...

  • Article
  • Open Access
1 Citations
1,933 Views
16 Pages

22 May 2023

The paper proposes an enhanced design for broadband digital receivers that aims to improve signal capture probability, real-time performance, and the hardware development cycle. To overcome the issue of false signals in the blind zone channelization...

  • Article
  • Open Access
281 Views
25 Pages

A Novel FEC Implementation for VSAT Terminals Using High-Level Synthesis

  • Najmeh Khosroshahi,
  • Ron Mankarious and
  • Mohammad Reza Soleymani

6 February 2026

This paper presents a hardware-efficient field-programmable gate array (FPGA) implementation of a layered two-dimensional corrected normalized min-sum (2D-CNMS) decoder for quasi-cyclic low-density parity-check (QC-LDPC) codes in very small aperture...

  • Article
  • Open Access
10 Citations
6,416 Views
16 Pages

As one of the fields of Artificial Intelligence (AI), Optical Character Recognition (OCR) systems have wide application in both industrial production and daily life. Conventional OCR systems are commonly designed and implement data computation on the...

  • Article
  • Open Access
7 Citations
5,170 Views
19 Pages

Due to performance and energy requirements, FPGA-based accelerators have become a promising solution for high-performance computations. Meanwhile, with the help of high-level synthesis (HLS) compilers, FPGA can be programmed using common programming...

  • Article
  • Open Access
8 Citations
5,661 Views
23 Pages

Muon–Electron Pulse Shape Discrimination for Water Cherenkov Detectors Based on FPGA/SoC

  • Luis Guillermo Garcia,
  • Romina Soledad Molina,
  • Maria Liz Crespo,
  • Sergio Carrato,
  • Giovanni Ramponi,
  • Andres Cicuttin,
  • Ivan Rene Morales and
  • Hector Perez

The distinction of secondary particles in extensive air showers, specifically muons and electrons, is one of the requirements to perform a good measurement of the composition of primary cosmic rays. We describe two methods for pulse shape detection a...

  • Article
  • Open Access
13 Citations
3,892 Views
18 Pages

31 October 2021

The increment in the use of high-resolution imaging sensors on-board satellites motivates the use of on-board image compression, mainly due to restrictions in terms of both hardware (computational and storage resources) and downlink bandwidth with th...

  • Article
  • Open Access
6 Citations
5,348 Views
16 Pages

Research on Convolutional Neural Network Inference Acceleration and Performance Optimization for Edge Intelligence

  • Yong Liang,
  • Junwen Tan,
  • Zhisong Xie,
  • Zetao Chen,
  • Daoqian Lin and
  • Zhenhao Yang

31 December 2023

In recent years, edge intelligence (EI) has emerged, combining edge computing with AI, and specifically deep learning, to run AI algorithms directly on edge devices. In practical applications, EI faces challenges related to computational power, power...

  • Article
  • Open Access
56 Citations
6,588 Views
19 Pages

A Uniform Architecture Design for Accelerating 2D and 3D CNNs on FPGAs

  • Zhiqiang Liu,
  • Paul Chow,
  • Jinwei Xu,
  • Jingfei Jiang,
  • Yong Dou and
  • Jie Zhou

Three-dimensional convolutional neural networks (3D CNNs) have gained popularity in many complicated computer vision applications. Many customized accelerators based on FPGAs are proposed for 2D CNNs, while very few are for 3D CNNs. Three-D CNNs are...

  • Article
  • Open Access
15 Citations
4,138 Views
23 Pages

Lossy Hyperspectral Image Compression on a Reconfigurable and Fault-Tolerant FPGA-Based Adaptive Computing Platform

  • Yubal Barrios,
  • Alfonso Rodríguez,
  • Antonio Sánchez,
  • Arturo Pérez,
  • Sebastián López,
  • Andrés Otero,
  • Eduardo de la Torre and
  • Roberto Sarmiento

26 September 2020

This paper describes a novel hardware implementation of a lossy multispectral and hyperspectral image compressor for on-board operation in space missions. The compression algorithm is a lossy extension of the Consultative Committee for Space Data Sys...

  • Article
  • Open Access
9 Citations
3,073 Views
15 Pages

Lightweight Cryptography for Connected Vehicles Communication Security on Edge Devices

  • Sahbi Boubaker,
  • Faisal S. Alsubaei,
  • Yahia Said and
  • Hossam E. Ahmed

29 September 2023

Recent advances in mobile connection technology have been involved in every aspect of modern life. Even vehicles are becoming more connected, with the ability to communicate without human intervention. The main idea of connected vehicles is to exchan...

  • Article
  • Open Access
16 Citations
5,866 Views
20 Pages

A Novel FPGA-Based Architecture for Fast Automatic Target Detection in Hyperspectral Images

  • Jie Lei,
  • Lingyun Wu,
  • Yunsong Li,
  • Weiying Xie,
  • Chein-I Chang,
  • Jintao Zhang and
  • Biying Huang

14 January 2019

Onboard target detection of hyperspectral imagery (HSI), considered as a significant remote sensing application, has gained increasing attention in the latest years. It usually requires processing huge volumes of HSI data in real-time under constrain...

  • Article
  • Open Access
10 Citations
3,977 Views
20 Pages

11 January 2023

Algorithms and computing power have consistently been the two driving forces behind the development of artificial intelligence. The computational power of a platform has a significant impact on the implementation cost, performance, power consumption,...