A Uniform Architecture Design for Accelerating 2D and 3D CNNs on FPGAs
AbstractThree-dimensional convolutional neural networks (3D CNNs) have gained popularity in many complicated computer vision applications. Many customized accelerators based on FPGAs are proposed for 2D CNNs, while very few are for 3D CNNs. Three-D CNNs are far more computationally intensive and the design space for 3D CNN acceleration has been further expanded since one more dimension is introduced, making it a big challenge to accelerate 3D CNNs on FPGAs. Motivated by the finding that the computation patterns of 2D and 3D CNNs are very similar, we propose a uniform architecture design for accelerating both 2D and 3D CNNs in this paper. The uniform architecture is based on the idea of mapping convolutions to matrix multiplications. A customized mapping module is developed to generate the feature matrix tilings with no need to store the entire enlarged feature matrix on-chip or off-chip, a splitting strategy is adopted to reconstruct a convolutional layer to adapt to the on-chip memory capacity, and a 2D multiply-and-accumulate (MAC) array is adopted to compute matrix multiplications efficiently. For demonstration, we implement an accelerator prototype with a high-level synthesis (HLS) methodology on a Xilinx VC709 board and test the accelerator on three typical CNN models: AlexNet, VGG16, and C3D. Experimental results show that the accelerator achieves state-of-the-art throughput performance on both 2D and 3D CNNs, with much better energy efficiency than the CPU and GPU. View Full-Text
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Liu, Z.; Chow, P.; Xu, J.; Jiang, J.; Dou, Y.; Zhou, J. A Uniform Architecture Design for Accelerating 2D and 3D CNNs on FPGAs. Electronics 2019, 8, 65.
Liu Z, Chow P, Xu J, Jiang J, Dou Y, Zhou J. A Uniform Architecture Design for Accelerating 2D and 3D CNNs on FPGAs. Electronics. 2019; 8(1):65.Chicago/Turabian Style
Liu, Zhiqiang; Chow, Paul; Xu, Jinwei; Jiang, Jingfei; Dou, Yong; Zhou, Jie. 2019. "A Uniform Architecture Design for Accelerating 2D and 3D CNNs on FPGAs." Electronics 8, no. 1: 65.
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