Special Issue "Miniaturized Transistors"

A special issue of Micromachines (ISSN 2072-666X). This special issue belongs to the section "A:Physics".

Deadline for manuscript submissions: closed (31 December 2018)

Special Issue Editors

Guest Editor
Dr. Lado Filipovic

Institute for Microelectronics, TU Wien, Gußhausstraße 27-29/E360, 1040 Wien, Austria
Website | E-Mail
Phone: +43-1-58801-36036
Interests: integrated sensors; semiconductor fabrication; CMOS; process modeling; TCAD; interconnect reliability; 3D integration
Guest Editor
Prof. Dr. Tibor Grasser

Institute for Microelectronics, TU Wien, Gußhausstraße 27-29/E360, 1040 Wien, Austria
Website | E-Mail
Phone: +43-1-58801-36023
Interests: transistor reliability; bias temperature instability; hot carrier degradation; degradation phenomena in emerging devices; modeling and simulation of semiconductor devices

Special Issue Information

Dear Colleagues,

What is the future of CMOS? Sustaining increased transistor densities along the path of Moore's Law has become increasingly challenging with limited power budgets, interconnect bandwidths, and fabrication capabilities. In the last decade alone, transistors have undergone significant design makeovers; from planar transistors of ten years ago, technological advancements have accelerated to today's FinFETs, which hardly resemble their bulky ancestors. FinFETs could potentially take us to the 5-nm node, but what comes after it? From gate-all-around devices to single electron transistors and two-dimensional semiconductors, a torrent of research is being carried out in order to design the next transistor generation, engineer the optimal materials, improve the fabrication technology, and properly model future devices. We invite insight from investigators and scientists in the field to showcase their work in this Special Issue with research papers, short communications, and review articles that focus on trends in micro- and nanotechnology from fundamental research to applications.

Dr. Lado Filipovic
Prof. Dr. Tibor Grasser
Guest Editors

Manuscript Submission Information

Manuscripts should be submitted online at www.mdpi.com by registering and logging in to this website. Once you are registered, click here to go to the submission form. Manuscripts can be submitted until the deadline. All papers will be peer-reviewed. Accepted papers will be published continuously in the journal (as soon as accepted) and will be listed together on the special issue website. Research articles, review articles as well as short communications are invited. For planned papers, a title and short abstract (about 100 words) can be sent to the Editorial Office for announcement on this website.

Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Micromachines is an international peer-reviewed open access monthly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 1400 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

Keywords

  • CMOS transistor scaling
  • Advanced More Moore devices and circuits
  • Nano-scale devices
  • - Nanoelectronics
  • - Nanostructures
  • - Quantum information processing
  • - Quantum physics
  • - Quantum transport Emerging devices and memories
  • Fabrication of modern devices and interconnects
  • Process reliability and variability
  • Modeling and simulation of semiconductor processes and devices
  • Compact modeling
  • Circuit simulation

Published Papers (14 papers)

View options order results:
result details:
Displaying articles 1-14
Export citation of selected articles as:

Editorial

Jump to: Research, Review

Open AccessEditorial
Editorial for the Special Issue on Miniaturized Transistors
Micromachines 2019, 10(5), 300; https://doi.org/10.3390/mi10050300
Received: 25 April 2019 / Accepted: 25 April 2019 / Published: 2 May 2019
PDF Full-text (173 KB) | HTML Full-text | XML Full-text
Abstract
Complementary Metal Oxide Semiconductor (CMOS) devices and fabrication techniques have enabled tremendous technological advancements in a short period of time [...] Full article
(This article belongs to the Special Issue Miniaturized Transistors)

Research

Jump to: Editorial, Review

Open AccessArticle
Incorporation of Phosphorus Impurities in a Silicon Nanowire Transistor with a Diameter of 5 nm
Micromachines 2019, 10(2), 127; https://doi.org/10.3390/mi10020127
Received: 15 November 2018 / Revised: 2 February 2019 / Accepted: 3 February 2019 / Published: 15 February 2019
Cited by 1 | PDF Full-text (1912 KB) | HTML Full-text | XML Full-text
Abstract
Silicon nanowire (SiNW) is always accompanied by severe impurity segregation and inhomogeneous distribution, which deteriorates the SiNWs electrical characteristics. In this paper, a method for phosphorus doping incorporation in SiNW was proposed using plasma. It showed that this method had a positive effect [...] Read more.
Silicon nanowire (SiNW) is always accompanied by severe impurity segregation and inhomogeneous distribution, which deteriorates the SiNWs electrical characteristics. In this paper, a method for phosphorus doping incorporation in SiNW was proposed using plasma. It showed that this method had a positive effect on the doping concentration of the wires with a diameter ranging from 5 nm to 20 nm. Moreover, an SiNW transistor was assembled based on the nanowire with a 5 nm diameter. The device’s ION/IOFF ratio reached 104. The proposed incorporation method could be helpful to improve the effect of the dopants in the silicon nanowire at a nanometer scale. Full article
(This article belongs to the Special Issue Miniaturized Transistors)
Figures

Figure 1

Open AccessArticle
High Performance Drain Engineered InGaN Heterostructure Tunnel Field Effect Transistor
Micromachines 2019, 10(1), 75; https://doi.org/10.3390/mi10010075
Received: 27 December 2018 / Revised: 18 January 2019 / Accepted: 18 January 2019 / Published: 21 January 2019
Cited by 1 | PDF Full-text (8648 KB) | HTML Full-text | XML Full-text
Abstract
A drain engineered InGaN heterostructure tunnel field effect transistor (TFET) is proposed and investigated by Silvaco Atlas simulation. This structure uses an additional metal on the drain region to modulate the energy band near the drain/channel interface in the drain regions, and increase [...] Read more.
A drain engineered InGaN heterostructure tunnel field effect transistor (TFET) is proposed and investigated by Silvaco Atlas simulation. This structure uses an additional metal on the drain region to modulate the energy band near the drain/channel interface in the drain regions, and increase the tunneling barrier for the flow of holes from the conduction band of the drain to the valence band of the channel region under negative gate bias for n-TFET, which induces the ambipolar current being reduced from 1.93 × 10−8 to 1.46 × 10−11 A/μm. In addition, polar InGaN heterostructure TFET having a polarization effect can adjust the energy band structure and achieve steep interband tunneling. The average subthreshold swing of the polar drain engineered heterostructure TFET (DE-HTFET) is reduced by 53.3% compared to that of the nonpolar DE-HTFET. Furthermore, ION increases 100% from 137 mA/mm of nonpolar DE-HTFET to 274 mA/mm of polar DE-HTFET. Full article
(This article belongs to the Special Issue Miniaturized Transistors)
Figures

Figure 1

Open AccessArticle
Design and Characterization of Semi-Floating-Gate Synaptic Transistor
Micromachines 2019, 10(1), 32; https://doi.org/10.3390/mi10010032
Received: 14 November 2018 / Revised: 31 December 2018 / Accepted: 2 January 2019 / Published: 7 January 2019
Cited by 1 | PDF Full-text (4231 KB) | HTML Full-text | XML Full-text
Abstract
In this work, a study on a semi-floating-gate synaptic transistor (SFGST) is performed to verify its feasibility in the more energy-efficient hardware-driven neuromorphic system. To realize short- and long-term potentiation (STP/LTP) in the SFGST, a poly-Si semi-floating gate (SFG) and a SiN charge-trap [...] Read more.
In this work, a study on a semi-floating-gate synaptic transistor (SFGST) is performed to verify its feasibility in the more energy-efficient hardware-driven neuromorphic system. To realize short- and long-term potentiation (STP/LTP) in the SFGST, a poly-Si semi-floating gate (SFG) and a SiN charge-trap layer are utilized, respectively. When an adequate number of holes are accumulated in the SFG, they are injected into the nitride charge-trap layer by the Fowler–Nordheim tunneling mechanism. Moreover, since the SFG is charged by an embedded tunneling field-effect transistor existing between the channel and the drain junction when the post-synaptic spike occurs after the pre-synaptic spike, and vice versa, the SFG is discharged by the diode when the post-synaptic spike takes place before the pre-synaptic spike. This indicates that the SFGST can attain STP/LTP and spike-timing-dependent plasticity behaviors. These characteristics of the SFGST in the highly miniaturized transistor structure can contribute to the neuromorphic chip such that the total system may operate as fast as the human brain with low power consumption and high integration density. Full article
(This article belongs to the Special Issue Miniaturized Transistors)
Figures

Figure 1

Open AccessArticle
Process Variability—Technological Challenge and Design Issue for Nanoscale Devices
Micromachines 2019, 10(1), 6; https://doi.org/10.3390/mi10010006
Received: 8 December 2018 / Revised: 14 December 2018 / Accepted: 15 December 2018 / Published: 23 December 2018
Cited by 1 | PDF Full-text (5714 KB) | HTML Full-text | XML Full-text
Abstract
Current advanced transistor architectures, such as FinFETs and (stacked) nanowires and nanosheets, employ truly three-dimensional architectures. Already for aggressively scaled bulk transistors, both statistical and systematic process variations have critically influenced device and circuit performance. Three-dimensional device architectures make the control and optimization [...] Read more.
Current advanced transistor architectures, such as FinFETs and (stacked) nanowires and nanosheets, employ truly three-dimensional architectures. Already for aggressively scaled bulk transistors, both statistical and systematic process variations have critically influenced device and circuit performance. Three-dimensional device architectures make the control and optimization of the device geometries even more important, both in view of the nominal electrical performance to be achieved and its variations. In turn, it is essential to accurately simulate the device geometry and its impact on the device properties, including the effect caused by non-idealized processes which are subject to various kinds of systematic variations induced by process equipment. In this paper, the hierarchical simulation system developed in the SUPERAID7 project to study the impact of variations from equipment to circuit level is presented. The software system consists of a combination of existing commercial and newly developed tools. As the paper focuses on technological challenges, especially issues resulting from the structuring processes needed to generate the three-dimensional device architectures are discussed. The feasibility of a full simulation of the impact of relevant systematic and stochastic variations on advanced devices and circuits is demonstrated. Full article
(This article belongs to the Special Issue Miniaturized Transistors)
Figures

Figure 1

Open AccessArticle
Empirical and Theoretical Modeling of Low-Frequency Noise Behavior of Ultrathin Silicon-on-Insulator MOSFETs Aiming at Low-Voltage and Low-Energy Regime
Micromachines 2019, 10(1), 5; https://doi.org/10.3390/mi10010005
Received: 4 November 2018 / Revised: 15 December 2018 / Accepted: 18 December 2018 / Published: 22 December 2018
Cited by 1 | PDF Full-text (3478 KB) | HTML Full-text | XML Full-text
Abstract
This paper theoretically revisits the low-frequency noise behavior of the inversion-channel silicon-on-insulator metal-oxide-semiconductor field-effect transistor (SOI MOSFET) and the buried-channel SOI MOSFET because the quality of both Si/SiO2 interfaces (top and bottom) should modulate the low-frequency fluctuation characteristics of both devices. It [...] Read more.
This paper theoretically revisits the low-frequency noise behavior of the inversion-channel silicon-on-insulator metal-oxide-semiconductor field-effect transistor (SOI MOSFET) and the buried-channel SOI MOSFET because the quality of both Si/SiO2 interfaces (top and bottom) should modulate the low-frequency fluctuation characteristics of both devices. It also addresses the low-frequency noise behavior of sub-100-nm channel SOI MOSFETs. We deepen the discussion of the low-frequency noise behavior in the subthreshold bias range in order to elucidate the device’s potential for future low-voltage and low-power applications. As expected, analyses suggest that the weak inversion channel near the top surface of the SOI MOSFET is strongly influenced by interface traps near the top surface of the SOI layer because the traps are not well shielded by low-density surface inversion carriers in the subthreshold bias range. Unexpectedly, we find that the buried channel is primarily influenced by interface traps near the top surface of the SOI layer, not by traps near the bottom surface of the SOI layer. This is not due to the simplified capacitance coupling effect. These interesting characteristics of current fluctuation spectral intensity are explained well by the theoretical models proposed here. Full article
(This article belongs to the Special Issue Miniaturized Transistors)
Figures

Figure 1

Open AccessArticle
Remote Phonon Scattering in Two-Dimensional InSe FETs with High-κ Gate Stack
Micromachines 2018, 9(12), 674; https://doi.org/10.3390/mi9120674
Received: 15 November 2018 / Revised: 13 December 2018 / Accepted: 17 December 2018 / Published: 19 December 2018
Cited by 2 | PDF Full-text (7536 KB) | HTML Full-text | XML Full-text
Abstract
This work focuses on the effect of remote phonon arising from the substrate and high-κ gate dielectric on electron mobility in two-dimensional (2D) InSe field-effect transistors (FETs). The electrostatic characteristic under quantum confinement is derived by self-consistently solving the Poisson and Schrödinger [...] Read more.
This work focuses on the effect of remote phonon arising from the substrate and high-κ gate dielectric on electron mobility in two-dimensional (2D) InSe field-effect transistors (FETs). The electrostatic characteristic under quantum confinement is derived by self-consistently solving the Poisson and Schrödinger equations using the effective mass approximation. Then mobility is calculated by the Kubo–Greenwood formula accounting for the remote phonon scattering (RPS) as well as the intrinsic phonon scatterings, including the acoustic phonon, homopolar phonon, optical phonon scatterings, and Fröhlich interaction. Using the above method, the mobility degradation due to remote phonon is comprehensively explored in single- and dual-gate InSe FETs utilizing SiO2, Al2O3, and HfO2 as gate dielectric respectively. We unveil the origin of temperature, inversion density, and thickness dependence of carrier mobility. Simulations indicate that remote phonon and Fröhlich interaction plays a comparatively major role in determining the electron transport in InSe. Mobility is more severely degraded by remote phonon of HfO2 dielectric than Al2O3 and SiO2 dielectric, which can be effectively insulated by introducing a SiO2 interfacial layer between the high-κ dielectric and InSe. Due to its smaller in-plane and quantization effective masses, mobility begins to increase at higher density as carriers become degenerate, and mobility degradation with a reduced layer number is much stronger in InSe compared with MoS2. Full article
(This article belongs to the Special Issue Miniaturized Transistors)
Figures

Figure 1

Open AccessArticle
3D Numerical Simulation of a Z Gate Layout MOSFET for Radiation Tolerance
Micromachines 2018, 9(12), 659; https://doi.org/10.3390/mi9120659
Received: 11 November 2018 / Revised: 10 December 2018 / Accepted: 11 December 2018 / Published: 14 December 2018
Cited by 1 | PDF Full-text (1203 KB) | HTML Full-text | XML Full-text
Abstract
In this paper, for the first time, an n-channel metal-oxide-semiconductor field-effect transistor (NMOSFET) layout with a Z gate and an improved total ionizing dose (TID) tolerance is proposed. The novel layout can be radiation-hardened with a fixed charge density at the shallow trench [...] Read more.
In this paper, for the first time, an n-channel metal-oxide-semiconductor field-effect transistor (NMOSFET) layout with a Z gate and an improved total ionizing dose (TID) tolerance is proposed. The novel layout can be radiation-hardened with a fixed charge density at the shallow trench isolation (STI) of 3.5 × 1012 cm−2. Moreover, it has the advantages of a small footprint, no limitation in W/L design, and a small gate capacitance compared with the enclosed gate layout. Beside the Z gate layout, a non-radiation-hardened single gate layout and a radiation-hardened enclosed gate layout are simulated using the Sentaurus 3D technology computer-aided design (TCAD) software. First, the transfer characteristics curves (Id-Vg) curves of the three layouts are compared to verify the radiation tolerance characteristic of the Z gate layout; then, the threshold voltage and the leakage current of the three layouts are extracted to compare their TID responses. Lastly, the threshold voltage shift and the leakage current increment at different radiation doses for the three layouts are presented and analyzed. Full article
(This article belongs to the Special Issue Miniaturized Transistors)
Figures

Figure 1

Open AccessArticle
Improving ESD Protection Robustness Using SiGe Source/Drain Regions in Tunnel FET
Micromachines 2018, 9(12), 657; https://doi.org/10.3390/mi9120657
Received: 14 November 2018 / Revised: 7 December 2018 / Accepted: 9 December 2018 / Published: 12 December 2018
Cited by 2 | PDF Full-text (2875 KB) | HTML Full-text | XML Full-text
Abstract
Currently, a tunnel field-effect transistor (TFET) is being considered as a suitable electrostatic discharge (ESD) protection device in advanced technology. In addition, silicon-germanium (SiGe) engineering is shown to improve the performance of TFET-based ESD protection devices. In this paper, a new TFET with [...] Read more.
Currently, a tunnel field-effect transistor (TFET) is being considered as a suitable electrostatic discharge (ESD) protection device in advanced technology. In addition, silicon-germanium (SiGe) engineering is shown to improve the performance of TFET-based ESD protection devices. In this paper, a new TFET with SiGe source/drain (S/D) regions is proposed, and its ESD characteristics are evaluated using technology computer aided design (TCAD) simulations. Under a transmission line pulsing (TLP) stressing condition, the triggering voltage of the SiGe S/D TFET is reduced by 35% and the failure current is increased by 17% in comparison with the conventional Si S/D TFET. Physical insights relevant to the ESD enhancement of the SiGe S/D TFET are provided and discussed. Full article
(This article belongs to the Special Issue Miniaturized Transistors)
Figures

Figure 1

Open AccessArticle
Variability Predictions for the Next Technology Generations of n-type SixGe1−x Nanowire MOSFETs
Micromachines 2018, 9(12), 643; https://doi.org/10.3390/mi9120643
Received: 21 November 2018 / Revised: 29 November 2018 / Accepted: 30 November 2018 / Published: 5 December 2018
Cited by 1 | PDF Full-text (1373 KB) | HTML Full-text | XML Full-text
Abstract
Using a state-of-the-art quantum transport simulator based on the effective mass approximation, we have thoroughly studied the impact of variability on SixGe1x channel gate-all-around nanowire metal-oxide-semiconductor field-effect transistors (NWFETs) associated with random discrete dopants, line edge roughness, and [...] Read more.
Using a state-of-the-art quantum transport simulator based on the effective mass approximation, we have thoroughly studied the impact of variability on Si x Ge 1 x channel gate-all-around nanowire metal-oxide-semiconductor field-effect transistors (NWFETs) associated with random discrete dopants, line edge roughness, and metal gate granularity. Performance predictions of NWFETs with different cross-sectional shapes such as square, circle, and ellipse are also investigated. For each NWFETs, the effective masses have carefully been extracted from s p 3 d 5 s tight-binding band structures. In total, we have generated 7200 transistor samples and performed approximately 10,000 quantum transport simulations. Our statistical analysis reveals that metal gate granularity is dominant among the variability sources considered in this work. Assuming the parameters of the variability sources are the same, we have found that there is no significant difference of variability between SiGe and Si channel NWFETs. Full article
(This article belongs to the Special Issue Miniaturized Transistors)
Figures

Figure 1

Open AccessArticle
The Balancing Act in Ferroelectric Transistors: How Hard Can It Be?
Micromachines 2018, 9(11), 582; https://doi.org/10.3390/mi9110582
Received: 19 October 2018 / Revised: 31 October 2018 / Accepted: 5 November 2018 / Published: 7 November 2018
Cited by 2 | PDF Full-text (1198 KB) | HTML Full-text | XML Full-text
Abstract
For some years now, the ever continuing dimensional scaling has no longer been considered to be sufficient for the realization of advanced CMOS devices. Alternative approaches, such as employing new materials and introducing new device architectures, appear to be the way to go [...] Read more.
For some years now, the ever continuing dimensional scaling has no longer been considered to be sufficient for the realization of advanced CMOS devices. Alternative approaches, such as employing new materials and introducing new device architectures, appear to be the way to go forward. A currently hot approach is to employ ferroelectric materials for obtaining a positive feedback in the gate control of a switch. This work elaborates on two device architectures based on this approach: the negative-capacitance and the piezoelectric field-effect transistor, i.e., the NC-FET (negative-capacitance field-effect transistor), respectively π -FET. It briefly describes their operation principle and compares those based on earlier reports. For optimal performance, the adopted ferroelectric material in the NC-FET should have a relatively wide polarization-field loop (i.e., “hard” ferroelectric material). Its optimal remnant polarization depends on the NC-FET architecture, although there is some consensus in having a low value for that (e.g., HZO (Hafnium-Zirconate)). π -FET is the piezoelectric coefficient, hence its polarization-field loop should be as high as possible (e.g., PZT (lead-zirconate-titanate)). In summary, literature reports indicate that the NC-FET shows better performance in terms of subthreshold swing and on-current. However, since its operation principle is based on a relatively large change in polarization the maximum speed, unlike in a π -FET, forms a big issue. Therefore, for future low-power CMOS, a hybrid solution is proposed comprising both device architectures on a chip where hard ferroelectric materials with a high piezocoefficient are used. Full article
(This article belongs to the Special Issue Miniaturized Transistors)
Figures

Figure 1

Open AccessArticle
Accelerating Flux Calculations Using Sparse Sampling
Micromachines 2018, 9(11), 550; https://doi.org/10.3390/mi9110550
Received: 20 September 2018 / Revised: 18 October 2018 / Accepted: 23 October 2018 / Published: 26 October 2018
Cited by 1 | PDF Full-text (4469 KB) | HTML Full-text | XML Full-text
Abstract
The ongoing miniaturization in electronics poses various challenges in the designing of modern devices and also in the development and optimization of the corresponding fabrication processes. Computer simulations offer a cost- and time-saving possibility to investigate and optimize these fabrication processes. However, modern [...] Read more.
The ongoing miniaturization in electronics poses various challenges in the designing of modern devices and also in the development and optimization of the corresponding fabrication processes. Computer simulations offer a cost- and time-saving possibility to investigate and optimize these fabrication processes. However, modern device designs require complex three-dimensional shapes, which significantly increases the computational complexity. For instance, in high-resolution topography simulations of etching and deposition, the evaluation of the particle flux on the substrate surface has to be re-evaluated in each timestep. This re-evaluation dominates the overall runtime of a simulation. To overcome this bottleneck, we introduce a method to enhance the performance of the re-evaluation step by calculating the particle flux only on a subset of the surface elements. This subset is selected using an advanced multi-material iterative partitioning scheme, taking local flux differences as well as geometrical variations into account. We show the applicability of our approach using an etching simulation of a dielectric layer embedded in a multi-material stack. We obtain speedups ranging from 1.8 to 8.0, with surface deviations being below two grid cells (0.6–3% of the size of the etched feature) for all tested configurations, both underlining the feasibility of our approach. Full article
(This article belongs to the Special Issue Miniaturized Transistors)
Figures

Figure 1

Review

Jump to: Editorial, Research

Open AccessReview
Modeling of Gate Stack Patterning for Advanced Technology Nodes: A Review
Micromachines 2018, 9(12), 631; https://doi.org/10.3390/mi9120631
Received: 7 November 2018 / Revised: 20 November 2018 / Accepted: 25 November 2018 / Published: 29 November 2018
Cited by 1 | PDF Full-text (6287 KB) | HTML Full-text | XML Full-text
Abstract
Semiconductor device dimensions have been decreasing steadily over the past several decades, generating the need to overcome fundamental limitations of both the materials they are made of and the fabrication techniques used to build them. Modern metal gates are no longer a simple [...] Read more.
Semiconductor device dimensions have been decreasing steadily over the past several decades, generating the need to overcome fundamental limitations of both the materials they are made of and the fabrication techniques used to build them. Modern metal gates are no longer a simple polysilicon layer, but rather consist of a stack of several different materials, often requiring multiple processing steps each, to obtain the characteristics needed for stable operation. In order to better understand the underlying mechanics and predict the potential of new methods and materials, technology computer aided design has become increasingly important. This review will discuss the fundamental methods, used to describe expected topology changes, and their respective benefits and limitations. In particular, common techniques used for effective modeling of the transport of molecular entities using numerical particle ray tracing in the feature scale region will be reviewed, taking into account the limitations they impose on chemical modeling. The modeling of surface chemistries and recent advances therein, which have enabled the identification of dominant etch mechanisms and the development of sophisticated chemical models, is further presented. Finally, recent advances in the modeling of gate stack pattering using advanced geometries in the feature scale are discussed, taking note of the underlying methods and their limitations, which still need to be overcome and are actively investigated. Full article
(This article belongs to the Special Issue Miniaturized Transistors)
Figures

Figure 1

Open AccessReview
A Review for Compact Model of Thin-Film Transistors (TFTs)
Micromachines 2018, 9(11), 599; https://doi.org/10.3390/mi9110599
Received: 16 October 2018 / Revised: 7 November 2018 / Accepted: 9 November 2018 / Published: 15 November 2018
Cited by 1 | PDF Full-text (9106 KB) | HTML Full-text | XML Full-text
Abstract
Thin-film transistors (TFTs) have grown into a huge industry due to their broad applications in display, radio-frequency identification tags (RFID), logical calculation, etc. In order to bridge the gap between the fabrication process and the circuit design, compact model plays an indispensable role [...] Read more.
Thin-film transistors (TFTs) have grown into a huge industry due to their broad applications in display, radio-frequency identification tags (RFID), logical calculation, etc. In order to bridge the gap between the fabrication process and the circuit design, compact model plays an indispensable role in the development and application of TFTs. The purpose of this review is to provide a theoretical description of compact models of TFTs with different active layers, such as polysilicon, amorphous silicon, organic and In-Ga-Zn-O (IGZO) semiconductors. Special attention is paid to the surface-potential-based compact models of silicon-based TFTs. With the understanding of both the charge transport characteristics and the requirement of TFTs in organic and IGZO TFTs, we have proposed the surface-potential-based compact models and the parameter extraction techniques. The proposed models can provide accurate circuit-level performance prediction and RFID circuit design, and pass the Gummel symmetry test (GST). Finally; the outlook on the compact models of TFTs is briefly discussed. Full article
(This article belongs to the Special Issue Miniaturized Transistors)
Figures

Figure 1

Micromachines EISSN 2072-666X Published by MDPI AG, Basel, Switzerland RSS E-Mail Table of Contents Alert
Back to Top