#
Variability Predictions for the Next Technology Generations of n-type Si_{x}Ge_{1−x} Nanowire MOSFETs

^{*}

## Abstract

**:**

## 1. Introduction

## 2. Simulation Framework

#### 2.1. Device Structure with the Variability Sources Included

#### 2.2. Quantum Transport Formalism

#### 2.3. Extraction of Effective Masses

## 3. Simulation Results and Discussion

## 4. Conclusions

## Author Contributions

## Funding

## Conflicts of Interest

## References

- IEEE International Roadmap for Devices and Systems (IRDS). 2016. Available online: https://irds.ieee.org/reports (accessed on 25 September 2018).
- Kawaura, H.; Sakamoto, T.; Baba, T. Observation of source-to-drain direct tunneling current in 8 nm gate electrically variable shallow junction metal–oxide–semiconductor field-effect transistors. Appl. Phys. Lett.
**2000**, 76, 3810–3812. [Google Scholar] [CrossRef] - Grillet, C.; Logoteta, D.; Cresti, A.; Pala, M.G. Assessment of the Electrical Performance of Short Channel InAs and Strained Si Nanowire FETs. IEEE Trans. Electron Devices
**2017**, 64, 2425–2431. [Google Scholar] [CrossRef] - Badami, O.; Caruso, E.; Lizzit, D.; Osgnach, P.; Esseni, D.; Palestri, P.; Selmi, L. An Improved Surface Roughness Scattering Model for Bulk, Thin-Body, and Quantum-Well MOSFETs. IEEE Trans. Electron Devices
**2016**, 63, 2306–2312. [Google Scholar] [CrossRef] - Al-Ameri, T.; Georgiev, V.P.; Adamu-Lema, F.; Asenov, A. Simulation study of vertically stacked lateral Si nanowires transistors for 5 nm CMOS applications. IEEE J. Electron Devices Soc.
**2017**, 2017 5, 466–472. [Google Scholar] [CrossRef] - Maheshwaram, S.; Manhas, S.K.; Kaushal, G.; Anand, B.; Singh, N. Vertical Silicon Nanowire Gate-All-Around Field Effect Transistor Based Nanoscale CMOS. IEEE Electron Device Lett.
**2011**, 32, 1011–1013. [Google Scholar] [CrossRef] - Zheng, G.; Lu, W.; Jin, S.; Lieber, C.M. Synthesis and Fabrication of High-Performance n-Type Silicon Nanowire Transistors. Adv. Mater.
**2004**, 16, 830–834. [Google Scholar] [CrossRef] - Tian, B.; Cohen-Karni, T.; Qing, Q.; Duan, X.; Xie, P.; Lieber, C. Three-Dimensional, Flexible Nanoscale Field-Effect Transistors as Localized Bioprobes. Science
**2010**, 329, 1890–1893. [Google Scholar] [CrossRef] - Kim, S.K.; Day, R.W.; Cahoon, J.F.; Kempa, T.J.; Song, K.D.; Park, H.G.; Lieber, C.M. Tuning Light Absorption in Core/Shell Silicon Nanowire Photovoltaic Devices through Morphological Design. Nano Lett.
**2012**, 12, 4971–4976. [Google Scholar] [CrossRef] [Green Version] - Kim, J.; Lee, H.C.; Kim, K.H.; Hwang, M.S.; Park, J.S.; Lee, J.M.; So, J.P.; Choi, J.H.; Kwon, S.H.; Barrelet, C.J.; et al. Photon-triggered nanowire transistors. Nat. Nanotechnol.
**2017**, 12, 963–968. [Google Scholar] [CrossRef] - Vasen, T.; Ramvall, P.; Afzalian, A.; Thelander, C.; Dick, K.A.; Holland, M.; Doornbos, G.; Wang, S.W.; Oxland, R.; Vellianitis, G.; et al. InAs nanowire GAA n-MOSFETs with 12–15 nm diameter. In Proceedings of the 2016 IEEE Symposium on VLSI Technology, Honolulu, HI, USA, 14–16 June 2016; pp. 1–2. [Google Scholar] [CrossRef]
- Selvakumar, C.S.; Hecht, B. SiGe-channel n-MOSFET by germanium implantation. IEEE Electron Device Lett.
**1991**, 12, 444–446. [Google Scholar] [CrossRef] - Lee, J.; Shin, M. Performance Assessment of III-V Channel Ultra-Thin-Body Schottky-Barrier MOSFETs. IEEE Electron Device Lett.
**2014**, 35, 726–728. [Google Scholar] [CrossRef] - Radisavljevic, B.; Radenovic, A.; Brivio, J.; Giacometti, V.; Kis, A. Single-layer MoS2 transistors. Nat. Nanotechnol.
**2011**, 6, 147–150. [Google Scholar] [CrossRef] [PubMed] [Green Version] - Alher, M.; Mosleh, A.; Cousar, L.; Dou, W.; Grant, P.C.; Ghetmiri, S.A.; AlKabi, S.; Du, W.; Benamara, M.; Li, B.; et al. CMOS Compatible Growth of High Quality Ge, SiGe and SiGeSn for Photonic Device Applications. ECS Trans.
**2015**, 69, 269–278. [Google Scholar] [CrossRef] - Seoane, N.; Indalecio, G.; Comesaña, E.; Aldegunde, M.; García-Loureiro, A.J.; Kalna, K. Random Dopant, Line-Edge Roughness, and Gate Workfunction Variability in a Nano InGaAs FinFET. IEEE Trans. Electron Devices
**2014**, 61, 466–472. [Google Scholar] [CrossRef] - Valin, R.; Martinez, A.; Barker, J. Non-equilibrium Green’s functions study of discrete dopants variability on an ultra-scaled FinFET. J. Appl. Phys.
**2015**, 117, 164505. [Google Scholar] [CrossRef] - Georgiev, V.P.; Towie, E.A.; Asenov, A. Impact of precisely positioned dopants on the performance of an ultimate silicon nanowire transistor: A full three-dimensional NEGF simulation study. IEEE Trans. Electron Devices
**2013**, 60, 965–971. [Google Scholar] [CrossRef] - Berrada, S.; Carrillo-Nuñez, H.; Lee, J.; Medina-Bailon, C.; Dutta, T.; Duan, M.; Adamu-Lema, F.; Georgiev, V.; Asenov, A. NESS: New Flexible Nano-Transistor Simulation Environment. In Proceedings of the International Conference on Simulation of Semiconductor Processes and Devices 2018, Austin, TX, USA, 24–26 September 2018. [Google Scholar]
- Frank, D.J.; Taur, Y.; Ieong, M.; Wong, H.-S. Monte Carlo modeling of threshold variation due to dopant fluctuations. In Proceedings of the 1999 Symposium on VLSI Technology Digest of Technical Papers, Kyoto, Japan, 14–16 June 1999; pp. 169–170. [Google Scholar] [CrossRef]
- Asenov, A. Random dopant induced threshold voltage lowering and fluctuations in sub 50 nm MOSFETs: A statistical 3D `atomistic’ simulation study. Nanotechnology
**1999**, 10, 153–158. [Google Scholar] [CrossRef] - Kim, S.; Luisier, M.; Paul, A.; Boykin, T.B.; Klimeck, G. Full Three-Dimensional Quantum Transport Simulation of Atomistic Interface Roughness in Silicon Nanowire FETs. IEEE Trans. Electron Devices
**2011**, 58, 1371–1380. [Google Scholar] [CrossRef] [Green Version] - Goodnick, S.M. Surface roughness at the Si(100)-SiO
_{2}interface. Phys. Rev. B**1985**, 32, 8171–8186. [Google Scholar] [CrossRef] - Wang, X.; Brown, A.R.; Idris, N.; Markov, S.; Roy, G.; Asenov, A. Statistical Threshold-Voltage Variability in Scaled Decananometer Bulk HKMG MOSFETs: A Full-Scale 3-D Simulation Scaling Study. IEEE Trans. Electron Devices
**2011**, 58, 2293–2301. [Google Scholar] [CrossRef] - Vardhan, P.H.; Mittal, S.; Ganguly, S.; Ganguly, U. Analytical Estimation of Threshold Voltage Variability by Metal Gate Granularity in FinFET. IEEE Trans. Electron Devices
**2017**, 64, 3071–3076. [Google Scholar] [CrossRef] - Dadgour, H.; Endo, K.; De, V.; Banerjee, K. Modeling and analysis of grain-orientation effects in emerging metal-gate devices and implications for SRAM reliability. In Proceedings of the 2008 IEEE International Electron Devices Meeting, San Francisco, CA, USA, 15–17 December 2008; pp. 1–4. [Google Scholar] [CrossRef]
- Loubet, N.; Hook, T.; Montanini, P.; Yeung, C.; Kanakasabapathy, S.; Guillom, M.; Yamashita, T.; Zhang, J.; Miao, X.; Wang, J.; et al. Stacked nanosheet gate-all-around transistor to enable scaling beyond FinFET. In Proceedings of the 2017 IEEE Symposium on VLSI Technology, Kyoto, Japan, 5–8 June 2017; pp. T230–T231. [Google Scholar]
- Luisier, M.; Schenk, A.; Fichtner, W. Quantum transport in two- and three-dimensional nanoscale transistors: Coupled mode effects in the nonequilibrium Green’s function formalism. J. Appl. Phys.
**2006**, 100, 043713. [Google Scholar] [CrossRef] - Lopez-Sancho, M.P.; Lopez-Sancho, J.M.; Sancho, J.M.L.; Rubio, J. Highly convergent schemes for the calculation of bulk and surface Green functions. J. Phys. F Met. Phys.
**1985**, 15, 851. [Google Scholar] [CrossRef] - Svizhenko, A.; Anantram, M.P. Role of scattering in nanotransistors. IEEE Trans. Electron Devices
**2003**, 50, 1459–1466. [Google Scholar] [CrossRef] [Green Version] - Atomistix Toolkit Version 2017.2, Synopsys QuantumWise A/S. Available online: https://www.quantumwise.com (accessed on 25 September 2018).
- Timothy, T.; Klimeck, G.; Oyafuso, F. Valence band effective-mass expressions in the sp3d5s* empirical tight-binding model applied to a Si and Ge parametrization. Phys. Rev. B
**2004**, 69, 115201. [Google Scholar] [CrossRef] - Paul, A.; Mehrotra, S.; Luisier, M.; Klimeck, G. Performance Prediction of Ultrascaled SiGe/Si Core/Shell Electron and Hole Nanowire MOSFETs. IEEE Electron Device Lett.
**2010**, 31, 278–280. [Google Scholar] [CrossRef] - Fischetti, M.V.; Laux, S.E. Band structure, deformation potentials, and carrier mobility in strained Si, Ge, and SiGe alloys. J. Appl. Phys.
**1996**, 80, 2234–2252. [Google Scholar] [CrossRef]

**Figure 1.**Schematic diagram of the elliptical gate-all-around nanowire metal-oxide-semiconductor field-effect transistors (GAA NWFET) (a = 3 nm and b = 5 nm) highlighting variability sources. For the square and circular nanowires (NWs), a = b = 5 nm. ${L}_{\mathrm{S}}$ = ${L}_{\mathrm{D}}$ = 28 nm, ${L}_{\mathrm{G}}$ = 10 nm, and ${L}_{\mathrm{V}}$ = 26 nm. The doping concentrations in source/drain and channel regions are 10

^{20}(n-type) and 10

^{15}(p-type) cm

^{−3}, respectively. RDD–random discrete dopants, LER–line edge roughness and MGG–metal gate granularity.

**Figure 2.**Band structures of (

**a**) Si and (

**b**) ${\mathrm{Si}}_{0.2}{\mathrm{Ge}}_{0.8}5\times 3$ nm

^{2}elliptical NWs. The bulk conduction band edge is set to 0.0 eV. $\Delta {E}_{Q}$ is also remarked.

**Figure 3.**Transfer characteristics of ${\mathrm{Si}}_{0.2}{\mathrm{Ge}}_{0.8}$ elliptical GAA NWFETs associated with (

**a**) random discrete dopants (RDD), (

**b**) RDD and line edge roughness (LER) and (

**c**) RDD, LER and metal gate granularity (MGG. The ideal device refers to a device with continuous and uniform doping profiles in the source and drain and no variability sources. Corresponding standard deviation of ${V}_{\mathrm{th}}\sigma \left({V}_{\mathrm{th}}\right)$ is also indicated. ${V}_{\mathrm{DS}}$ = 0.6 V.

**Figure 4.**Distributions of threshold voltage (${V}_{\mathrm{th}}$) for the elliptical NWFETs with different mole fractions. RDD, LER, and MGG are taken into account.

**Figure 5.**Correlation between important FoMs for the elliptical GAA NWFETs with different Ge mole fraction. The bottom left of the table shows correlation scatter plots and the top right shows correlation coefficients which are also listed in the following order: Si (blue), ${\mathrm{Si}}_{0.8}{\mathrm{Ge}}_{0.2}$ (magenta), ${\mathrm{Si}}_{0.5}{\mathrm{Ge}}_{0.5}$ (red), and ${\mathrm{Si}}_{0.2}{\mathrm{Ge}}_{0.8}$ (black).

**Figure 6.**Dependence of ${V}_{\mathrm{th}}$ of the elliptical GAA NWFETs on the variability sources and the Ge mole fraction.

**Figure 7.**Dependence of (

**a**) ${V}_{\mathrm{th}}$ and (

**b**) drain induced barrier lowering (DIBL) on the Ge mole fraction and cross-sectional shape. RDD, LER, and MGG are considered

**Table 1.**Calculated effective masses of Si and ${\mathrm{Si}}_{x}{\mathrm{Ge}}_{1-x}$ nanowires (NWs) with various cross-sectional shapes. Herein, unit is ${m}_{0}$, the rest electron mass.

Degeneracy | Square | Circle | Ellipse | ||||||||
---|---|---|---|---|---|---|---|---|---|---|---|

${\mathit{m}}_{\mathit{x}}$ | ${\mathit{m}}_{\mathit{y}}$ | ${\mathit{m}}_{\mathit{z}}$ | ${\mathit{m}}_{\mathit{x}}$ | ${\mathit{m}}_{\mathit{y}}$ | ${\mathit{m}}_{\mathit{z}}$ | ${\mathit{m}}_{\mathit{x}}$ | ${\mathit{m}}_{\mathit{y}}$ | ${\mathit{m}}_{\mathit{z}}$ | |||

Si | ${\Delta}_{x}$ | 2 | 0.918 | 0.240 | 0.240 | 0.915 | 0.224 | 0.224 | 0.927 | 0.464 | 0.146 |

${\Delta}_{y}$ | 2 | 0.233 | 0.953 | 0.237 | 0.236 | 0.887 | 0.215 | 0.241 | 0.839 | 0.220 | |

${\Delta}_{z}$ | 2 | 0.233 | 0.242 | 0.875 | 0.236 | 0.208 | 0.896 | 0.241 | 0.206 | 0.886 | |

${\mathrm{Si}}_{0.8}{\mathrm{Ge}}_{0.2}$ | ${\Delta}_{x}$ | 2 | 0.861 | 0.235 | 0.235 | 0.849 | 0.287 | 0.287 | 0.875 | 0.321 | 0.198 |

${\Delta}_{y}$ | 2 | 0.240 | 0.884 | 0.221 | 0.235 | 1.342 | 0.262 | 0.251 | 0.757 | 0.224 | |

${\Delta}_{z}$ | 2 | 0.240 | 0.220 | 0.885 | 0.235 | 0.259 | 1.366 | 0.251 | 0.192 | 0.905 | |

${\mathrm{Si}}_{0.5}{\mathrm{Ge}}_{0.5}$ | ${\Delta}_{x}$ | 2 | 0.799 | 0.241 | 0.241 | 0.788 | 0.286 | 0.286 | 0.818 | 0.392 | 0.179 |

${\Delta}_{y}$ | 2 | 0.250 | 0.864 | 0.224 | 0.247 | 1.042 | 0.272 | 0.268 | 0.674 | 0.210 | |

${\Delta}_{z}$ | 2 | 0.250 | 0.224 | 0.816 | 0.247 | 0.270 | 1.015 | 0.268 | 0.194 | 0.809 | |

${\mathrm{Si}}_{0.2}{\mathrm{Ge}}_{0.8}$ | ${\Delta}_{x}$ | 2 | 0.759 | 0.237 | 0.237 | 0.739 | 0.285 | 0.285 | 0.788 | 0.448 | 0.174 |

${\Delta}_{y}$ | 2 | 0.266 | 0.788 | 0.217 | 0.258 | 0.952 | 0.272 | 0.286 | 0.657 | 0.206 | |

${\Delta}_{z}$ | 2 | 0.266 | 0.213 | 0.798 | 0.258 | 0.272 | 0.958 | 0.286 | 0.186 | 0.828 | |

L | 4 | 0.350 | 0.134 | 0.297 | 0.500 | 0.147 | 0.449 | 0.600 | 0.327 | 0.152 |

**Table 2.**Medians of ${I}_{\mathrm{ON}}$ and ${I}_{\mathrm{OFF}}$ for the ${\mathrm{Si}}_{x}{\mathrm{Ge}}_{1-x}$ nanowire metal-oxide-semiconductor field-effect transistors (NWFETs). Random discrete dopants (RDD), line edge roughness (LER), and metal gate granularity (MGG) are considered.

${\mathbf{Si}}_{\mathit{x}}{\mathbf{Ge}}_{1-\mathit{x}}$ | ${\mathit{I}}_{\mathit{ON}}$ (mA/μm)/${\mathit{I}}_{\mathit{OFF}}$ (pA/μm) | ||
---|---|---|---|

Square | Circular | Elliptical | |

Si | 1.59/397 | 1.37/98.9 | 0.771/9.26 |

${\mathrm{Si}}_{0.8}{\mathrm{Ge}}_{0.2}$ | 1.71/427 | 1.50/127 | 0.862/11.7 |

${\mathrm{Si}}_{0.5}{\mathrm{Ge}}_{0.5}$ | 1.70/473 | 1.51/151 | 0.861/12.7 |

${\mathrm{Si}}_{0.2}{\mathrm{Ge}}_{0.8}$ | 1.84/668 | 1.63/210 | 0.958/18.1 |

**Table 3.**The comparison of drain induced barrier lowering (DIBL) in ${\mathrm{Si}}_{0.2}{\mathrm{Ge}}_{0.8}$ channel devices obtained from the ideal devices and statistical simulations.

Cross-Sectional Shape (RDD + LER + MGG) | Ideal Device | Median |
---|---|---|

Square | 62.4 mV/V | 64.7 mV/V |

Circle | 42.8 mV/V | 50.2 mV/V |

Ellipse | 20.3 mV/V | 29.2 mV/V |

© 2018 by the authors. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (http://creativecommons.org/licenses/by/4.0/).

## Share and Cite

**MDPI and ACS Style**

Lee, J.; Badami, O.; Carrillo-Nuñez, H.; Berrada, S.; Medina-Bailon, C.; Dutta, T.; Adamu-Lema, F.; Georgiev, V.P.; Asenov, A.
Variability Predictions for the Next Technology Generations of *n*-type Si_{x}Ge_{1−x} Nanowire MOSFETs. *Micromachines* **2018**, *9*, 643.
https://doi.org/10.3390/mi9120643

**AMA Style**

Lee J, Badami O, Carrillo-Nuñez H, Berrada S, Medina-Bailon C, Dutta T, Adamu-Lema F, Georgiev VP, Asenov A.
Variability Predictions for the Next Technology Generations of *n*-type Si_{x}Ge_{1−x} Nanowire MOSFETs. *Micromachines*. 2018; 9(12):643.
https://doi.org/10.3390/mi9120643

**Chicago/Turabian Style**

Lee, Jaehyun, Oves Badami, Hamilton Carrillo-Nuñez, Salim Berrada, Cristina Medina-Bailon, Tapas Dutta, Fikru Adamu-Lema, Vihar P. Georgiev, and Asen Asenov.
2018. "Variability Predictions for the Next Technology Generations of *n*-type Si_{x}Ge_{1−x} Nanowire MOSFETs" *Micromachines* 9, no. 12: 643.
https://doi.org/10.3390/mi9120643