Process Variability—Technological Challenge and Design Issue for Nanoscale Devices
1
Fraunhofer Institut für Integrierte Systeme und Bauelementetechnologie, Schottkystrasse 10, 91058 Erlangen, Germany
2
CEA, LETI, MINATEC campus and Univ. Grenoble Alpes, 38054 Grenoble, France
3
Synopsys Northern Europe Ltd., Glasgow G3 8HB, UK
*
Author to whom correspondence should be addressed.
Micromachines 2019, 10(1), 6; https://doi.org/10.3390/mi10010006
Received: 8 December 2018 / Revised: 14 December 2018 / Accepted: 15 December 2018 / Published: 23 December 2018
(This article belongs to the Special Issue Miniaturized Transistors)
Current advanced transistor architectures, such as FinFETs and (stacked) nanowires and nanosheets, employ truly three-dimensional architectures. Already for aggressively scaled bulk transistors, both statistical and systematic process variations have critically influenced device and circuit performance. Three-dimensional device architectures make the control and optimization of the device geometries even more important, both in view of the nominal electrical performance to be achieved and its variations. In turn, it is essential to accurately simulate the device geometry and its impact on the device properties, including the effect caused by non-idealized processes which are subject to various kinds of systematic variations induced by process equipment. In this paper, the hierarchical simulation system developed in the SUPERAID7 project to study the impact of variations from equipment to circuit level is presented. The software system consists of a combination of existing commercial and newly developed tools. As the paper focuses on technological challenges, especially issues resulting from the structuring processes needed to generate the three-dimensional device architectures are discussed. The feasibility of a full simulation of the impact of relevant systematic and stochastic variations on advanced devices and circuits is demonstrated.
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Keywords:
process simulation; device simulation; compact models; process variations; systematic variations; statistical variations; FinFETs; nanowires; nanosheets
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MDPI and ACS Style
Lorenz, J.; Bär, E.; Barraud, S.; Brown, A.R.; Evanschitzky, P.; Klüpfel, F.; Wang, L. Process Variability—Technological Challenge and Design Issue for Nanoscale Devices. Micromachines 2019, 10, 6. https://doi.org/10.3390/mi10010006
AMA Style
Lorenz J, Bär E, Barraud S, Brown AR, Evanschitzky P, Klüpfel F, Wang L. Process Variability—Technological Challenge and Design Issue for Nanoscale Devices. Micromachines. 2019; 10(1):6. https://doi.org/10.3390/mi10010006
Chicago/Turabian StyleLorenz, Jürgen, Eberhard Bär, Sylvain Barraud, Andrew R. Brown, Peter Evanschitzky, Fabian Klüpfel, and Liping Wang. 2019. "Process Variability—Technological Challenge and Design Issue for Nanoscale Devices" Micromachines 10, no. 1: 6. https://doi.org/10.3390/mi10010006
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